1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/read.h> 15 #include <linux/list.h> 16 #include <syscon.h> 17 #include <asm/arch-rockchip/clock.h> 18 #include <asm/gpio.h> 19 20 #include "rockchip_display.h" 21 #include "rockchip_crtc.h" 22 #include "rockchip_connector.h" 23 #include "analogix_dp.h" 24 25 /** 26 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 27 * @lcdsel_grf_reg: grf register offset of lcdc select 28 * @lcdsel_big: reg value of selecting vop big for eDP 29 * @lcdsel_lit: reg value of selecting vop little for eDP 30 */ 31 struct rockchip_dp_chip_data { 32 u32 lcdsel_grf_reg; 33 u32 lcdsel_big; 34 u32 lcdsel_lit; 35 u32 chip_type; 36 bool has_vop_sel; 37 }; 38 39 static void 40 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 41 bool enable) 42 { 43 u8 data; 44 45 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 46 47 if (enable) 48 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 49 DP_LANE_COUNT_ENHANCED_FRAME_EN | 50 DPCD_LANE_COUNT_SET(data)); 51 else 52 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 53 DPCD_LANE_COUNT_SET(data)); 54 } 55 56 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 57 { 58 u8 data; 59 int retval; 60 61 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 62 retval = DPCD_ENHANCED_FRAME_CAP(data); 63 64 return retval; 65 } 66 67 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 68 { 69 u8 data; 70 71 data = analogix_dp_is_enhanced_mode_available(dp); 72 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 73 analogix_dp_enable_enhanced_mode(dp, data); 74 } 75 76 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 77 { 78 analogix_dp_set_training_pattern(dp, DP_NONE); 79 80 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 81 DP_TRAINING_PATTERN_DISABLE); 82 } 83 84 static int analogix_dp_link_start(struct analogix_dp_device *dp) 85 { 86 u8 buf[4]; 87 int lane, lane_count, retval; 88 89 lane_count = dp->link_train.lane_count; 90 91 dp->link_train.lt_state = CLOCK_RECOVERY; 92 dp->link_train.eq_loop = 0; 93 94 for (lane = 0; lane < lane_count; lane++) 95 dp->link_train.cr_loop[lane] = 0; 96 97 /* Set link rate and count as you want to establish*/ 98 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 99 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 100 101 /* Setup RX configuration */ 102 buf[0] = dp->link_train.link_rate; 103 buf[1] = dp->link_train.lane_count; 104 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 105 if (retval) 106 return retval; 107 108 /* Set TX voltage-swing and pre-emphasis to minimum */ 109 for (lane = 0; lane < lane_count; lane++) 110 dp->link_train.training_lane[lane] = 111 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 112 DP_TRAIN_PRE_EMPH_LEVEL_0; 113 analogix_dp_set_lane_link_training(dp); 114 115 /* Set training pattern 1 */ 116 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 117 118 /* Set RX training pattern */ 119 retval = analogix_dp_write_byte_to_dpcd(dp, 120 DP_TRAINING_PATTERN_SET, 121 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 122 if (retval) 123 return retval; 124 125 for (lane = 0; lane < lane_count; lane++) 126 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 127 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 128 129 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 130 lane_count, buf); 131 132 return retval; 133 } 134 135 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 136 { 137 int shift = (lane & 1) * 4; 138 u8 link_value = link_status[lane >> 1]; 139 140 return (link_value >> shift) & 0xf; 141 } 142 143 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 144 { 145 int lane; 146 u8 lane_status; 147 148 for (lane = 0; lane < lane_count; lane++) { 149 lane_status = analogix_dp_get_lane_status(link_status, lane); 150 if ((lane_status & DP_LANE_CR_DONE) == 0) 151 return -EINVAL; 152 } 153 return 0; 154 } 155 156 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 157 int lane_count) 158 { 159 int lane; 160 u8 lane_status; 161 162 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 163 return -EINVAL; 164 165 for (lane = 0; lane < lane_count; lane++) { 166 lane_status = analogix_dp_get_lane_status(link_status, lane); 167 lane_status &= DP_CHANNEL_EQ_BITS; 168 if (lane_status != DP_CHANNEL_EQ_BITS) 169 return -EINVAL; 170 } 171 172 return 0; 173 } 174 175 static unsigned char 176 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 177 { 178 int shift = (lane & 1) * 4; 179 u8 link_value = adjust_request[lane >> 1]; 180 181 return (link_value >> shift) & 0x3; 182 } 183 184 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 185 u8 adjust_request[2], 186 int lane) 187 { 188 int shift = (lane & 1) * 4; 189 u8 link_value = adjust_request[lane >> 1]; 190 191 return ((link_value >> shift) & 0xc) >> 2; 192 } 193 194 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 195 { 196 analogix_dp_training_pattern_dis(dp); 197 analogix_dp_set_enhanced_mode(dp); 198 199 dp->link_train.lt_state = FAILED; 200 } 201 202 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 203 u8 adjust_request[2]) 204 { 205 int lane, lane_count; 206 u8 voltage_swing, pre_emphasis, training_lane; 207 208 lane_count = dp->link_train.lane_count; 209 for (lane = 0; lane < lane_count; lane++) { 210 voltage_swing = analogix_dp_get_adjust_request_voltage( 211 adjust_request, lane); 212 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 213 adjust_request, lane); 214 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 215 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 216 217 if (voltage_swing == VOLTAGE_LEVEL_3) 218 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 219 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 220 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 221 222 dp->link_train.training_lane[lane] = training_lane; 223 } 224 } 225 226 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 227 { 228 int lane, lane_count, retval; 229 u8 voltage_swing, pre_emphasis, training_lane; 230 u8 link_status[2], adjust_request[2]; 231 232 udelay(101); 233 234 lane_count = dp->link_train.lane_count; 235 236 retval = analogix_dp_read_bytes_from_dpcd(dp, 237 DP_LANE0_1_STATUS, 2, link_status); 238 if (retval) 239 return retval; 240 241 retval = analogix_dp_read_bytes_from_dpcd(dp, 242 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 243 if (retval) 244 return retval; 245 246 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 247 /* set training pattern 2 for EQ */ 248 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 249 250 retval = analogix_dp_write_byte_to_dpcd(dp, 251 DP_TRAINING_PATTERN_SET, 252 DP_LINK_SCRAMBLING_DISABLE | 253 DP_TRAINING_PATTERN_2); 254 if (retval) 255 return retval; 256 257 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 258 dp->link_train.lt_state = EQUALIZER_TRAINING; 259 } else { 260 for (lane = 0; lane < lane_count; lane++) { 261 training_lane = analogix_dp_get_lane_link_training( 262 dp, lane); 263 voltage_swing = analogix_dp_get_adjust_request_voltage( 264 adjust_request, lane); 265 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 266 adjust_request, lane); 267 268 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 269 voltage_swing && 270 DPCD_PRE_EMPHASIS_GET(training_lane) == 271 pre_emphasis) 272 dp->link_train.cr_loop[lane]++; 273 274 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 275 voltage_swing == VOLTAGE_LEVEL_3 || 276 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 277 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 278 dp->link_train.cr_loop[lane], 279 voltage_swing, pre_emphasis); 280 analogix_dp_reduce_link_rate(dp); 281 return -EIO; 282 } 283 } 284 } 285 286 analogix_dp_get_adjust_training_lane(dp, adjust_request); 287 analogix_dp_set_lane_link_training(dp); 288 289 retval = analogix_dp_write_bytes_to_dpcd(dp, 290 DP_TRAINING_LANE0_SET, lane_count, 291 dp->link_train.training_lane); 292 if (retval) 293 return retval; 294 295 return retval; 296 } 297 298 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 299 { 300 int lane_count, retval; 301 u32 reg; 302 u8 link_align, link_status[2], adjust_request[2]; 303 304 udelay(401); 305 306 lane_count = dp->link_train.lane_count; 307 308 retval = analogix_dp_read_bytes_from_dpcd(dp, 309 DP_LANE0_1_STATUS, 2, link_status); 310 if (retval) 311 return retval; 312 313 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 314 analogix_dp_reduce_link_rate(dp); 315 return -EIO; 316 } 317 318 retval = analogix_dp_read_bytes_from_dpcd(dp, 319 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 320 if (retval) 321 return retval; 322 323 retval = analogix_dp_read_byte_from_dpcd(dp, 324 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 325 if (retval) 326 return retval; 327 328 analogix_dp_get_adjust_training_lane(dp, adjust_request); 329 330 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 331 /* traing pattern Set to Normal */ 332 analogix_dp_training_pattern_dis(dp); 333 334 printf("Link Training success!\n"); 335 336 analogix_dp_get_link_bandwidth(dp, ®); 337 dp->link_train.link_rate = reg; 338 analogix_dp_get_lane_count(dp, ®); 339 dp->link_train.lane_count = reg; 340 341 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 342 dp->link_train.link_rate, dp->link_train.lane_count); 343 344 /* set enhanced mode if available */ 345 analogix_dp_set_enhanced_mode(dp); 346 dp->link_train.lt_state = FINISHED; 347 348 return 0; 349 } 350 351 /* not all locked */ 352 dp->link_train.eq_loop++; 353 354 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 355 dev_dbg(dp->dev, "EQ Max loop\n"); 356 analogix_dp_reduce_link_rate(dp); 357 return -EIO; 358 } 359 360 analogix_dp_set_lane_link_training(dp); 361 362 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 363 lane_count, dp->link_train.training_lane); 364 365 return retval; 366 } 367 368 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 369 u8 *bandwidth) 370 { 371 u8 data; 372 373 /* 374 * For DP rev.1.1, Maximum link rate of Main Link lanes 375 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 376 * For DP rev.1.2, Maximum link rate of Main Link lanes 377 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 378 */ 379 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 380 *bandwidth = data; 381 } 382 383 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 384 u8 *lane_count) 385 { 386 u8 data; 387 388 /* 389 * For DP rev.1.1, Maximum number of Main Link lanes 390 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 391 */ 392 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 393 *lane_count = DPCD_MAX_LANE_COUNT(data); 394 } 395 396 static int analogix_dp_init_training(struct analogix_dp_device *dp, 397 enum link_lane_count_type max_lane, 398 int max_rate) 399 { 400 /* 401 * MACRO_RST must be applied after the PLL_LOCK to avoid 402 * the DP inter pair skew issue for at least 10 us 403 */ 404 analogix_dp_reset_macro(dp); 405 406 /* Initialize by reading RX's DPCD */ 407 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 408 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 409 410 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 411 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 412 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 413 dev_err(dp->dev, "failed to get Rx Max Link Rate\n"); 414 return -ENODEV; 415 } 416 417 if (dp->link_train.lane_count == 0) { 418 dev_err(dp->dev, "failed to get Rx Max Lane Count\n"); 419 return -ENODEV; 420 } 421 422 /* Setup TX lane count & rate */ 423 if (dp->link_train.lane_count > max_lane) 424 dp->link_train.lane_count = max_lane; 425 if (dp->link_train.link_rate > max_rate) 426 dp->link_train.link_rate = max_rate; 427 428 /* All DP analog module power up */ 429 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 430 431 return 0; 432 } 433 434 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 435 { 436 int retval = 0, training_finished = 0; 437 438 dp->link_train.lt_state = START; 439 440 /* Process here */ 441 while (!retval && !training_finished) { 442 switch (dp->link_train.lt_state) { 443 case START: 444 retval = analogix_dp_link_start(dp); 445 if (retval) 446 dev_err(dp->dev, "LT link start failed!\n"); 447 break; 448 case CLOCK_RECOVERY: 449 retval = analogix_dp_process_clock_recovery(dp); 450 if (retval) 451 dev_err(dp->dev, "LT CR failed!\n"); 452 break; 453 case EQUALIZER_TRAINING: 454 retval = analogix_dp_process_equalizer_training(dp); 455 if (retval) 456 dev_err(dp->dev, "LT EQ failed!\n"); 457 break; 458 case FINISHED: 459 training_finished = 1; 460 break; 461 case FAILED: 462 return -EREMOTEIO; 463 } 464 } 465 466 return retval; 467 } 468 469 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 470 u32 count, u32 bwtype) 471 { 472 int ret; 473 474 ret = analogix_dp_init_training(dp, count, bwtype); 475 if (ret < 0) { 476 dev_err(dp->dev, "failed to init training\n"); 477 return ret; 478 } 479 480 ret = analogix_dp_sw_link_training(dp); 481 if (ret < 0) { 482 dev_err(dp->dev, "failed to do sw link training\n"); 483 return ret; 484 } 485 486 return 0; 487 } 488 489 static int analogix_dp_config_video(struct analogix_dp_device *dp) 490 { 491 int timeout_loop = 0; 492 int done_count = 0; 493 494 analogix_dp_config_video_slave_mode(dp); 495 496 analogix_dp_set_video_color_format(dp); 497 498 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 499 dev_err(dp->dev, "PLL is not locked yet.\n"); 500 return -EINVAL; 501 } 502 503 for (;;) { 504 timeout_loop++; 505 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 506 break; 507 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 508 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 509 return -ETIMEDOUT; 510 } 511 512 udelay(2); 513 } 514 515 /* Set to use the register calculated M/N video */ 516 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 517 518 /* For video bist, Video timing must be generated by register */ 519 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 520 521 /* Disable video mute */ 522 analogix_dp_enable_video_mute(dp, 0); 523 524 /* Configure video slave mode */ 525 analogix_dp_enable_video_master(dp, 0); 526 527 /* Enable video input */ 528 analogix_dp_start_video(dp); 529 530 timeout_loop = 0; 531 532 for (;;) { 533 timeout_loop++; 534 if (analogix_dp_is_video_stream_on(dp) == 0) { 535 done_count++; 536 if (done_count > 10) 537 break; 538 } else if (done_count) { 539 done_count = 0; 540 } 541 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 542 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 543 return -ETIMEDOUT; 544 } 545 546 udelay(1001); 547 } 548 549 return 0; 550 } 551 552 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 553 bool enable) 554 { 555 u8 data; 556 557 if (enable) { 558 analogix_dp_enable_scrambling(dp); 559 560 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 561 &data); 562 analogix_dp_write_byte_to_dpcd(dp, 563 DP_TRAINING_PATTERN_SET, 564 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 565 } else { 566 analogix_dp_disable_scrambling(dp); 567 568 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 569 &data); 570 analogix_dp_write_byte_to_dpcd(dp, 571 DP_TRAINING_PATTERN_SET, 572 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 573 } 574 } 575 576 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 577 { 578 analogix_dp_reset(dp); 579 580 analogix_dp_swreset(dp); 581 582 analogix_dp_init_analog_param(dp); 583 analogix_dp_init_interrupt(dp); 584 585 /* SW defined function Normal operation */ 586 analogix_dp_enable_sw_function(dp); 587 588 analogix_dp_config_interrupt(dp); 589 analogix_dp_init_analog_func(dp); 590 591 analogix_dp_init_hpd(dp); 592 analogix_dp_init_aux(dp); 593 } 594 595 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 596 { 597 int i; 598 unsigned char sum = 0; 599 600 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 601 sum = sum + edid_data[i]; 602 603 return sum; 604 } 605 606 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 607 { 608 unsigned char *edid = dp->edid; 609 unsigned int extend_block = 0; 610 unsigned char test_vector; 611 int retval; 612 613 /* 614 * EDID device address is 0x50. 615 * However, if necessary, you must have set upper address 616 * into E-EDID in I2C device, 0x30. 617 */ 618 619 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 620 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 621 EDID_EXTENSION_FLAG, 622 &extend_block); 623 if (retval) 624 return retval; 625 626 if (extend_block > 0) { 627 debug("EDID data includes a single extension!\n"); 628 629 /* Read EDID data */ 630 retval = analogix_dp_read_bytes_from_i2c(dp, 631 I2C_EDID_DEVICE_ADDR, 632 EDID_HEADER_PATTERN, 633 EDID_BLOCK_LENGTH, 634 &edid[EDID_HEADER_PATTERN]); 635 if (retval < 0) 636 return retval; 637 638 if (analogix_dp_calc_edid_check_sum(edid)) 639 return -EINVAL; 640 641 /* Read additional EDID data */ 642 retval = analogix_dp_read_bytes_from_i2c(dp, 643 I2C_EDID_DEVICE_ADDR, 644 EDID_BLOCK_LENGTH, 645 EDID_BLOCK_LENGTH, 646 &edid[EDID_BLOCK_LENGTH]); 647 if (retval < 0) 648 return retval; 649 650 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 651 return -EINVAL; 652 653 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 654 &test_vector); 655 if (test_vector & DP_TEST_LINK_EDID_READ) { 656 analogix_dp_write_byte_to_dpcd(dp, 657 DP_TEST_EDID_CHECKSUM, 658 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 659 analogix_dp_write_byte_to_dpcd(dp, 660 DP_TEST_RESPONSE, 661 DP_TEST_EDID_CHECKSUM_WRITE); 662 } 663 } else { 664 dev_info(dp->dev, 665 "EDID data does not include any extensions.\n"); 666 667 /* Read EDID data */ 668 retval = analogix_dp_read_bytes_from_i2c(dp, 669 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 670 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 671 if (retval < 0) 672 return retval; 673 674 if (analogix_dp_calc_edid_check_sum(edid)) 675 return -EINVAL; 676 677 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 678 &test_vector); 679 if (test_vector & DP_TEST_LINK_EDID_READ) { 680 analogix_dp_write_byte_to_dpcd(dp, 681 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 682 analogix_dp_write_byte_to_dpcd(dp, 683 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 684 } 685 } 686 687 return 0; 688 } 689 690 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 691 { 692 u8 buf[12]; 693 int i, try = 5; 694 int retval; 695 696 retry: 697 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 698 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 699 700 if (retval && try--) { 701 mdelay(10); 702 goto retry; 703 } 704 705 if (retval) 706 return retval; 707 708 /* Read EDID */ 709 for (i = 0; i < 3; i++) { 710 retval = analogix_dp_read_edid(dp); 711 if (!retval) 712 break; 713 } 714 715 return retval; 716 } 717 718 static int analogix_dp_connector_init(struct display_state *state) 719 { 720 struct connector_state *conn_state = &state->conn_state; 721 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 722 723 conn_state->type = DRM_MODE_CONNECTOR_eDP; 724 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 725 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 726 727 /* eDP software reset request */ 728 reset_assert(&dp->reset); 729 udelay(1); 730 reset_deassert(&dp->reset); 731 732 analogix_dp_init_dp(dp); 733 734 return 0; 735 } 736 737 static int analogix_dp_connector_get_edid(struct display_state *state) 738 { 739 struct connector_state *conn_state = &state->conn_state; 740 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 741 int ret; 742 743 ret = analogix_dp_handle_edid(dp); 744 if (ret) { 745 dev_err(dp->dev, "failed to get edid\n"); 746 return ret; 747 } 748 749 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 750 751 return 0; 752 } 753 754 static int analogix_dp_connector_enable(struct display_state *state) 755 { 756 struct connector_state *conn_state = &state->conn_state; 757 struct crtc_state *crtc_state = &state->crtc_state; 758 const struct rockchip_connector *connector = conn_state->connector; 759 const struct rockchip_dp_chip_data *pdata = connector->data; 760 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 761 struct video_info *video = &dp->video_info; 762 u32 val; 763 int ret; 764 765 if (pdata->has_vop_sel) { 766 if (crtc_state->crtc_id) 767 val = pdata->lcdsel_lit; 768 else 769 val = pdata->lcdsel_big; 770 771 writel(val, dp->grf + pdata->lcdsel_grf_reg); 772 } 773 774 switch (conn_state->bpc) { 775 case 12: 776 video->color_depth = COLOR_12; 777 break; 778 case 10: 779 video->color_depth = COLOR_10; 780 break; 781 case 6: 782 video->color_depth = COLOR_6; 783 break; 784 case 8: 785 default: 786 video->color_depth = COLOR_8; 787 break; 788 } 789 790 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 791 dp->video_info.max_link_rate); 792 if (ret) { 793 dev_err(dp->dev, "unable to do link train\n"); 794 return ret; 795 } 796 797 analogix_dp_enable_scramble(dp, 1); 798 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 799 analogix_dp_enable_enhanced_mode(dp, 1); 800 801 analogix_dp_init_video(dp); 802 ret = analogix_dp_config_video(dp); 803 if (ret) { 804 dev_err(dp->dev, "unable to config video\n"); 805 return ret; 806 } 807 808 return 0; 809 } 810 811 static int analogix_dp_connector_disable(struct display_state *state) 812 { 813 /* TODO */ 814 815 return 0; 816 } 817 818 static int analogix_dp_connector_detect(struct display_state *state) 819 { 820 struct connector_state *conn_state = &state->conn_state; 821 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 822 823 return analogix_dp_detect(dp); 824 } 825 826 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 827 .init = analogix_dp_connector_init, 828 .get_edid = analogix_dp_connector_get_edid, 829 .enable = analogix_dp_connector_enable, 830 .disable = analogix_dp_connector_disable, 831 .detect = analogix_dp_connector_detect, 832 }; 833 834 static int analogix_dp_probe(struct udevice *dev) 835 { 836 struct analogix_dp_device *dp = dev_get_priv(dev); 837 const struct rockchip_connector *connector = 838 (const struct rockchip_connector *)dev_get_driver_data(dev); 839 const struct rockchip_dp_chip_data *pdata = connector->data; 840 int ret; 841 842 dp->reg_base = dev_read_addr_ptr(dev); 843 dp->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 844 if (IS_ERR(dp->grf)) 845 return PTR_ERR(dp->grf); 846 847 ret = reset_get_by_name(dev, "dp", &dp->reset); 848 if (ret) { 849 dev_err(dev, "failed to get reset control: %d\n", ret); 850 return ret; 851 } 852 853 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 854 GPIOD_IS_IN); 855 if (ret && ret != -ENOENT) { 856 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 857 return ret; 858 } 859 860 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 861 862 dp->plat_data.dev_type = ROCKCHIP_DP; 863 dp->plat_data.subdev_type = pdata->chip_type; 864 /* 865 * Like Rockchip DisplayPort TRM indicate that "Main link 866 * containing 4 physical lanes of 2.7/1.62 Gbps/lane". 867 */ 868 dp->video_info.max_link_rate = 0x0A; 869 dp->video_info.max_lane_count = 0x04; 870 871 dp->dev = dev; 872 873 return 0; 874 } 875 876 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 877 .lcdsel_grf_reg = 0x025c, 878 .lcdsel_big = 0 | BIT(21), 879 .lcdsel_lit = BIT(5) | BIT(21), 880 .chip_type = RK3288_DP, 881 .has_vop_sel = true, 882 }; 883 884 static const struct rockchip_connector rk3288_edp_driver_data = { 885 .funcs = &analogix_dp_connector_funcs, 886 .data = &rk3288_edp_platform_data, 887 }; 888 889 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 890 .chip_type = RK3368_EDP, 891 .has_vop_sel = false, 892 }; 893 894 static const struct rockchip_connector rk3368_edp_driver_data = { 895 .funcs = &analogix_dp_connector_funcs, 896 .data = &rk3368_edp_platform_data, 897 }; 898 899 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 900 .lcdsel_grf_reg = 0x6250, 901 .lcdsel_big = 0 | BIT(21), 902 .lcdsel_lit = BIT(5) | BIT(21), 903 .chip_type = RK3399_EDP, 904 .has_vop_sel = true, 905 }; 906 907 static const struct rockchip_connector rk3399_edp_driver_data = { 908 .funcs = &analogix_dp_connector_funcs, 909 .data = &rk3399_edp_platform_data, 910 }; 911 912 static const struct udevice_id analogix_dp_ids[] = { 913 { 914 .compatible = "rockchip,rk3288-dp", 915 .data = (ulong)&rk3288_edp_driver_data, 916 }, { 917 .compatible = "rockchip,rk3368-edp", 918 .data = (ulong)&rk3368_edp_driver_data, 919 }, { 920 .compatible = "rockchip,rk3399-edp", 921 .data = (ulong)&rk3399_edp_driver_data, 922 }, 923 {} 924 }; 925 926 U_BOOT_DRIVER(analogix_dp) = { 927 .name = "analogix_dp", 928 .id = UCLASS_DISPLAY, 929 .of_match = analogix_dp_ids, 930 .probe = analogix_dp_probe, 931 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 932 }; 933