1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/read.h> 15 #include <linux/list.h> 16 #include <syscon.h> 17 #include <asm/arch-rockchip/clock.h> 18 #include <asm/gpio.h> 19 20 #include "rockchip_display.h" 21 #include "rockchip_crtc.h" 22 #include "rockchip_connector.h" 23 #include "analogix_dp.h" 24 25 /** 26 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 27 * @lcdsel_grf_reg: grf register offset of lcdc select 28 * @lcdsel_big: reg value of selecting vop big for eDP 29 * @lcdsel_lit: reg value of selecting vop little for eDP 30 * @chip_type: specific chip type 31 * @ssc: check if SSC is supported by source 32 */ 33 struct rockchip_dp_chip_data { 34 u32 lcdsel_grf_reg; 35 u32 lcdsel_big; 36 u32 lcdsel_lit; 37 u32 chip_type; 38 bool ssc; 39 }; 40 41 static void 42 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 43 bool enable) 44 { 45 u8 data; 46 47 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 48 49 if (enable) 50 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 51 DP_LANE_COUNT_ENHANCED_FRAME_EN | 52 DPCD_LANE_COUNT_SET(data)); 53 else 54 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 55 DPCD_LANE_COUNT_SET(data)); 56 } 57 58 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 59 { 60 u8 data; 61 int retval; 62 63 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 64 retval = DPCD_ENHANCED_FRAME_CAP(data); 65 66 return retval; 67 } 68 69 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 70 { 71 u8 data; 72 73 data = analogix_dp_is_enhanced_mode_available(dp); 74 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 75 analogix_dp_enable_enhanced_mode(dp, data); 76 } 77 78 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 79 { 80 analogix_dp_set_training_pattern(dp, DP_NONE); 81 82 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 83 DP_TRAINING_PATTERN_DISABLE); 84 } 85 86 static int analogix_dp_link_start(struct analogix_dp_device *dp) 87 { 88 u8 buf[4]; 89 int lane, lane_count, retval; 90 91 lane_count = dp->link_train.lane_count; 92 93 dp->link_train.lt_state = CLOCK_RECOVERY; 94 dp->link_train.eq_loop = 0; 95 96 for (lane = 0; lane < lane_count; lane++) 97 dp->link_train.cr_loop[lane] = 0; 98 99 /* Set link rate and count as you want to establish*/ 100 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 101 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 102 103 /* Setup RX configuration */ 104 buf[0] = dp->link_train.link_rate; 105 buf[1] = dp->link_train.lane_count; 106 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 107 if (retval) 108 return retval; 109 110 /* Spread AMP if required, enable 8b/10b coding */ 111 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 112 buf[1] = DP_SET_ANSI_8B10B; 113 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_DOWNSPREAD_CTRL, 114 2, buf); 115 if (retval < 0) 116 return retval; 117 118 /* Set TX voltage-swing and pre-emphasis to minimum */ 119 for (lane = 0; lane < lane_count; lane++) 120 dp->link_train.training_lane[lane] = 121 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 122 DP_TRAIN_PRE_EMPH_LEVEL_0; 123 analogix_dp_set_lane_link_training(dp); 124 125 /* Set training pattern 1 */ 126 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 127 128 /* Set RX training pattern */ 129 retval = analogix_dp_write_byte_to_dpcd(dp, 130 DP_TRAINING_PATTERN_SET, 131 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 132 if (retval) 133 return retval; 134 135 for (lane = 0; lane < lane_count; lane++) 136 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 137 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 138 139 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 140 lane_count, buf); 141 142 return retval; 143 } 144 145 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 146 { 147 int shift = (lane & 1) * 4; 148 u8 link_value = link_status[lane >> 1]; 149 150 return (link_value >> shift) & 0xf; 151 } 152 153 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 154 { 155 int lane; 156 u8 lane_status; 157 158 for (lane = 0; lane < lane_count; lane++) { 159 lane_status = analogix_dp_get_lane_status(link_status, lane); 160 if ((lane_status & DP_LANE_CR_DONE) == 0) 161 return -EINVAL; 162 } 163 return 0; 164 } 165 166 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 167 int lane_count) 168 { 169 int lane; 170 u8 lane_status; 171 172 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 173 return -EINVAL; 174 175 for (lane = 0; lane < lane_count; lane++) { 176 lane_status = analogix_dp_get_lane_status(link_status, lane); 177 lane_status &= DP_CHANNEL_EQ_BITS; 178 if (lane_status != DP_CHANNEL_EQ_BITS) 179 return -EINVAL; 180 } 181 182 return 0; 183 } 184 185 static unsigned char 186 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 187 { 188 int shift = (lane & 1) * 4; 189 u8 link_value = adjust_request[lane >> 1]; 190 191 return (link_value >> shift) & 0x3; 192 } 193 194 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 195 u8 adjust_request[2], 196 int lane) 197 { 198 int shift = (lane & 1) * 4; 199 u8 link_value = adjust_request[lane >> 1]; 200 201 return ((link_value >> shift) & 0xc) >> 2; 202 } 203 204 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 205 { 206 analogix_dp_training_pattern_dis(dp); 207 analogix_dp_set_enhanced_mode(dp); 208 209 dp->link_train.lt_state = FAILED; 210 } 211 212 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 213 u8 adjust_request[2]) 214 { 215 int lane, lane_count; 216 u8 voltage_swing, pre_emphasis, training_lane; 217 218 lane_count = dp->link_train.lane_count; 219 for (lane = 0; lane < lane_count; lane++) { 220 voltage_swing = analogix_dp_get_adjust_request_voltage( 221 adjust_request, lane); 222 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 223 adjust_request, lane); 224 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 225 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 226 227 if (voltage_swing == VOLTAGE_LEVEL_3) 228 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 229 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 230 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 231 232 dp->link_train.training_lane[lane] = training_lane; 233 } 234 } 235 236 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 237 { 238 int lane, lane_count, retval; 239 u8 voltage_swing, pre_emphasis, training_lane; 240 u8 link_status[2], adjust_request[2]; 241 242 udelay(101); 243 244 lane_count = dp->link_train.lane_count; 245 246 retval = analogix_dp_read_bytes_from_dpcd(dp, 247 DP_LANE0_1_STATUS, 2, link_status); 248 if (retval) 249 return retval; 250 251 retval = analogix_dp_read_bytes_from_dpcd(dp, 252 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 253 if (retval) 254 return retval; 255 256 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 257 /* set training pattern 2 for EQ */ 258 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 259 260 retval = analogix_dp_write_byte_to_dpcd(dp, 261 DP_TRAINING_PATTERN_SET, 262 DP_LINK_SCRAMBLING_DISABLE | 263 DP_TRAINING_PATTERN_2); 264 if (retval) 265 return retval; 266 267 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 268 dp->link_train.lt_state = EQUALIZER_TRAINING; 269 } else { 270 for (lane = 0; lane < lane_count; lane++) { 271 training_lane = analogix_dp_get_lane_link_training( 272 dp, lane); 273 voltage_swing = analogix_dp_get_adjust_request_voltage( 274 adjust_request, lane); 275 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 276 adjust_request, lane); 277 278 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 279 voltage_swing && 280 DPCD_PRE_EMPHASIS_GET(training_lane) == 281 pre_emphasis) 282 dp->link_train.cr_loop[lane]++; 283 284 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 285 voltage_swing == VOLTAGE_LEVEL_3 || 286 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 287 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 288 dp->link_train.cr_loop[lane], 289 voltage_swing, pre_emphasis); 290 analogix_dp_reduce_link_rate(dp); 291 return -EIO; 292 } 293 } 294 } 295 296 analogix_dp_get_adjust_training_lane(dp, adjust_request); 297 analogix_dp_set_lane_link_training(dp); 298 299 retval = analogix_dp_write_bytes_to_dpcd(dp, 300 DP_TRAINING_LANE0_SET, lane_count, 301 dp->link_train.training_lane); 302 if (retval) 303 return retval; 304 305 return retval; 306 } 307 308 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 309 { 310 int lane_count, retval; 311 u32 reg; 312 u8 link_align, link_status[2], adjust_request[2]; 313 314 udelay(401); 315 316 lane_count = dp->link_train.lane_count; 317 318 retval = analogix_dp_read_bytes_from_dpcd(dp, 319 DP_LANE0_1_STATUS, 2, link_status); 320 if (retval) 321 return retval; 322 323 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 324 analogix_dp_reduce_link_rate(dp); 325 return -EIO; 326 } 327 328 retval = analogix_dp_read_bytes_from_dpcd(dp, 329 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 330 if (retval) 331 return retval; 332 333 retval = analogix_dp_read_byte_from_dpcd(dp, 334 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 335 if (retval) 336 return retval; 337 338 analogix_dp_get_adjust_training_lane(dp, adjust_request); 339 340 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 341 /* traing pattern Set to Normal */ 342 analogix_dp_training_pattern_dis(dp); 343 344 printf("Link Training success!\n"); 345 346 analogix_dp_get_link_bandwidth(dp, ®); 347 dp->link_train.link_rate = reg; 348 analogix_dp_get_lane_count(dp, ®); 349 dp->link_train.lane_count = reg; 350 351 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 352 dp->link_train.link_rate, dp->link_train.lane_count); 353 354 /* set enhanced mode if available */ 355 analogix_dp_set_enhanced_mode(dp); 356 dp->link_train.lt_state = FINISHED; 357 358 return 0; 359 } 360 361 /* not all locked */ 362 dp->link_train.eq_loop++; 363 364 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 365 dev_dbg(dp->dev, "EQ Max loop\n"); 366 analogix_dp_reduce_link_rate(dp); 367 return -EIO; 368 } 369 370 analogix_dp_set_lane_link_training(dp); 371 372 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 373 lane_count, dp->link_train.training_lane); 374 375 return retval; 376 } 377 378 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 379 u8 *bandwidth) 380 { 381 u8 data; 382 383 /* 384 * For DP rev.1.1, Maximum link rate of Main Link lanes 385 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 386 * For DP rev.1.2, Maximum link rate of Main Link lanes 387 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 388 */ 389 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 390 *bandwidth = data; 391 } 392 393 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 394 u8 *lane_count) 395 { 396 u8 data; 397 398 /* 399 * For DP rev.1.1, Maximum number of Main Link lanes 400 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 401 */ 402 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 403 *lane_count = DPCD_MAX_LANE_COUNT(data); 404 } 405 406 static int analogix_dp_init_training(struct analogix_dp_device *dp, 407 enum link_lane_count_type max_lane, 408 int max_rate) 409 { 410 u8 dpcd; 411 412 /* 413 * MACRO_RST must be applied after the PLL_LOCK to avoid 414 * the DP inter pair skew issue for at least 10 us 415 */ 416 analogix_dp_reset_macro(dp); 417 418 /* Initialize by reading RX's DPCD */ 419 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 420 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 421 422 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 423 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 424 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 425 dev_err(dp->dev, "failed to get Rx Max Link Rate\n"); 426 return -ENODEV; 427 } 428 429 if (dp->link_train.lane_count == 0) { 430 dev_err(dp->dev, "failed to get Rx Max Lane Count\n"); 431 return -ENODEV; 432 } 433 434 /* Setup TX lane count & rate */ 435 if (dp->link_train.lane_count > max_lane) 436 dp->link_train.lane_count = max_lane; 437 if (dp->link_train.link_rate > max_rate) 438 dp->link_train.link_rate = max_rate; 439 440 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_DOWNSPREAD, &dpcd); 441 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 442 443 /* All DP analog module power up */ 444 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 445 446 return 0; 447 } 448 449 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 450 { 451 int retval = 0, training_finished = 0; 452 453 dp->link_train.lt_state = START; 454 455 /* Process here */ 456 while (!retval && !training_finished) { 457 switch (dp->link_train.lt_state) { 458 case START: 459 retval = analogix_dp_link_start(dp); 460 if (retval) 461 dev_err(dp->dev, "LT link start failed!\n"); 462 break; 463 case CLOCK_RECOVERY: 464 retval = analogix_dp_process_clock_recovery(dp); 465 if (retval) 466 dev_err(dp->dev, "LT CR failed!\n"); 467 break; 468 case EQUALIZER_TRAINING: 469 retval = analogix_dp_process_equalizer_training(dp); 470 if (retval) 471 dev_err(dp->dev, "LT EQ failed!\n"); 472 break; 473 case FINISHED: 474 training_finished = 1; 475 break; 476 case FAILED: 477 return -EREMOTEIO; 478 } 479 } 480 481 return retval; 482 } 483 484 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 485 u32 count, u32 bwtype) 486 { 487 int ret; 488 489 ret = analogix_dp_init_training(dp, count, bwtype); 490 if (ret < 0) { 491 dev_err(dp->dev, "failed to init training\n"); 492 return ret; 493 } 494 495 ret = analogix_dp_sw_link_training(dp); 496 if (ret < 0) { 497 dev_err(dp->dev, "failed to do sw link training\n"); 498 return ret; 499 } 500 501 return 0; 502 } 503 504 static int analogix_dp_config_video(struct analogix_dp_device *dp) 505 { 506 int timeout_loop = 0; 507 int done_count = 0; 508 509 analogix_dp_config_video_slave_mode(dp); 510 511 analogix_dp_set_video_color_format(dp); 512 513 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 514 dev_err(dp->dev, "PLL is not locked yet.\n"); 515 return -EINVAL; 516 } 517 518 for (;;) { 519 timeout_loop++; 520 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 521 break; 522 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 523 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 524 return -ETIMEDOUT; 525 } 526 527 udelay(2); 528 } 529 530 /* Set to use the register calculated M/N video */ 531 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 532 533 /* For video bist, Video timing must be generated by register */ 534 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 535 536 /* Disable video mute */ 537 analogix_dp_enable_video_mute(dp, 0); 538 539 /* Configure video slave mode */ 540 analogix_dp_enable_video_master(dp, 0); 541 542 /* Enable video input */ 543 analogix_dp_start_video(dp); 544 545 timeout_loop = 0; 546 547 for (;;) { 548 timeout_loop++; 549 if (analogix_dp_is_video_stream_on(dp) == 0) { 550 done_count++; 551 if (done_count > 10) 552 break; 553 } else if (done_count) { 554 done_count = 0; 555 } 556 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 557 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 558 return -ETIMEDOUT; 559 } 560 561 udelay(1001); 562 } 563 564 return 0; 565 } 566 567 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 568 bool enable) 569 { 570 u8 data; 571 572 if (enable) { 573 analogix_dp_enable_scrambling(dp); 574 575 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 576 &data); 577 analogix_dp_write_byte_to_dpcd(dp, 578 DP_TRAINING_PATTERN_SET, 579 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 580 } else { 581 analogix_dp_disable_scrambling(dp); 582 583 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 584 &data); 585 analogix_dp_write_byte_to_dpcd(dp, 586 DP_TRAINING_PATTERN_SET, 587 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 588 } 589 } 590 591 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 592 { 593 analogix_dp_reset(dp); 594 595 analogix_dp_swreset(dp); 596 597 analogix_dp_init_analog_param(dp); 598 analogix_dp_init_interrupt(dp); 599 600 /* SW defined function Normal operation */ 601 analogix_dp_enable_sw_function(dp); 602 603 analogix_dp_config_interrupt(dp); 604 analogix_dp_init_analog_func(dp); 605 606 analogix_dp_init_hpd(dp); 607 analogix_dp_init_aux(dp); 608 } 609 610 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 611 { 612 int i; 613 unsigned char sum = 0; 614 615 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 616 sum = sum + edid_data[i]; 617 618 return sum; 619 } 620 621 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 622 { 623 unsigned char *edid = dp->edid; 624 unsigned int extend_block = 0; 625 unsigned char test_vector; 626 int retval; 627 628 /* 629 * EDID device address is 0x50. 630 * However, if necessary, you must have set upper address 631 * into E-EDID in I2C device, 0x30. 632 */ 633 634 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 635 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 636 EDID_EXTENSION_FLAG, 637 &extend_block); 638 if (retval) 639 return retval; 640 641 if (extend_block > 0) { 642 debug("EDID data includes a single extension!\n"); 643 644 /* Read EDID data */ 645 retval = analogix_dp_read_bytes_from_i2c(dp, 646 I2C_EDID_DEVICE_ADDR, 647 EDID_HEADER_PATTERN, 648 EDID_BLOCK_LENGTH, 649 &edid[EDID_HEADER_PATTERN]); 650 if (retval < 0) 651 return retval; 652 653 if (analogix_dp_calc_edid_check_sum(edid)) 654 return -EINVAL; 655 656 /* Read additional EDID data */ 657 retval = analogix_dp_read_bytes_from_i2c(dp, 658 I2C_EDID_DEVICE_ADDR, 659 EDID_BLOCK_LENGTH, 660 EDID_BLOCK_LENGTH, 661 &edid[EDID_BLOCK_LENGTH]); 662 if (retval < 0) 663 return retval; 664 665 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 666 return -EINVAL; 667 668 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 669 &test_vector); 670 if (test_vector & DP_TEST_LINK_EDID_READ) { 671 analogix_dp_write_byte_to_dpcd(dp, 672 DP_TEST_EDID_CHECKSUM, 673 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 674 analogix_dp_write_byte_to_dpcd(dp, 675 DP_TEST_RESPONSE, 676 DP_TEST_EDID_CHECKSUM_WRITE); 677 } 678 } else { 679 dev_info(dp->dev, 680 "EDID data does not include any extensions.\n"); 681 682 /* Read EDID data */ 683 retval = analogix_dp_read_bytes_from_i2c(dp, 684 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 685 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 686 if (retval < 0) 687 return retval; 688 689 if (analogix_dp_calc_edid_check_sum(edid)) 690 return -EINVAL; 691 692 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 693 &test_vector); 694 if (test_vector & DP_TEST_LINK_EDID_READ) { 695 analogix_dp_write_byte_to_dpcd(dp, 696 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 697 analogix_dp_write_byte_to_dpcd(dp, 698 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 699 } 700 } 701 702 return 0; 703 } 704 705 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 706 { 707 u8 buf[12]; 708 int i, try = 5; 709 int retval; 710 711 retry: 712 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 713 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 714 715 if (retval && try--) { 716 mdelay(10); 717 goto retry; 718 } 719 720 if (retval) 721 return retval; 722 723 /* Read EDID */ 724 for (i = 0; i < 3; i++) { 725 retval = analogix_dp_read_edid(dp); 726 if (!retval) 727 break; 728 } 729 730 return retval; 731 } 732 733 static int analogix_dp_connector_init(struct display_state *state) 734 { 735 struct connector_state *conn_state = &state->conn_state; 736 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 737 738 conn_state->type = DRM_MODE_CONNECTOR_eDP; 739 conn_state->output_if |= VOP_OUTPUT_IF_eDP0; 740 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 741 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 742 743 reset_assert_bulk(&dp->resets); 744 udelay(1); 745 reset_deassert_bulk(&dp->resets); 746 747 generic_phy_power_on(&dp->phy); 748 analogix_dp_init_dp(dp); 749 750 return 0; 751 } 752 753 static int analogix_dp_connector_get_edid(struct display_state *state) 754 { 755 struct connector_state *conn_state = &state->conn_state; 756 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 757 int ret; 758 759 ret = analogix_dp_handle_edid(dp); 760 if (ret) { 761 dev_err(dp->dev, "failed to get edid\n"); 762 return ret; 763 } 764 765 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 766 767 return 0; 768 } 769 770 static int analogix_dp_connector_enable(struct display_state *state) 771 { 772 struct connector_state *conn_state = &state->conn_state; 773 struct crtc_state *crtc_state = &state->crtc_state; 774 const struct rockchip_connector *connector = conn_state->connector; 775 const struct rockchip_dp_chip_data *pdata = connector->data; 776 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 777 struct video_info *video = &dp->video_info; 778 u32 val; 779 int ret; 780 781 if (pdata->lcdsel_grf_reg) { 782 if (crtc_state->crtc_id) 783 val = pdata->lcdsel_lit; 784 else 785 val = pdata->lcdsel_big; 786 787 writel(val, syscon_get_first_range(ROCKCHIP_SYSCON_GRF) + pdata->lcdsel_grf_reg); 788 } 789 790 switch (conn_state->bpc) { 791 case 12: 792 video->color_depth = COLOR_12; 793 break; 794 case 10: 795 video->color_depth = COLOR_10; 796 break; 797 case 6: 798 video->color_depth = COLOR_6; 799 break; 800 case 8: 801 default: 802 video->color_depth = COLOR_8; 803 break; 804 } 805 806 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 807 dp->video_info.max_link_rate); 808 if (ret) { 809 dev_err(dp->dev, "unable to do link train\n"); 810 return ret; 811 } 812 813 analogix_dp_enable_scramble(dp, 1); 814 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 815 analogix_dp_enable_enhanced_mode(dp, 1); 816 817 analogix_dp_init_video(dp); 818 ret = analogix_dp_config_video(dp); 819 if (ret) { 820 dev_err(dp->dev, "unable to config video\n"); 821 return ret; 822 } 823 824 return 0; 825 } 826 827 static int analogix_dp_connector_disable(struct display_state *state) 828 { 829 /* TODO */ 830 831 return 0; 832 } 833 834 static int analogix_dp_connector_detect(struct display_state *state) 835 { 836 struct connector_state *conn_state = &state->conn_state; 837 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 838 839 return analogix_dp_detect(dp); 840 } 841 842 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 843 .init = analogix_dp_connector_init, 844 .get_edid = analogix_dp_connector_get_edid, 845 .enable = analogix_dp_connector_enable, 846 .disable = analogix_dp_connector_disable, 847 .detect = analogix_dp_connector_detect, 848 }; 849 850 static int analogix_dp_probe(struct udevice *dev) 851 { 852 struct analogix_dp_device *dp = dev_get_priv(dev); 853 const struct rockchip_connector *connector = 854 (const struct rockchip_connector *)dev_get_driver_data(dev); 855 const struct rockchip_dp_chip_data *pdata = connector->data; 856 int ret; 857 858 dp->reg_base = dev_read_addr_ptr(dev); 859 860 ret = reset_get_bulk(dev, &dp->resets); 861 if (ret) { 862 dev_err(dev, "failed to get reset control: %d\n", ret); 863 return ret; 864 } 865 866 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 867 GPIOD_IS_IN); 868 if (ret && ret != -ENOENT) { 869 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 870 return ret; 871 } 872 873 generic_phy_get_by_name(dev, "dp", &dp->phy); 874 875 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 876 877 dp->plat_data.dev_type = ROCKCHIP_DP; 878 dp->plat_data.subdev_type = pdata->chip_type; 879 dp->plat_data.ssc = pdata->ssc; 880 /* 881 * Like Rockchip DisplayPort TRM indicate that "Main link 882 * containing 4 physical lanes of 2.7/1.62 Gbps/lane". 883 */ 884 dp->video_info.max_link_rate = 0x0A; 885 dp->video_info.max_lane_count = 0x04; 886 887 dp->dev = dev; 888 889 return 0; 890 } 891 892 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 893 .lcdsel_grf_reg = 0x025c, 894 .lcdsel_big = 0 | BIT(21), 895 .lcdsel_lit = BIT(5) | BIT(21), 896 .chip_type = RK3288_DP, 897 }; 898 899 static const struct rockchip_connector rk3288_edp_driver_data = { 900 .funcs = &analogix_dp_connector_funcs, 901 .data = &rk3288_edp_platform_data, 902 }; 903 904 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 905 .chip_type = RK3368_EDP, 906 }; 907 908 static const struct rockchip_connector rk3368_edp_driver_data = { 909 .funcs = &analogix_dp_connector_funcs, 910 .data = &rk3368_edp_platform_data, 911 }; 912 913 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 914 .lcdsel_grf_reg = 0x6250, 915 .lcdsel_big = 0 | BIT(21), 916 .lcdsel_lit = BIT(5) | BIT(21), 917 .chip_type = RK3399_EDP, 918 }; 919 920 static const struct rockchip_connector rk3399_edp_driver_data = { 921 .funcs = &analogix_dp_connector_funcs, 922 .data = &rk3399_edp_platform_data, 923 }; 924 925 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 926 .chip_type = RK3568_EDP, 927 .ssc = true, 928 }; 929 930 static const struct rockchip_connector rk3568_edp_driver_data = { 931 .funcs = &analogix_dp_connector_funcs, 932 .data = &rk3568_edp_platform_data, 933 }; 934 935 static const struct udevice_id analogix_dp_ids[] = { 936 { 937 .compatible = "rockchip,rk3288-dp", 938 .data = (ulong)&rk3288_edp_driver_data, 939 }, { 940 .compatible = "rockchip,rk3368-edp", 941 .data = (ulong)&rk3368_edp_driver_data, 942 }, { 943 .compatible = "rockchip,rk3399-edp", 944 .data = (ulong)&rk3399_edp_driver_data, 945 }, { 946 .compatible = "rockchip,rk3568-edp", 947 .data = (ulong)&rk3568_edp_driver_data, 948 }, 949 {} 950 }; 951 952 U_BOOT_DRIVER(analogix_dp) = { 953 .name = "analogix_dp", 954 .id = UCLASS_DISPLAY, 955 .of_match = analogix_dp_ids, 956 .probe = analogix_dp_probe, 957 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 958 }; 959