1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/list.h> 17 #include <syscon.h> 18 #include <asm/arch-rockchip/clock.h> 19 #include <asm/gpio.h> 20 21 #include "rockchip_display.h" 22 #include "rockchip_crtc.h" 23 #include "rockchip_connector.h" 24 #include "analogix_dp.h" 25 26 /** 27 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 28 * @lcdsel_grf_reg: grf register offset of lcdc select 29 * @lcdsel_big: reg value of selecting vop big for eDP 30 * @lcdsel_lit: reg value of selecting vop little for eDP 31 * @chip_type: specific chip type 32 * @ssc: check if SSC is supported by source 33 */ 34 struct rockchip_dp_chip_data { 35 u32 lcdsel_grf_reg; 36 u32 lcdsel_big; 37 u32 lcdsel_lit; 38 u32 chip_type; 39 bool ssc; 40 }; 41 42 static void 43 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 44 bool enable) 45 { 46 u8 data; 47 48 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 49 50 if (enable) 51 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 52 DP_LANE_COUNT_ENHANCED_FRAME_EN | 53 DPCD_LANE_COUNT_SET(data)); 54 else 55 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 56 DPCD_LANE_COUNT_SET(data)); 57 } 58 59 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 60 { 61 u8 data; 62 int retval; 63 64 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 65 retval = DPCD_ENHANCED_FRAME_CAP(data); 66 67 return retval; 68 } 69 70 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 71 { 72 u8 data; 73 74 data = analogix_dp_is_enhanced_mode_available(dp); 75 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 76 analogix_dp_enable_enhanced_mode(dp, data); 77 } 78 79 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 80 { 81 analogix_dp_set_training_pattern(dp, DP_NONE); 82 83 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 84 DP_TRAINING_PATTERN_DISABLE); 85 } 86 87 static int analogix_dp_link_start(struct analogix_dp_device *dp) 88 { 89 u8 buf[4]; 90 int lane, lane_count, retval; 91 92 lane_count = dp->link_train.lane_count; 93 94 dp->link_train.lt_state = CLOCK_RECOVERY; 95 dp->link_train.eq_loop = 0; 96 97 for (lane = 0; lane < lane_count; lane++) 98 dp->link_train.cr_loop[lane] = 0; 99 100 /* Set link rate and count as you want to establish*/ 101 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 102 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 103 104 /* Setup RX configuration */ 105 buf[0] = dp->link_train.link_rate; 106 buf[1] = dp->link_train.lane_count; 107 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 108 if (retval) 109 return retval; 110 111 /* Spread AMP if required, enable 8b/10b coding */ 112 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 113 buf[1] = DP_SET_ANSI_8B10B; 114 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_DOWNSPREAD_CTRL, 115 2, buf); 116 if (retval < 0) 117 return retval; 118 119 /* Set TX voltage-swing and pre-emphasis to minimum */ 120 for (lane = 0; lane < lane_count; lane++) 121 dp->link_train.training_lane[lane] = 122 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 123 DP_TRAIN_PRE_EMPH_LEVEL_0; 124 analogix_dp_set_lane_link_training(dp); 125 126 /* Set training pattern 1 */ 127 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 128 129 /* Set RX training pattern */ 130 retval = analogix_dp_write_byte_to_dpcd(dp, 131 DP_TRAINING_PATTERN_SET, 132 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 133 if (retval) 134 return retval; 135 136 for (lane = 0; lane < lane_count; lane++) 137 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 138 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 139 140 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 141 lane_count, buf); 142 143 return retval; 144 } 145 146 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 147 { 148 int shift = (lane & 1) * 4; 149 u8 link_value = link_status[lane >> 1]; 150 151 return (link_value >> shift) & 0xf; 152 } 153 154 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 155 { 156 int lane; 157 u8 lane_status; 158 159 for (lane = 0; lane < lane_count; lane++) { 160 lane_status = analogix_dp_get_lane_status(link_status, lane); 161 if ((lane_status & DP_LANE_CR_DONE) == 0) 162 return -EINVAL; 163 } 164 return 0; 165 } 166 167 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 168 int lane_count) 169 { 170 int lane; 171 u8 lane_status; 172 173 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 174 return -EINVAL; 175 176 for (lane = 0; lane < lane_count; lane++) { 177 lane_status = analogix_dp_get_lane_status(link_status, lane); 178 lane_status &= DP_CHANNEL_EQ_BITS; 179 if (lane_status != DP_CHANNEL_EQ_BITS) 180 return -EINVAL; 181 } 182 183 return 0; 184 } 185 186 static unsigned char 187 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 188 { 189 int shift = (lane & 1) * 4; 190 u8 link_value = adjust_request[lane >> 1]; 191 192 return (link_value >> shift) & 0x3; 193 } 194 195 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 196 u8 adjust_request[2], 197 int lane) 198 { 199 int shift = (lane & 1) * 4; 200 u8 link_value = adjust_request[lane >> 1]; 201 202 return ((link_value >> shift) & 0xc) >> 2; 203 } 204 205 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 206 { 207 analogix_dp_training_pattern_dis(dp); 208 analogix_dp_set_enhanced_mode(dp); 209 210 dp->link_train.lt_state = FAILED; 211 } 212 213 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 214 u8 adjust_request[2]) 215 { 216 int lane, lane_count; 217 u8 voltage_swing, pre_emphasis, training_lane; 218 219 lane_count = dp->link_train.lane_count; 220 for (lane = 0; lane < lane_count; lane++) { 221 voltage_swing = analogix_dp_get_adjust_request_voltage( 222 adjust_request, lane); 223 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 224 adjust_request, lane); 225 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 226 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 227 228 if (voltage_swing == VOLTAGE_LEVEL_3) 229 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 230 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 231 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 232 233 dp->link_train.training_lane[lane] = training_lane; 234 } 235 } 236 237 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 238 { 239 int lane, lane_count, retval; 240 u8 voltage_swing, pre_emphasis, training_lane; 241 u8 link_status[2], adjust_request[2]; 242 243 udelay(101); 244 245 lane_count = dp->link_train.lane_count; 246 247 retval = analogix_dp_read_bytes_from_dpcd(dp, 248 DP_LANE0_1_STATUS, 2, link_status); 249 if (retval) 250 return retval; 251 252 retval = analogix_dp_read_bytes_from_dpcd(dp, 253 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 254 if (retval) 255 return retval; 256 257 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 258 /* set training pattern 2 for EQ */ 259 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 260 261 retval = analogix_dp_write_byte_to_dpcd(dp, 262 DP_TRAINING_PATTERN_SET, 263 DP_LINK_SCRAMBLING_DISABLE | 264 DP_TRAINING_PATTERN_2); 265 if (retval) 266 return retval; 267 268 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 269 dp->link_train.lt_state = EQUALIZER_TRAINING; 270 } else { 271 for (lane = 0; lane < lane_count; lane++) { 272 training_lane = analogix_dp_get_lane_link_training( 273 dp, lane); 274 voltage_swing = analogix_dp_get_adjust_request_voltage( 275 adjust_request, lane); 276 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 277 adjust_request, lane); 278 279 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 280 voltage_swing && 281 DPCD_PRE_EMPHASIS_GET(training_lane) == 282 pre_emphasis) 283 dp->link_train.cr_loop[lane]++; 284 285 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 286 voltage_swing == VOLTAGE_LEVEL_3 || 287 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 288 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 289 dp->link_train.cr_loop[lane], 290 voltage_swing, pre_emphasis); 291 analogix_dp_reduce_link_rate(dp); 292 return -EIO; 293 } 294 } 295 } 296 297 analogix_dp_get_adjust_training_lane(dp, adjust_request); 298 analogix_dp_set_lane_link_training(dp); 299 300 retval = analogix_dp_write_bytes_to_dpcd(dp, 301 DP_TRAINING_LANE0_SET, lane_count, 302 dp->link_train.training_lane); 303 if (retval) 304 return retval; 305 306 return retval; 307 } 308 309 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 310 { 311 int lane_count, retval; 312 u32 reg; 313 u8 link_align, link_status[2], adjust_request[2]; 314 315 udelay(401); 316 317 lane_count = dp->link_train.lane_count; 318 319 retval = analogix_dp_read_bytes_from_dpcd(dp, 320 DP_LANE0_1_STATUS, 2, link_status); 321 if (retval) 322 return retval; 323 324 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 325 analogix_dp_reduce_link_rate(dp); 326 return -EIO; 327 } 328 329 retval = analogix_dp_read_bytes_from_dpcd(dp, 330 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 331 if (retval) 332 return retval; 333 334 retval = analogix_dp_read_byte_from_dpcd(dp, 335 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 336 if (retval) 337 return retval; 338 339 analogix_dp_get_adjust_training_lane(dp, adjust_request); 340 341 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 342 /* traing pattern Set to Normal */ 343 analogix_dp_training_pattern_dis(dp); 344 345 printf("Link Training success!\n"); 346 347 analogix_dp_get_link_bandwidth(dp, ®); 348 dp->link_train.link_rate = reg; 349 analogix_dp_get_lane_count(dp, ®); 350 dp->link_train.lane_count = reg; 351 352 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 353 dp->link_train.link_rate, dp->link_train.lane_count); 354 355 /* set enhanced mode if available */ 356 analogix_dp_set_enhanced_mode(dp); 357 dp->link_train.lt_state = FINISHED; 358 359 return 0; 360 } 361 362 /* not all locked */ 363 dp->link_train.eq_loop++; 364 365 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 366 dev_dbg(dp->dev, "EQ Max loop\n"); 367 analogix_dp_reduce_link_rate(dp); 368 return -EIO; 369 } 370 371 analogix_dp_set_lane_link_training(dp); 372 373 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 374 lane_count, dp->link_train.training_lane); 375 376 return retval; 377 } 378 379 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 380 u8 *bandwidth) 381 { 382 u8 data; 383 384 /* 385 * For DP rev.1.1, Maximum link rate of Main Link lanes 386 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 387 * For DP rev.1.2, Maximum link rate of Main Link lanes 388 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 389 */ 390 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 391 *bandwidth = data; 392 } 393 394 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 395 u8 *lane_count) 396 { 397 u8 data; 398 399 /* 400 * For DP rev.1.1, Maximum number of Main Link lanes 401 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 402 */ 403 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 404 *lane_count = DPCD_MAX_LANE_COUNT(data); 405 } 406 407 static int analogix_dp_init_training(struct analogix_dp_device *dp, 408 enum link_lane_count_type max_lane, 409 int max_rate) 410 { 411 u8 dpcd; 412 413 /* 414 * MACRO_RST must be applied after the PLL_LOCK to avoid 415 * the DP inter pair skew issue for at least 10 us 416 */ 417 analogix_dp_reset_macro(dp); 418 419 /* Initialize by reading RX's DPCD */ 420 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 421 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 422 423 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 424 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 425 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 426 dev_err(dp->dev, "failed to get Rx Max Link Rate\n"); 427 return -ENODEV; 428 } 429 430 if (dp->link_train.lane_count == 0) { 431 dev_err(dp->dev, "failed to get Rx Max Lane Count\n"); 432 return -ENODEV; 433 } 434 435 /* Setup TX lane count & rate */ 436 if (dp->link_train.lane_count > max_lane) 437 dp->link_train.lane_count = max_lane; 438 if (dp->link_train.link_rate > max_rate) 439 dp->link_train.link_rate = max_rate; 440 441 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_DOWNSPREAD, &dpcd); 442 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 443 444 /* All DP analog module power up */ 445 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 446 447 return 0; 448 } 449 450 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 451 { 452 int retval = 0, training_finished = 0; 453 454 dp->link_train.lt_state = START; 455 456 /* Process here */ 457 while (!retval && !training_finished) { 458 switch (dp->link_train.lt_state) { 459 case START: 460 retval = analogix_dp_link_start(dp); 461 if (retval) 462 dev_err(dp->dev, "LT link start failed!\n"); 463 break; 464 case CLOCK_RECOVERY: 465 retval = analogix_dp_process_clock_recovery(dp); 466 if (retval) 467 dev_err(dp->dev, "LT CR failed!\n"); 468 break; 469 case EQUALIZER_TRAINING: 470 retval = analogix_dp_process_equalizer_training(dp); 471 if (retval) 472 dev_err(dp->dev, "LT EQ failed!\n"); 473 break; 474 case FINISHED: 475 training_finished = 1; 476 break; 477 case FAILED: 478 return -EREMOTEIO; 479 } 480 } 481 482 return retval; 483 } 484 485 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 486 u32 count, u32 bwtype) 487 { 488 int ret; 489 490 ret = analogix_dp_init_training(dp, count, bwtype); 491 if (ret < 0) { 492 dev_err(dp->dev, "failed to init training\n"); 493 return ret; 494 } 495 496 ret = analogix_dp_sw_link_training(dp); 497 if (ret < 0) { 498 dev_err(dp->dev, "failed to do sw link training\n"); 499 return ret; 500 } 501 502 return 0; 503 } 504 505 static int analogix_dp_config_video(struct analogix_dp_device *dp) 506 { 507 int timeout_loop = 0; 508 int done_count = 0; 509 510 analogix_dp_config_video_slave_mode(dp); 511 512 analogix_dp_set_video_color_format(dp); 513 514 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 515 dev_err(dp->dev, "PLL is not locked yet.\n"); 516 return -EINVAL; 517 } 518 519 for (;;) { 520 timeout_loop++; 521 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 522 break; 523 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 524 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 525 return -ETIMEDOUT; 526 } 527 528 udelay(2); 529 } 530 531 /* Set to use the register calculated M/N video */ 532 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 533 534 /* For video bist, Video timing must be generated by register */ 535 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 536 537 /* Disable video mute */ 538 analogix_dp_enable_video_mute(dp, 0); 539 540 /* Configure video slave mode */ 541 analogix_dp_enable_video_master(dp, 0); 542 543 /* Enable video input */ 544 analogix_dp_start_video(dp); 545 546 timeout_loop = 0; 547 548 for (;;) { 549 timeout_loop++; 550 if (analogix_dp_is_video_stream_on(dp) == 0) { 551 done_count++; 552 if (done_count > 10) 553 break; 554 } else if (done_count) { 555 done_count = 0; 556 } 557 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 558 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 559 return -ETIMEDOUT; 560 } 561 562 udelay(1001); 563 } 564 565 return 0; 566 } 567 568 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 569 bool enable) 570 { 571 u8 data; 572 573 if (enable) { 574 analogix_dp_enable_scrambling(dp); 575 576 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 577 &data); 578 analogix_dp_write_byte_to_dpcd(dp, 579 DP_TRAINING_PATTERN_SET, 580 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 581 } else { 582 analogix_dp_disable_scrambling(dp); 583 584 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 585 &data); 586 analogix_dp_write_byte_to_dpcd(dp, 587 DP_TRAINING_PATTERN_SET, 588 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 589 } 590 } 591 592 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 593 { 594 analogix_dp_reset(dp); 595 596 analogix_dp_swreset(dp); 597 598 analogix_dp_init_analog_param(dp); 599 analogix_dp_init_interrupt(dp); 600 601 /* SW defined function Normal operation */ 602 analogix_dp_enable_sw_function(dp); 603 604 analogix_dp_config_interrupt(dp); 605 analogix_dp_init_analog_func(dp); 606 607 analogix_dp_init_hpd(dp); 608 analogix_dp_init_aux(dp); 609 } 610 611 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 612 { 613 int i; 614 unsigned char sum = 0; 615 616 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 617 sum = sum + edid_data[i]; 618 619 return sum; 620 } 621 622 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 623 { 624 unsigned char *edid = dp->edid; 625 unsigned int extend_block = 0; 626 unsigned char test_vector; 627 int retval; 628 629 /* 630 * EDID device address is 0x50. 631 * However, if necessary, you must have set upper address 632 * into E-EDID in I2C device, 0x30. 633 */ 634 635 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 636 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 637 EDID_EXTENSION_FLAG, 638 &extend_block); 639 if (retval) 640 return retval; 641 642 if (extend_block > 0) { 643 debug("EDID data includes a single extension!\n"); 644 645 /* Read EDID data */ 646 retval = analogix_dp_read_bytes_from_i2c(dp, 647 I2C_EDID_DEVICE_ADDR, 648 EDID_HEADER_PATTERN, 649 EDID_BLOCK_LENGTH, 650 &edid[EDID_HEADER_PATTERN]); 651 if (retval < 0) 652 return retval; 653 654 if (analogix_dp_calc_edid_check_sum(edid)) 655 return -EINVAL; 656 657 /* Read additional EDID data */ 658 retval = analogix_dp_read_bytes_from_i2c(dp, 659 I2C_EDID_DEVICE_ADDR, 660 EDID_BLOCK_LENGTH, 661 EDID_BLOCK_LENGTH, 662 &edid[EDID_BLOCK_LENGTH]); 663 if (retval < 0) 664 return retval; 665 666 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 667 return -EINVAL; 668 669 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 670 &test_vector); 671 if (test_vector & DP_TEST_LINK_EDID_READ) { 672 analogix_dp_write_byte_to_dpcd(dp, 673 DP_TEST_EDID_CHECKSUM, 674 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 675 analogix_dp_write_byte_to_dpcd(dp, 676 DP_TEST_RESPONSE, 677 DP_TEST_EDID_CHECKSUM_WRITE); 678 } 679 } else { 680 dev_info(dp->dev, 681 "EDID data does not include any extensions.\n"); 682 683 /* Read EDID data */ 684 retval = analogix_dp_read_bytes_from_i2c(dp, 685 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 686 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 687 if (retval < 0) 688 return retval; 689 690 if (analogix_dp_calc_edid_check_sum(edid)) 691 return -EINVAL; 692 693 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 694 &test_vector); 695 if (test_vector & DP_TEST_LINK_EDID_READ) { 696 analogix_dp_write_byte_to_dpcd(dp, 697 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 698 analogix_dp_write_byte_to_dpcd(dp, 699 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 700 } 701 } 702 703 return 0; 704 } 705 706 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 707 { 708 u8 buf[12]; 709 int i, try = 5; 710 int retval; 711 712 retry: 713 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 714 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 715 716 if (retval && try--) { 717 mdelay(10); 718 goto retry; 719 } 720 721 if (retval) 722 return retval; 723 724 /* Read EDID */ 725 for (i = 0; i < 3; i++) { 726 retval = analogix_dp_read_edid(dp); 727 if (!retval) 728 break; 729 } 730 731 return retval; 732 } 733 734 static int analogix_dp_connector_pre_init(struct display_state *state) 735 { 736 struct connector_state *conn_state = &state->conn_state; 737 738 conn_state->type = DRM_MODE_CONNECTOR_eDP; 739 740 return 0; 741 } 742 743 static int analogix_dp_connector_init(struct display_state *state) 744 { 745 struct connector_state *conn_state = &state->conn_state; 746 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 747 748 conn_state->output_if |= VOP_OUTPUT_IF_eDP0; 749 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 750 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 751 752 reset_assert_bulk(&dp->resets); 753 udelay(1); 754 reset_deassert_bulk(&dp->resets); 755 756 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 757 generic_phy_power_on(&dp->phy); 758 analogix_dp_init_dp(dp); 759 760 return 0; 761 } 762 763 static int analogix_dp_connector_get_edid(struct display_state *state) 764 { 765 struct connector_state *conn_state = &state->conn_state; 766 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 767 int ret; 768 769 ret = analogix_dp_handle_edid(dp); 770 if (ret) { 771 dev_err(dp->dev, "failed to get edid\n"); 772 return ret; 773 } 774 775 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 776 777 return 0; 778 } 779 780 static int analogix_dp_connector_enable(struct display_state *state) 781 { 782 struct connector_state *conn_state = &state->conn_state; 783 struct crtc_state *crtc_state = &state->crtc_state; 784 const struct rockchip_connector *connector = conn_state->connector; 785 const struct rockchip_dp_chip_data *pdata = connector->data; 786 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 787 struct video_info *video = &dp->video_info; 788 u32 val; 789 int ret; 790 791 if (pdata->lcdsel_grf_reg) { 792 if (crtc_state->crtc_id) 793 val = pdata->lcdsel_lit; 794 else 795 val = pdata->lcdsel_big; 796 797 writel(val, syscon_get_first_range(ROCKCHIP_SYSCON_GRF) + pdata->lcdsel_grf_reg); 798 } 799 800 switch (conn_state->bpc) { 801 case 12: 802 video->color_depth = COLOR_12; 803 break; 804 case 10: 805 video->color_depth = COLOR_10; 806 break; 807 case 6: 808 video->color_depth = COLOR_6; 809 break; 810 case 8: 811 default: 812 video->color_depth = COLOR_8; 813 break; 814 } 815 816 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 817 dp->video_info.max_link_rate); 818 if (ret) { 819 dev_err(dp->dev, "unable to do link train\n"); 820 return ret; 821 } 822 823 analogix_dp_enable_scramble(dp, 1); 824 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 825 analogix_dp_enable_enhanced_mode(dp, 1); 826 827 analogix_dp_init_video(dp); 828 ret = analogix_dp_config_video(dp); 829 if (ret) { 830 dev_err(dp->dev, "unable to config video\n"); 831 return ret; 832 } 833 834 return 0; 835 } 836 837 static int analogix_dp_connector_disable(struct display_state *state) 838 { 839 /* TODO */ 840 841 return 0; 842 } 843 844 static int analogix_dp_connector_detect(struct display_state *state) 845 { 846 struct connector_state *conn_state = &state->conn_state; 847 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 848 849 return analogix_dp_detect(dp); 850 } 851 852 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 853 .pre_init = analogix_dp_connector_pre_init, 854 .init = analogix_dp_connector_init, 855 .get_edid = analogix_dp_connector_get_edid, 856 .enable = analogix_dp_connector_enable, 857 .disable = analogix_dp_connector_disable, 858 .detect = analogix_dp_connector_detect, 859 }; 860 861 static int analogix_dp_probe(struct udevice *dev) 862 { 863 struct analogix_dp_device *dp = dev_get_priv(dev); 864 const struct rockchip_connector *connector = 865 (const struct rockchip_connector *)dev_get_driver_data(dev); 866 const struct rockchip_dp_chip_data *pdata = connector->data; 867 int ret; 868 869 dp->reg_base = dev_read_addr_ptr(dev); 870 871 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 872 if (dp->id < 0) 873 dp->id = 0; 874 ret = reset_get_bulk(dev, &dp->resets); 875 if (ret) { 876 dev_err(dev, "failed to get reset control: %d\n", ret); 877 return ret; 878 } 879 880 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 881 GPIOD_IS_IN); 882 if (ret && ret != -ENOENT) { 883 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 884 return ret; 885 } 886 887 generic_phy_get_by_name(dev, "dp", &dp->phy); 888 889 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 890 891 dp->plat_data.dev_type = ROCKCHIP_DP; 892 dp->plat_data.subdev_type = pdata->chip_type; 893 dp->plat_data.ssc = pdata->ssc; 894 /* 895 * Like Rockchip DisplayPort TRM indicate that "Main link 896 * containing 4 physical lanes of 2.7/1.62 Gbps/lane". 897 */ 898 dp->video_info.max_link_rate = 0x0A; 899 dp->video_info.max_lane_count = 0x04; 900 901 dp->dev = dev; 902 903 return 0; 904 } 905 906 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 907 .lcdsel_grf_reg = 0x025c, 908 .lcdsel_big = 0 | BIT(21), 909 .lcdsel_lit = BIT(5) | BIT(21), 910 .chip_type = RK3288_DP, 911 }; 912 913 static const struct rockchip_connector rk3288_edp_driver_data = { 914 .funcs = &analogix_dp_connector_funcs, 915 .data = &rk3288_edp_platform_data, 916 }; 917 918 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 919 .chip_type = RK3368_EDP, 920 }; 921 922 static const struct rockchip_connector rk3368_edp_driver_data = { 923 .funcs = &analogix_dp_connector_funcs, 924 .data = &rk3368_edp_platform_data, 925 }; 926 927 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 928 .lcdsel_grf_reg = 0x6250, 929 .lcdsel_big = 0 | BIT(21), 930 .lcdsel_lit = BIT(5) | BIT(21), 931 .chip_type = RK3399_EDP, 932 }; 933 934 static const struct rockchip_connector rk3399_edp_driver_data = { 935 .funcs = &analogix_dp_connector_funcs, 936 .data = &rk3399_edp_platform_data, 937 }; 938 939 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 940 .chip_type = RK3568_EDP, 941 .ssc = true, 942 }; 943 944 static const struct rockchip_connector rk3568_edp_driver_data = { 945 .funcs = &analogix_dp_connector_funcs, 946 .data = &rk3568_edp_platform_data, 947 }; 948 949 static const struct udevice_id analogix_dp_ids[] = { 950 { 951 .compatible = "rockchip,rk3288-dp", 952 .data = (ulong)&rk3288_edp_driver_data, 953 }, { 954 .compatible = "rockchip,rk3368-edp", 955 .data = (ulong)&rk3368_edp_driver_data, 956 }, { 957 .compatible = "rockchip,rk3399-edp", 958 .data = (ulong)&rk3399_edp_driver_data, 959 }, { 960 .compatible = "rockchip,rk3568-edp", 961 .data = (ulong)&rk3568_edp_driver_data, 962 }, 963 {} 964 }; 965 966 U_BOOT_DRIVER(analogix_dp) = { 967 .name = "analogix_dp", 968 .id = UCLASS_DISPLAY, 969 .of_match = analogix_dp_ids, 970 .probe = analogix_dp_probe, 971 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 972 }; 973