1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/bitfield.h> 17 #include <linux/list.h> 18 #include <linux/media-bus-format.h> 19 #include <syscon.h> 20 #include <asm/arch-rockchip/clock.h> 21 #include <asm/gpio.h> 22 23 #include "rockchip_display.h" 24 #include "rockchip_crtc.h" 25 #include "rockchip_connector.h" 26 #include "analogix_dp.h" 27 28 #define RK3588_GRF_VO1_CON0 0x0000 29 #define EDP_MODE BIT(0) 30 #define RK3588_GRF_VO1_CON1 0x0004 31 32 /** 33 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 34 * @lcdsel_grf_reg: grf register offset of lcdc select 35 * @lcdsel_big: reg value of selecting vop big for eDP 36 * @lcdsel_lit: reg value of selecting vop little for eDP 37 * @chip_type: specific chip type 38 * @ssc: check if SSC is supported by source 39 * @max_link_rate: max supported link rate 40 * @max_lane_count: max supported lane count 41 * @format_yuv: check if yuv color format is supported 42 * @max_bpc: max supported bpc which set to 8 by default 43 */ 44 struct rockchip_dp_chip_data { 45 u32 lcdsel_grf_reg; 46 u32 lcdsel_big; 47 u32 lcdsel_lit; 48 u32 chip_type; 49 bool ssc; 50 51 u32 max_link_rate; 52 u32 max_lane_count; 53 bool format_yuv; 54 u8 max_bpc; 55 }; 56 57 static const struct analogix_dp_output_format possible_output_fmts[] = { 58 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 10 }, 59 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 8 }, 60 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 6 }, 61 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 10 }, 62 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 8}, 63 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 10 }, 64 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 8 }, 65 }; 66 67 static u8 analogix_dp_get_output_bpp(const struct analogix_dp_output_format *fmt) 68 { 69 switch (fmt->color_format) { 70 case DRM_COLOR_FORMAT_YCRCB422: 71 return fmt->bpc * 2; 72 case DRM_COLOR_FORMAT_RGB444: 73 case DRM_COLOR_FORMAT_YCRCB444: 74 default: 75 return fmt->bpc * 3; 76 } 77 } 78 79 static int 80 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 81 bool enable) 82 { 83 u8 data; 84 int ret; 85 86 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); 87 if (ret != 1) 88 return ret; 89 90 if (enable) 91 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 92 DP_LANE_COUNT_ENHANCED_FRAME_EN | 93 DPCD_LANE_COUNT_SET(data)); 94 else 95 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 96 DPCD_LANE_COUNT_SET(data)); 97 98 return ret < 0 ? ret : 0; 99 } 100 101 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 102 { 103 bool enhanced_frame_en; 104 u8 data; 105 int ret; 106 107 enhanced_frame_en = drm_dp_enhanced_frame_cap(dp->dpcd); 108 109 ret = analogix_dp_enable_rx_to_enhanced_mode(dp, enhanced_frame_en); 110 if (ret < 0) 111 return ret; 112 113 if (!enhanced_frame_en) { 114 /* 115 * As the Table 3-4 in eDP v1.2 spec: 116 * DPCD 0000Dh: 117 * Bit 1 = FRAMING_CHANGE_CAPABLE 118 * A setting of 1 indicates that this is an eDP device that 119 * uses only Enhanced Framing, independently of the setting by 120 * the source of ENHANCED_FRAME_EN 121 * 122 * And as the Table 3-3 in eDP v1.4 spec: 123 * DPCD 0000Dh: 124 * Bit 1 = RESERVED for eDP 125 * New to eDP v1.4.(Read all 0s) 126 */ 127 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_CONFIGURATION_CAP, 128 &data); 129 if (ret < 0) 130 return ret; 131 132 enhanced_frame_en = !!(data & DP_FRAMING_CHANGE_CAP); 133 } 134 135 analogix_dp_enable_enhanced_mode(dp, enhanced_frame_en); 136 137 return 0; 138 } 139 140 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 141 { 142 int ret; 143 144 analogix_dp_set_training_pattern(dp, DP_NONE); 145 146 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 147 DP_TRAINING_PATTERN_DISABLE); 148 149 return ret < 0 ? ret : 0; 150 } 151 152 static int analogix_dp_enable_sink_to_assr_mode(struct analogix_dp_device *dp, bool enable) 153 { 154 u8 data; 155 int ret; 156 157 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_CONFIGURATION_SET, &data); 158 if (ret != 1) 159 return ret; 160 161 if (enable) 162 ret = drm_dp_dpcd_writeb(&dp->aux, DP_EDP_CONFIGURATION_SET, 163 data | DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 164 else 165 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 166 data & ~DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 167 168 return ret < 0 ? ret : 0; 169 } 170 171 static int analogix_dp_set_assr_mode(struct analogix_dp_device *dp) 172 { 173 bool assr_en; 174 int ret; 175 176 assr_en = drm_dp_alternate_scrambler_reset_cap(dp->dpcd); 177 178 ret = analogix_dp_enable_sink_to_assr_mode(dp, assr_en); 179 if (ret < 0) 180 return ret; 181 182 analogix_dp_enable_assr_mode(dp, assr_en); 183 184 return 0; 185 } 186 187 static int analogix_dp_link_start(struct analogix_dp_device *dp) 188 { 189 u8 buf[4]; 190 int lane, lane_count, retval; 191 192 lane_count = dp->link_train.lane_count; 193 194 dp->link_train.lt_state = CLOCK_RECOVERY; 195 dp->link_train.eq_loop = 0; 196 197 for (lane = 0; lane < lane_count; lane++) 198 dp->link_train.cr_loop[lane] = 0; 199 200 /* Set link rate and count as you want to establish */ 201 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 202 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 203 204 if (dp->nr_link_rate_table) { 205 /* Setup DP_LINK_RATE_SET for eDP 1.4 and later */ 206 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, dp->link_train.lane_count); 207 drm_dp_dpcd_writeb(&dp->aux, DP_LINK_RATE_SET, dp->link_rate_select); 208 } else { 209 /* Setup DP_LINK_BW_SET for eDP 1.3 and earlier */ 210 buf[0] = dp->link_train.link_rate; 211 buf[1] = dp->link_train.lane_count; 212 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2); 213 if (retval < 0) 214 return retval; 215 } 216 217 /* Spread AMP if required, enable 8b/10b coding */ 218 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 219 buf[1] = DP_SET_ANSI_8B10B; 220 retval = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 2); 221 if (retval < 0) 222 return retval; 223 224 /* set ASSR if available */ 225 retval = analogix_dp_set_assr_mode(dp); 226 if (retval < 0) { 227 dev_err(dp->dev, "failed to set assr mode\n"); 228 return retval; 229 } 230 231 /* set enhanced mode if available */ 232 retval = analogix_dp_set_enhanced_mode(dp); 233 if (retval < 0) { 234 dev_err(dp->dev, "failed to set enhance mode\n"); 235 return retval; 236 } 237 238 /* Set TX voltage-swing and pre-emphasis to minimum */ 239 for (lane = 0; lane < lane_count; lane++) 240 dp->link_train.training_lane[lane] = 241 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 242 DP_TRAIN_PRE_EMPH_LEVEL_0; 243 analogix_dp_set_lane_link_training(dp); 244 245 /* Set training pattern 1 */ 246 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 247 248 /* Set RX training pattern */ 249 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 250 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 251 if (retval < 0) 252 return retval; 253 254 for (lane = 0; lane < lane_count; lane++) 255 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 256 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 257 258 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, 259 lane_count); 260 if (retval < 0) 261 return retval; 262 263 return 0; 264 } 265 266 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 267 { 268 int shift = (lane & 1) * 4; 269 u8 link_value = link_status[lane >> 1]; 270 271 return (link_value >> shift) & 0xf; 272 } 273 274 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 275 { 276 int lane; 277 u8 lane_status; 278 279 for (lane = 0; lane < lane_count; lane++) { 280 lane_status = analogix_dp_get_lane_status(link_status, lane); 281 if ((lane_status & DP_LANE_CR_DONE) == 0) 282 return -EINVAL; 283 } 284 return 0; 285 } 286 287 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 288 int lane_count) 289 { 290 int lane; 291 u8 lane_status; 292 293 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 294 return -EINVAL; 295 296 for (lane = 0; lane < lane_count; lane++) { 297 lane_status = analogix_dp_get_lane_status(link_status, lane); 298 lane_status &= DP_CHANNEL_EQ_BITS; 299 if (lane_status != DP_CHANNEL_EQ_BITS) 300 return -EINVAL; 301 } 302 303 return 0; 304 } 305 306 static unsigned char 307 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 308 { 309 int shift = (lane & 1) * 4; 310 u8 link_value = adjust_request[lane >> 1]; 311 312 return (link_value >> shift) & 0x3; 313 } 314 315 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 316 u8 adjust_request[2], 317 int lane) 318 { 319 int shift = (lane & 1) * 4; 320 u8 link_value = adjust_request[lane >> 1]; 321 322 return ((link_value >> shift) & 0xc) >> 2; 323 } 324 325 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 326 { 327 analogix_dp_training_pattern_dis(dp); 328 analogix_dp_set_enhanced_mode(dp); 329 330 dp->link_train.lt_state = FAILED; 331 } 332 333 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 334 u8 adjust_request[2]) 335 { 336 int lane, lane_count; 337 u8 voltage_swing, pre_emphasis, training_lane; 338 339 lane_count = dp->link_train.lane_count; 340 for (lane = 0; lane < lane_count; lane++) { 341 voltage_swing = analogix_dp_get_adjust_request_voltage( 342 adjust_request, lane); 343 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 344 adjust_request, lane); 345 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 346 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 347 348 if (voltage_swing == VOLTAGE_LEVEL_3) 349 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 350 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 351 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 352 353 dp->link_train.training_lane[lane] = training_lane; 354 } 355 } 356 357 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp) 358 { 359 bool source_tps3_supported, sink_tps3_supported; 360 u8 dpcd = 0; 361 362 source_tps3_supported = 363 dp->video_info.max_link_rate == DP_LINK_BW_5_4; 364 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &dpcd); 365 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; 366 367 return source_tps3_supported && sink_tps3_supported; 368 } 369 370 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 371 { 372 int lane, lane_count, retval; 373 u8 voltage_swing, pre_emphasis, training_lane; 374 u8 link_status[2], adjust_request[2]; 375 u8 training_pattern = TRAINING_PTN2; 376 377 drm_dp_link_train_clock_recovery_delay(dp->dpcd); 378 379 lane_count = dp->link_train.lane_count; 380 381 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 382 if (retval < 0) 383 return retval; 384 385 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 386 if (analogix_dp_tps3_supported(dp)) 387 training_pattern = TRAINING_PTN3; 388 389 /* set training pattern for EQ */ 390 analogix_dp_set_training_pattern(dp, training_pattern); 391 392 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 393 DP_LINK_SCRAMBLING_DISABLE | 394 (training_pattern == TRAINING_PTN3 ? 395 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); 396 if (retval < 0) 397 return retval; 398 399 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 400 dp->link_train.lt_state = EQUALIZER_TRAINING; 401 402 return 0; 403 } else { 404 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 405 adjust_request, 2); 406 if (retval < 0) 407 return retval; 408 409 for (lane = 0; lane < lane_count; lane++) { 410 training_lane = analogix_dp_get_lane_link_training( 411 dp, lane); 412 voltage_swing = analogix_dp_get_adjust_request_voltage( 413 adjust_request, lane); 414 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 415 adjust_request, lane); 416 417 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 418 voltage_swing && 419 DPCD_PRE_EMPHASIS_GET(training_lane) == 420 pre_emphasis) 421 dp->link_train.cr_loop[lane]++; 422 423 /* 424 * In DP spec 1.3, Condition of CR fail are 425 * outlined in section 3.5.1.2.2.1, figure 3-20: 426 * 427 * 1. Maximum Voltage Swing reached 428 * 2. Same Voltage five times 429 */ 430 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 431 DPCD_VOLTAGE_SWING_GET(training_lane) == VOLTAGE_LEVEL_3) { 432 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 433 dp->link_train.cr_loop[lane], 434 voltage_swing, pre_emphasis); 435 analogix_dp_reduce_link_rate(dp); 436 return -EIO; 437 } 438 } 439 } 440 441 analogix_dp_get_adjust_training_lane(dp, adjust_request); 442 analogix_dp_set_lane_link_training(dp); 443 444 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 445 dp->link_train.training_lane, lane_count); 446 if (retval < 0) 447 return retval; 448 449 return 0; 450 } 451 452 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 453 { 454 int lane_count, retval; 455 u32 reg; 456 u8 link_align, link_status[2], adjust_request[2]; 457 458 drm_dp_link_train_channel_eq_delay(dp->dpcd); 459 460 lane_count = dp->link_train.lane_count; 461 462 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 463 if (retval < 0) 464 return retval; 465 466 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 467 analogix_dp_reduce_link_rate(dp); 468 return -EIO; 469 } 470 471 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 472 if (retval < 0) 473 return retval; 474 475 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 476 /* traing pattern Set to Normal */ 477 retval = analogix_dp_training_pattern_dis(dp); 478 if (retval < 0) 479 return retval; 480 481 printf("Link Training success!\n"); 482 483 analogix_dp_get_link_bandwidth(dp, ®); 484 dp->link_train.link_rate = reg; 485 analogix_dp_get_lane_count(dp, ®); 486 dp->link_train.lane_count = reg; 487 488 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 489 dp->link_train.link_rate, dp->link_train.lane_count); 490 491 dp->link_train.lt_state = FINISHED; 492 493 return 0; 494 } 495 496 /* not all locked */ 497 dp->link_train.eq_loop++; 498 499 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 500 dev_dbg(dp->dev, "EQ Max loop\n"); 501 analogix_dp_reduce_link_rate(dp); 502 return -EIO; 503 } 504 505 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, adjust_request, 2); 506 if (retval < 0) 507 return retval; 508 509 analogix_dp_get_adjust_training_lane(dp, adjust_request); 510 analogix_dp_set_lane_link_training(dp); 511 512 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 513 dp->link_train.training_lane, lane_count); 514 if (retval < 0) 515 return retval; 516 517 return 0; 518 } 519 520 static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp, 521 const struct drm_display_mode *mode, u32 bpp, 522 unsigned int rate, unsigned int lanes) 523 { 524 u32 max_bw, req_bw; 525 526 req_bw = mode->clock * bpp / 8; 527 max_bw = lanes * rate; 528 if (req_bw > max_bw) 529 return false; 530 531 return true; 532 } 533 534 static bool analogix_dp_link_config_validate(u8 link_rate, u8 lane_count) 535 { 536 switch (link_rate) { 537 case DP_LINK_BW_1_62: 538 case DP_LINK_BW_2_7: 539 case DP_LINK_BW_5_4: 540 /* Supported link rate in eDP 1.4 */ 541 case EDP_LINK_BW_2_16: 542 case EDP_LINK_BW_2_43: 543 case EDP_LINK_BW_3_24: 544 case EDP_LINK_BW_4_32: 545 break; 546 default: 547 return false; 548 } 549 550 switch (lane_count) { 551 case LANE_COUNT1: 552 case LANE_COUNT2: 553 case LANE_COUNT4: 554 break; 555 default: 556 return false; 557 } 558 559 return true; 560 } 561 562 static int analogix_dp_select_link_rate_from_table(struct analogix_dp_device *dp) 563 { 564 int i; 565 u8 bw_code; 566 u32 max_link_rate = drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate); 567 568 for (i = 0; i < dp->nr_link_rate_table; i++) { 569 bw_code = drm_dp_link_rate_to_bw_code(dp->link_rate_table[i]); 570 571 if (!analogix_dp_bandwidth_ok(dp, &dp->video_info.mode, 572 analogix_dp_get_output_bpp(dp->output_fmt), 573 dp->link_rate_table[i], dp->link_train.lane_count)) 574 continue; 575 576 if (dp->link_rate_table[i] <= max_link_rate && 577 analogix_dp_link_config_validate(bw_code, dp->link_train.lane_count)) { 578 dp->link_rate_select = i; 579 return bw_code; 580 } 581 } 582 583 return 0; 584 } 585 586 static int analogix_dp_select_rx_bandwidth(struct analogix_dp_device *dp) 587 { 588 if (dp->nr_link_rate_table) 589 /* 590 * Select the smallest one among link rates which meet 591 * the bandwidth requirement for eDP 1.4 and later. 592 */ 593 dp->link_train.link_rate = analogix_dp_select_link_rate_from_table(dp); 594 else 595 /* 596 * Select the smaller one between rx DP_MAX_LINK_RATE 597 * and the max link rate supported by the platform. 598 */ 599 dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate, 600 dp->video_info.max_link_rate); 601 if (!dp->link_train.link_rate) 602 return -EINVAL; 603 604 return 0; 605 } 606 607 static int analogix_dp_init_link_rate_table(struct analogix_dp_device *dp) 608 { 609 u8 link_rate_table[DP_MAX_SUPPORTED_RATES * 2]; 610 int i; 611 int ret; 612 613 ret = drm_dp_dpcd_read(&dp->aux, DP_SUPPORTED_LINK_RATES, link_rate_table, 614 sizeof(link_rate_table)); 615 if (ret < 0) 616 return ret; 617 618 for (i = 0; i < ARRAY_SIZE(link_rate_table) / 2; i++) { 619 int val = link_rate_table[2 * i] | link_rate_table[2 * i + 1] << 8; 620 621 if (val == 0) 622 break; 623 624 /* Convert to the link_rate as drm_dp_bw_code_to_link_rate() */ 625 dp->link_rate_table[i] = (val * 20); 626 } 627 dp->nr_link_rate_table = i; 628 629 return 0; 630 } 631 632 static int analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 633 u8 *bandwidth) 634 { 635 u8 data; 636 int ret; 637 638 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_DPCD_REV, &data); 639 if (ret == 1 && data >= DP_EDP_14) { 640 u32 max_link_rate; 641 642 /* As the Table 4-23 in eDP 1.4 spec, the link rate table is required */ 643 if (!dp->nr_link_rate_table) { 644 dev_info(dp->dev, "eDP version: 0x%02x supports link rate table\n", 645 data); 646 647 if (analogix_dp_init_link_rate_table(dp)) 648 dev_err(dp->dev, "failed to read link rate table: %d\n", 649 ret); 650 } 651 max_link_rate = dp->link_rate_table[dp->nr_link_rate_table - 1]; 652 *bandwidth = drm_dp_link_rate_to_bw_code(max_link_rate); 653 } else { 654 /* 655 * For DP rev.1.1, Maximum link rate of Main Link lanes 656 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 657 * For DP rev.1.2, Maximum link rate of Main Link lanes 658 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 659 */ 660 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data); 661 if (ret < 0) 662 return ret; 663 664 *bandwidth = data; 665 } 666 667 return 0; 668 } 669 670 static int analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 671 u8 *lane_count) 672 { 673 u8 data; 674 int ret; 675 676 /* 677 * For DP rev.1.1, Maximum number of Main Link lanes 678 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 679 */ 680 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 681 if (ret < 0) 682 return ret; 683 684 *lane_count = DPCD_MAX_LANE_COUNT(data); 685 686 return 0; 687 } 688 689 static int analogix_dp_init_training(struct analogix_dp_device *dp, 690 enum link_lane_count_type max_lane, 691 int max_rate) 692 { 693 u8 dpcd; 694 695 /* 696 * MACRO_RST must be applied after the PLL_LOCK to avoid 697 * the DP inter pair skew issue for at least 10 us 698 */ 699 analogix_dp_reset_macro(dp); 700 701 /* Setup TX lane count */ 702 dp->link_train.lane_count = min_t(u32, dp->link_train.lane_count, max_lane); 703 704 /* Setup TX lane rate */ 705 if (analogix_dp_select_rx_bandwidth(dp)) { 706 dev_err(dp->dev, "Select rx bandwidth failed\n"); 707 return -EINVAL; 708 } 709 710 drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &dpcd); 711 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 712 713 /* All DP analog module power up */ 714 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 715 716 return 0; 717 } 718 719 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 720 { 721 int retval = 0, training_finished = 0; 722 723 dp->link_train.lt_state = START; 724 725 /* Process here */ 726 while (!retval && !training_finished) { 727 switch (dp->link_train.lt_state) { 728 case START: 729 retval = analogix_dp_link_start(dp); 730 if (retval) 731 dev_err(dp->dev, "LT link start failed!\n"); 732 break; 733 case CLOCK_RECOVERY: 734 retval = analogix_dp_process_clock_recovery(dp); 735 if (retval) 736 dev_err(dp->dev, "LT CR failed!\n"); 737 break; 738 case EQUALIZER_TRAINING: 739 retval = analogix_dp_process_equalizer_training(dp); 740 if (retval) 741 dev_err(dp->dev, "LT EQ failed!\n"); 742 break; 743 case FINISHED: 744 training_finished = 1; 745 break; 746 case FAILED: 747 return -EREMOTEIO; 748 } 749 } 750 751 return retval; 752 } 753 754 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 755 u32 count, u32 bwtype) 756 { 757 int i, ret; 758 759 for (i = 0; i < 5; i++) { 760 ret = analogix_dp_init_training(dp, count, bwtype); 761 if (ret < 0) { 762 dev_err(dp->dev, "failed to init training\n"); 763 return ret; 764 } 765 766 ret = analogix_dp_sw_link_training(dp); 767 if (!ret) 768 break; 769 } 770 771 return ret; 772 } 773 774 static int analogix_dp_config_video(struct analogix_dp_device *dp) 775 { 776 int timeout_loop = 0; 777 int done_count = 0; 778 779 analogix_dp_config_video_slave_mode(dp); 780 781 analogix_dp_set_video_color_format(dp); 782 783 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 784 dev_err(dp->dev, "PLL is not locked yet.\n"); 785 return -EINVAL; 786 } 787 788 for (;;) { 789 timeout_loop++; 790 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 791 break; 792 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 793 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 794 return -ETIMEDOUT; 795 } 796 797 udelay(2); 798 } 799 800 /* Set to use the register calculated M/N video */ 801 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 802 803 /* For video bist, Video timing must be generated by register */ 804 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_REGISTER); 805 806 /* Disable video mute */ 807 analogix_dp_enable_video_mute(dp, 0); 808 809 /* Configure video slave mode */ 810 analogix_dp_enable_video_master(dp, 0); 811 812 /* Enable video input */ 813 analogix_dp_start_video(dp); 814 815 timeout_loop = 0; 816 817 for (;;) { 818 timeout_loop++; 819 if (analogix_dp_is_video_stream_on(dp) == 0) { 820 done_count++; 821 if (done_count > 10) 822 break; 823 } else if (done_count) { 824 done_count = 0; 825 } 826 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 827 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 828 return -ETIMEDOUT; 829 } 830 831 udelay(1001); 832 } 833 834 return 0; 835 } 836 837 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp, 838 bool enable) 839 { 840 u8 data; 841 int ret; 842 843 if (enable) { 844 analogix_dp_enable_scrambling(dp); 845 846 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, 847 &data); 848 if (ret != 1) 849 return ret; 850 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 851 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 852 } else { 853 analogix_dp_disable_scrambling(dp); 854 855 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, 856 &data); 857 if (ret != 1) 858 return ret; 859 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 860 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 861 } 862 return ret < 0 ? ret : 0; 863 } 864 865 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 866 { 867 analogix_dp_reset(dp); 868 869 analogix_dp_swreset(dp); 870 871 analogix_dp_init_analog_param(dp); 872 analogix_dp_init_interrupt(dp); 873 874 /* SW defined function Normal operation */ 875 analogix_dp_enable_sw_function(dp); 876 877 analogix_dp_config_interrupt(dp); 878 analogix_dp_init_analog_func(dp); 879 880 analogix_dp_init_hpd(dp); 881 analogix_dp_init_aux(dp); 882 } 883 884 static int analogix_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 885 { 886 struct connector_state *conn_state = &state->conn_state; 887 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 888 889 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; 890 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 891 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 892 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 893 894 reset_assert_bulk(&dp->resets); 895 udelay(1); 896 reset_deassert_bulk(&dp->resets); 897 898 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 899 generic_phy_set_mode(&dp->phy, PHY_MODE_DP); 900 generic_phy_power_on(&dp->phy); 901 analogix_dp_init_dp(dp); 902 903 return 0; 904 } 905 906 static int analogix_dp_connector_get_edid(struct rockchip_connector *conn, 907 struct display_state *state) 908 { 909 struct connector_state *conn_state = &state->conn_state; 910 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 911 int ret; 912 913 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 914 915 return ret; 916 } 917 918 static int analogix_dp_link_power_up(struct analogix_dp_device *dp) 919 { 920 u8 value; 921 int ret; 922 923 if (dp->dpcd[DP_DPCD_REV] < 0x11) 924 return 0; 925 926 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 927 if (ret < 0) 928 return ret; 929 930 value &= ~DP_SET_POWER_MASK; 931 value |= DP_SET_POWER_D0; 932 933 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 934 if (ret < 0) 935 return ret; 936 937 mdelay(1); 938 939 return 0; 940 } 941 942 static int analogix_dp_link_power_down(struct analogix_dp_device *dp) 943 { 944 u8 value; 945 int ret; 946 947 if (dp->dpcd[DP_DPCD_REV] < 0x11) 948 return 0; 949 950 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 951 if (ret < 0) 952 return ret; 953 954 value &= ~DP_SET_POWER_MASK; 955 value |= DP_SET_POWER_D3; 956 957 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 958 if (ret < 0) 959 return ret; 960 961 return 0; 962 } 963 964 static u32 analogix_dp_get_output_format(struct analogix_dp_device *dp, u32 bus_format) 965 { 966 unsigned int i; 967 968 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 969 const struct analogix_dp_output_format *fmt = &possible_output_fmts[i]; 970 971 if (fmt->bus_format == bus_format) 972 break; 973 } 974 975 if (i == ARRAY_SIZE(possible_output_fmts)) 976 return 1; 977 978 return i; 979 } 980 981 static u32 analogix_dp_get_output_format_by_edid(struct analogix_dp_device *dp, 982 struct hdmi_edid_data *edid_data) 983 { 984 unsigned int i; 985 986 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 987 const struct analogix_dp_output_format *fmt = &possible_output_fmts[i]; 988 989 if (fmt->bpc > edid_data->display_info.bpc || fmt->bpc > dp->plat_data.max_bpc) 990 continue; 991 992 if (!(edid_data->display_info.color_formats & fmt->color_format)) 993 continue; 994 995 if (!analogix_dp_bandwidth_ok(dp, edid_data->preferred_mode, 996 analogix_dp_get_output_bpp(fmt), 997 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate), 998 dp->link_train.lane_count)) 999 continue; 1000 1001 break; 1002 } 1003 1004 if (i == ARRAY_SIZE(possible_output_fmts)) 1005 return 1; 1006 1007 return i; 1008 } 1009 1010 static int analogix_dp_connector_enable(struct rockchip_connector *conn, 1011 struct display_state *state) 1012 { 1013 struct connector_state *conn_state = &state->conn_state; 1014 struct crtc_state *crtc_state = &state->crtc_state; 1015 const struct rockchip_dp_chip_data *pdata = 1016 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1017 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1018 struct video_info *video = &dp->video_info; 1019 struct drm_display_mode mode; 1020 u32 fmt_id; 1021 u32 val; 1022 int ret; 1023 1024 drm_mode_copy(&video->mode, &conn_state->mode); 1025 1026 if (pdata->lcdsel_grf_reg) { 1027 if (crtc_state->crtc_id) 1028 val = pdata->lcdsel_lit; 1029 else 1030 val = pdata->lcdsel_big; 1031 1032 regmap_write(dp->grf, pdata->lcdsel_grf_reg, val); 1033 } 1034 1035 if (pdata->chip_type == RK3588_EDP) 1036 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 1037 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); 1038 1039 if (!dp->output_fmt) { 1040 fmt_id = analogix_dp_get_output_format(dp, conn_state->bus_format); 1041 dp->output_fmt = &possible_output_fmts[fmt_id]; 1042 } 1043 1044 switch (dp->output_fmt->bpc) { 1045 case 12: 1046 video->color_depth = COLOR_12; 1047 break; 1048 case 10: 1049 video->color_depth = COLOR_10; 1050 break; 1051 case 6: 1052 video->color_depth = COLOR_6; 1053 break; 1054 case 8: 1055 default: 1056 video->color_depth = COLOR_8; 1057 break; 1058 } 1059 if (dp->output_fmt->color_format == DRM_COLOR_FORMAT_YCRCB444) { 1060 video->color_space = COLOR_YCBCR444; 1061 video->ycbcr_coeff = COLOR_YCBCR709; 1062 } else if (dp->output_fmt->color_format == DRM_COLOR_FORMAT_YCRCB422) { 1063 video->color_space = COLOR_YCBCR422; 1064 video->ycbcr_coeff = COLOR_YCBCR709; 1065 } else { 1066 video->color_space = COLOR_RGB; 1067 video->ycbcr_coeff = COLOR_YCBCR601; 1068 } 1069 1070 ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd, DP_RECEIVER_CAP_SIZE); 1071 if (ret < 0) { 1072 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret); 1073 return ret; 1074 } 1075 1076 ret = analogix_dp_link_power_up(dp); 1077 if (ret) { 1078 dev_err(dp->dev, "failed to power up link: %d\n", ret); 1079 return ret; 1080 } 1081 1082 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 1083 dp->video_info.max_link_rate); 1084 if (ret) { 1085 dev_err(dp->dev, "unable to do link train\n"); 1086 return ret; 1087 } 1088 1089 ret = analogix_dp_enable_scramble(dp, 1); 1090 if (ret < 0) { 1091 dev_err(dp->dev, "can not enable scramble\n"); 1092 return ret; 1093 } 1094 1095 analogix_dp_init_video(dp); 1096 1097 drm_mode_copy(&mode, &conn_state->mode); 1098 if (conn->dual_channel_mode) 1099 drm_mode_convert_to_origin_mode(&mode); 1100 analogix_dp_set_video_format(dp, &mode); 1101 1102 if (dp->video_bist_enable) 1103 analogix_dp_video_bist_enable(dp); 1104 1105 ret = analogix_dp_config_video(dp); 1106 if (ret) { 1107 dev_err(dp->dev, "unable to config video\n"); 1108 return ret; 1109 } 1110 1111 return 0; 1112 } 1113 1114 static int analogix_dp_connector_disable(struct rockchip_connector *conn, 1115 struct display_state *state) 1116 { 1117 const struct rockchip_dp_chip_data *pdata = 1118 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1119 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1120 1121 if (!analogix_dp_get_plug_in_status(dp)) 1122 analogix_dp_link_power_down(dp); 1123 1124 if (pdata->chip_type == RK3588_EDP) 1125 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 1126 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 0)); 1127 1128 return 0; 1129 } 1130 1131 static int analogix_dp_connector_detect(struct rockchip_connector *conn, 1132 struct display_state *state) 1133 { 1134 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1135 int ret; 1136 1137 if (analogix_dp_detect(dp)) { 1138 /* Initialize by reading RX's DPCD */ 1139 ret = analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 1140 if (ret) { 1141 dev_err(dp->dev, "failed to read max link rate\n"); 1142 return 0; 1143 } 1144 1145 ret = analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 1146 if (ret) { 1147 dev_err(dp->dev, "failed to read max lane count\n"); 1148 return 0; 1149 } 1150 1151 return 1; 1152 } else { 1153 return 0; 1154 } 1155 } 1156 1157 static int analogix_dp_connector_mode_valid(struct rockchip_connector *conn, 1158 struct display_state *state) 1159 { 1160 struct connector_state *conn_state = &state->conn_state; 1161 struct videomode vm; 1162 1163 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1164 1165 if (!vm.hfront_porch || !vm.hback_porch || !vm.vfront_porch || !vm.vback_porch) { 1166 dev_err(dp->dev, "front porch or back porch can not be 0\n"); 1167 return MODE_BAD; 1168 } 1169 1170 return MODE_OK; 1171 } 1172 1173 static int analogix_dp_mode_valid(struct analogix_dp_device *dp, struct hdmi_edid_data *edid_data) 1174 { 1175 struct drm_display_info *di = &edid_data->display_info; 1176 u32 max_link_rate, max_lane_count; 1177 u32 min_bpp; 1178 int i; 1179 1180 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1181 min_bpp = 16; 1182 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1183 min_bpp = 18; 1184 else 1185 min_bpp = 24; 1186 1187 max_link_rate = min_t(u32, dp->video_info.max_link_rate, dp->link_train.link_rate); 1188 max_lane_count = min_t(u32, dp->video_info.max_lane_count, dp->link_train.lane_count); 1189 for (i = 0; i < edid_data->modes; i++) { 1190 if (!analogix_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, 1191 drm_dp_bw_code_to_link_rate(max_link_rate), 1192 max_lane_count)) 1193 edid_data->mode_buf[i].invalid = true; 1194 } 1195 1196 return 0; 1197 } 1198 1199 static int analogix_dp_connector_get_timing(struct rockchip_connector *conn, 1200 struct display_state *state) 1201 { 1202 struct connector_state *conn_state = &state->conn_state; 1203 const struct rockchip_dp_chip_data *pdata = 1204 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1205 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1206 struct drm_display_mode *mode = &conn_state->mode; 1207 struct hdmi_edid_data edid_data; 1208 struct drm_display_mode *mode_buf; 1209 struct vop_rect rect; 1210 u32 yuv_fmts_mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422; 1211 u32 fmt_id; 1212 int ret, i; 1213 1214 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1215 if (!mode_buf) 1216 return -ENOMEM; 1217 1218 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1219 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1220 edid_data.mode_buf = mode_buf; 1221 1222 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1223 if (!ret) 1224 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1225 1226 if (ret < 0) { 1227 printf("failed to get edid\n"); 1228 goto err; 1229 } 1230 1231 if (!pdata->format_yuv) { 1232 if (edid_data.display_info.color_formats & yuv_fmts_mask) { 1233 printf("Swapping display color format from YUV to RGB\n"); 1234 edid_data.display_info.color_formats &= ~yuv_fmts_mask; 1235 edid_data.display_info.color_formats |= DRM_COLOR_FORMAT_RGB444; 1236 } 1237 } 1238 1239 if (state->conn_state.secondary) { 1240 rect.width = state->crtc_state.max_output.width / 2; 1241 rect.height = state->crtc_state.max_output.height / 2; 1242 } else { 1243 rect.width = state->crtc_state.max_output.width; 1244 rect.height = state->crtc_state.max_output.height; 1245 } 1246 1247 drm_mode_max_resolution_filter(&edid_data, &rect); 1248 analogix_dp_mode_valid(dp, &edid_data); 1249 1250 if (!drm_mode_prune_invalid(&edid_data)) { 1251 printf("can't find valid dp mode\n"); 1252 ret = -EINVAL; 1253 goto err; 1254 } 1255 1256 for (i = 0; i < edid_data.modes; i++) 1257 edid_data.mode_buf[i].vrefresh = drm_mode_vrefresh(&edid_data.mode_buf[i]); 1258 1259 drm_mode_sort(&edid_data); 1260 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1261 1262 fmt_id = analogix_dp_get_output_format_by_edid(dp, &edid_data); 1263 dp->output_fmt = &possible_output_fmts[fmt_id]; 1264 1265 switch (dp->output_fmt->color_format) { 1266 case DRM_COLOR_FORMAT_YCRCB422: 1267 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422; 1268 break; 1269 case DRM_COLOR_FORMAT_RGB444: 1270 case DRM_COLOR_FORMAT_YCRCB444: 1271 default: 1272 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1273 break; 1274 } 1275 1276 conn_state->bus_format = dp->output_fmt->bus_format; 1277 conn_state->bpc = dp->output_fmt->bpc; 1278 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 1279 if (dp->output_fmt->color_format == DRM_COLOR_FORMAT_RGB444) 1280 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 1281 else 1282 conn_state->color_range = DRM_COLOR_YCBCR_LIMITED_RANGE; 1283 1284 err: 1285 free(mode_buf); 1286 1287 return 0; 1288 } 1289 1290 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 1291 .init = analogix_dp_connector_init, 1292 .get_edid = analogix_dp_connector_get_edid, 1293 .enable = analogix_dp_connector_enable, 1294 .disable = analogix_dp_connector_disable, 1295 .detect = analogix_dp_connector_detect, 1296 .mode_valid = analogix_dp_connector_mode_valid, 1297 .get_timing = analogix_dp_connector_get_timing, 1298 }; 1299 1300 static u32 analogix_dp_parse_link_frequencies(struct analogix_dp_device *dp) 1301 { 1302 struct udevice *dev = dp->dev; 1303 const struct device_node *endpoint; 1304 u64 frequency = 0; 1305 1306 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 1307 if (!endpoint) 1308 return 0; 1309 1310 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 1311 return 0; 1312 1313 if (!frequency) 1314 return 0; 1315 1316 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 1317 1318 switch (frequency) { 1319 case 162000: 1320 case 270000: 1321 case 540000: 1322 break; 1323 default: 1324 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 1325 return 0; 1326 } 1327 1328 return frequency; 1329 } 1330 1331 static int analogix_dp_parse_dt(struct analogix_dp_device *dp) 1332 { 1333 struct udevice *dev = dp->dev; 1334 int len; 1335 u32 num_lanes; 1336 u32 max_link_rate; 1337 int ret; 1338 1339 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1340 dp->video_bist_enable = dev_read_bool(dev, "analogix,video-bist-enable"); 1341 dp->video_info.force_stream_valid = 1342 dev_read_bool(dev, "analogix,force-stream-valid"); 1343 1344 max_link_rate = analogix_dp_parse_link_frequencies(dp); 1345 if (max_link_rate && max_link_rate < drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate)) 1346 dp->video_info.max_link_rate = drm_dp_link_rate_to_bw_code(max_link_rate); 1347 1348 if (dev_read_prop(dev, "data-lanes", &len)) { 1349 num_lanes = len / sizeof(u32); 1350 if (num_lanes < 1 || num_lanes > 4 || num_lanes == 3) { 1351 dev_err(dev, "bad number of data lanes\n"); 1352 return -EINVAL; 1353 } 1354 1355 ret = dev_read_u32_array(dev, "data-lanes", dp->lane_map, 1356 num_lanes); 1357 if (ret) 1358 return ret; 1359 1360 dp->video_info.max_lane_count = num_lanes; 1361 } else { 1362 dp->lane_map[0] = 0; 1363 dp->lane_map[1] = 1; 1364 dp->lane_map[2] = 2; 1365 dp->lane_map[3] = 3; 1366 } 1367 1368 return 0; 1369 } 1370 1371 static int analogix_dp_ddc_init(struct analogix_dp_device *dp) 1372 { 1373 dp->aux.name = "analogix-dp"; 1374 dp->aux.dev = dp->dev; 1375 dp->aux.transfer = analogix_dp_aux_transfer; 1376 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1377 1378 return 0; 1379 } 1380 1381 static int analogix_dp_probe(struct udevice *dev) 1382 { 1383 struct analogix_dp_device *dp = dev_get_priv(dev); 1384 const struct rockchip_dp_chip_data *pdata = 1385 (const struct rockchip_dp_chip_data *)dev_get_driver_data(dev); 1386 struct udevice *syscon; 1387 int ret; 1388 1389 dp->reg_base = dev_read_addr_ptr(dev); 1390 1391 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 1392 if (dp->id < 0) 1393 dp->id = 0; 1394 1395 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1396 &syscon); 1397 if (!ret) { 1398 dp->grf = syscon_get_regmap(syscon); 1399 if (!dp->grf) 1400 return -ENODEV; 1401 } 1402 1403 ret = reset_get_bulk(dev, &dp->resets); 1404 if (ret) { 1405 dev_err(dev, "failed to get reset control: %d\n", ret); 1406 return ret; 1407 } 1408 1409 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1410 GPIOD_IS_IN); 1411 if (ret && ret != -ENOENT) { 1412 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1413 return ret; 1414 } 1415 1416 generic_phy_get_by_name(dev, "dp", &dp->phy); 1417 1418 dp->plat_data.dev_type = ROCKCHIP_DP; 1419 dp->plat_data.subdev_type = pdata->chip_type; 1420 dp->plat_data.ssc = pdata->ssc; 1421 dp->plat_data.max_bpc = pdata->max_bpc ? pdata->max_bpc : 8; 1422 1423 dp->video_info.max_link_rate = pdata->max_link_rate; 1424 dp->video_info.max_lane_count = pdata->max_lane_count; 1425 1426 dp->dev = dev; 1427 1428 ret = analogix_dp_parse_dt(dp); 1429 if (ret) { 1430 dev_err(dev, "failed to parse DT: %d\n", ret); 1431 return ret; 1432 } 1433 1434 analogix_dp_ddc_init(dp); 1435 1436 rockchip_connector_bind(&dp->connector, dev, dp->id, &analogix_dp_connector_funcs, 1437 NULL, DRM_MODE_CONNECTOR_eDP); 1438 1439 return 0; 1440 } 1441 1442 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 1443 .lcdsel_grf_reg = 0x025c, 1444 .lcdsel_big = 0 | BIT(21), 1445 .lcdsel_lit = BIT(5) | BIT(21), 1446 .chip_type = RK3288_DP, 1447 1448 .max_link_rate = DP_LINK_BW_2_7, 1449 .max_lane_count = 4, 1450 }; 1451 1452 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 1453 .chip_type = RK3368_EDP, 1454 1455 .max_link_rate = DP_LINK_BW_2_7, 1456 .max_lane_count = 4, 1457 }; 1458 1459 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 1460 .lcdsel_grf_reg = 0x6250, 1461 .lcdsel_big = 0 | BIT(21), 1462 .lcdsel_lit = BIT(5) | BIT(21), 1463 .chip_type = RK3399_EDP, 1464 .ssc = true, 1465 1466 .max_link_rate = DP_LINK_BW_5_4, 1467 .max_lane_count = 4, 1468 }; 1469 1470 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 1471 .chip_type = RK3568_EDP, 1472 .ssc = true, 1473 1474 .max_link_rate = DP_LINK_BW_2_7, 1475 .max_lane_count = 4, 1476 }; 1477 1478 static const struct rockchip_dp_chip_data rk3576_edp_platform_data = { 1479 .chip_type = RK3576_EDP, 1480 .ssc = true, 1481 1482 .max_link_rate = DP_LINK_BW_5_4, 1483 .max_lane_count = 4, 1484 .format_yuv = true, 1485 .max_bpc = 10, 1486 }; 1487 1488 static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { 1489 .chip_type = RK3588_EDP, 1490 .ssc = true, 1491 1492 .max_link_rate = DP_LINK_BW_5_4, 1493 .max_lane_count = 4, 1494 .format_yuv = true, 1495 .max_bpc = 10, 1496 }; 1497 1498 static const struct udevice_id analogix_dp_ids[] = { 1499 { 1500 .compatible = "rockchip,rk3288-dp", 1501 .data = (ulong)&rk3288_edp_platform_data, 1502 }, { 1503 .compatible = "rockchip,rk3368-edp", 1504 .data = (ulong)&rk3368_edp_platform_data, 1505 }, { 1506 .compatible = "rockchip,rk3399-edp", 1507 .data = (ulong)&rk3399_edp_platform_data, 1508 }, { 1509 .compatible = "rockchip,rk3568-edp", 1510 .data = (ulong)&rk3568_edp_platform_data, 1511 }, { 1512 .compatible = "rockchip,rk3576-edp", 1513 .data = (ulong)&rk3576_edp_platform_data, 1514 }, { 1515 .compatible = "rockchip,rk3588-edp", 1516 .data = (ulong)&rk3588_edp_platform_data, 1517 }, 1518 {} 1519 }; 1520 1521 U_BOOT_DRIVER(analogix_dp) = { 1522 .name = "analogix_dp", 1523 .id = UCLASS_DISPLAY, 1524 .of_match = analogix_dp_ids, 1525 .probe = analogix_dp_probe, 1526 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1527 }; 1528