1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/bitfield.h> 17 #include <linux/list.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <asm/gpio.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "analogix_dp.h" 26 27 #define RK3588_GRF_VO1_CON0 0x0000 28 #define EDP_MODE BIT(0) 29 #define RK3588_GRF_VO1_CON1 0x0004 30 31 /** 32 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 33 * @lcdsel_grf_reg: grf register offset of lcdc select 34 * @lcdsel_big: reg value of selecting vop big for eDP 35 * @lcdsel_lit: reg value of selecting vop little for eDP 36 * @chip_type: specific chip type 37 * @ssc: check if SSC is supported by source 38 */ 39 struct rockchip_dp_chip_data { 40 u32 lcdsel_grf_reg; 41 u32 lcdsel_big; 42 u32 lcdsel_lit; 43 u32 chip_type; 44 bool ssc; 45 46 u32 max_link_rate; 47 u32 max_lane_count; 48 }; 49 50 static int 51 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 52 bool enable) 53 { 54 u8 data; 55 int ret; 56 57 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); 58 if (ret != 1) 59 return ret; 60 61 if (enable) 62 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 63 DP_LANE_COUNT_ENHANCED_FRAME_EN | 64 DPCD_LANE_COUNT_SET(data)); 65 else 66 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 67 DPCD_LANE_COUNT_SET(data)); 68 69 return ret < 0 ? ret : 0; 70 } 71 72 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp, 73 u8 *enhanced_mode_support) 74 { 75 u8 data; 76 int ret; 77 78 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 79 if (ret != 1) { 80 *enhanced_mode_support = 0; 81 return ret; 82 } 83 84 *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data); 85 86 return 0; 87 } 88 89 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 90 { 91 u8 data; 92 int ret; 93 94 ret = analogix_dp_is_enhanced_mode_available(dp, &data); 95 if (ret < 0) 96 return ret; 97 98 ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data); 99 if (ret < 0) 100 return ret; 101 102 if (!data) { 103 /* 104 * As the Table 3-4 in eDP v1.2 spec: 105 * DPCD 0000Dh: 106 * Bit 1 = FRAMING_CHANGE_CAPABLE 107 * A setting of 1 indicates that this is an eDP device that 108 * uses only Enhanced Framing, independently of the setting by 109 * the source of ENHANCED_FRAME_EN 110 * 111 * And as the Table 3-3 in eDP v1.4 spec: 112 * DPCD 0000Dh: 113 * Bit 1 = RESERVED for eDP 114 * New to eDP v1.4.(Read all 0s) 115 */ 116 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_CONFIGURATION_CAP, 117 &data); 118 if (ret < 0) 119 return ret; 120 121 data = !!(data & DP_FRAMING_CHANGE_CAP); 122 } 123 124 analogix_dp_enable_enhanced_mode(dp, data); 125 126 return 0; 127 } 128 129 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 130 { 131 int ret; 132 133 analogix_dp_set_training_pattern(dp, DP_NONE); 134 135 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 136 DP_TRAINING_PATTERN_DISABLE); 137 138 return ret < 0 ? ret : 0; 139 } 140 141 static int analogix_dp_link_start(struct analogix_dp_device *dp) 142 { 143 u8 buf[4]; 144 int lane, lane_count, retval; 145 146 lane_count = dp->link_train.lane_count; 147 148 dp->link_train.lt_state = CLOCK_RECOVERY; 149 dp->link_train.eq_loop = 0; 150 151 for (lane = 0; lane < lane_count; lane++) 152 dp->link_train.cr_loop[lane] = 0; 153 154 /* Set link rate and count as you want to establish */ 155 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 156 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 157 158 if (dp->nr_link_rate_table) { 159 /* Setup DP_LINK_RATE_SET for eDP 1.4 and later */ 160 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, dp->link_train.lane_count); 161 drm_dp_dpcd_writeb(&dp->aux, DP_LINK_RATE_SET, dp->link_rate_select); 162 } else { 163 /* Setup DP_LINK_BW_SET for eDP 1.3 and earlier */ 164 buf[0] = dp->link_train.link_rate; 165 buf[1] = dp->link_train.lane_count; 166 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2); 167 if (retval < 0) 168 return retval; 169 } 170 171 /* Spread AMP if required, enable 8b/10b coding */ 172 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 173 buf[1] = DP_SET_ANSI_8B10B; 174 retval = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 2); 175 if (retval < 0) 176 return retval; 177 178 /* set enhanced mode if available */ 179 retval = analogix_dp_set_enhanced_mode(dp); 180 if (retval < 0) { 181 dev_err(dp->dev, "failed to set enhance mode\n"); 182 return retval; 183 } 184 185 /* Set TX voltage-swing and pre-emphasis to minimum */ 186 for (lane = 0; lane < lane_count; lane++) 187 dp->link_train.training_lane[lane] = 188 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 189 DP_TRAIN_PRE_EMPH_LEVEL_0; 190 analogix_dp_set_lane_link_training(dp); 191 192 /* Set training pattern 1 */ 193 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 194 195 /* Set RX training pattern */ 196 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 197 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 198 if (retval < 0) 199 return retval; 200 201 for (lane = 0; lane < lane_count; lane++) 202 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 203 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 204 205 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, 206 lane_count); 207 if (retval < 0) 208 return retval; 209 210 return 0; 211 } 212 213 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 214 { 215 int shift = (lane & 1) * 4; 216 u8 link_value = link_status[lane >> 1]; 217 218 return (link_value >> shift) & 0xf; 219 } 220 221 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 222 { 223 int lane; 224 u8 lane_status; 225 226 for (lane = 0; lane < lane_count; lane++) { 227 lane_status = analogix_dp_get_lane_status(link_status, lane); 228 if ((lane_status & DP_LANE_CR_DONE) == 0) 229 return -EINVAL; 230 } 231 return 0; 232 } 233 234 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 235 int lane_count) 236 { 237 int lane; 238 u8 lane_status; 239 240 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 241 return -EINVAL; 242 243 for (lane = 0; lane < lane_count; lane++) { 244 lane_status = analogix_dp_get_lane_status(link_status, lane); 245 lane_status &= DP_CHANNEL_EQ_BITS; 246 if (lane_status != DP_CHANNEL_EQ_BITS) 247 return -EINVAL; 248 } 249 250 return 0; 251 } 252 253 static unsigned char 254 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 255 { 256 int shift = (lane & 1) * 4; 257 u8 link_value = adjust_request[lane >> 1]; 258 259 return (link_value >> shift) & 0x3; 260 } 261 262 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 263 u8 adjust_request[2], 264 int lane) 265 { 266 int shift = (lane & 1) * 4; 267 u8 link_value = adjust_request[lane >> 1]; 268 269 return ((link_value >> shift) & 0xc) >> 2; 270 } 271 272 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 273 { 274 analogix_dp_training_pattern_dis(dp); 275 analogix_dp_set_enhanced_mode(dp); 276 277 dp->link_train.lt_state = FAILED; 278 } 279 280 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 281 u8 adjust_request[2]) 282 { 283 int lane, lane_count; 284 u8 voltage_swing, pre_emphasis, training_lane; 285 286 lane_count = dp->link_train.lane_count; 287 for (lane = 0; lane < lane_count; lane++) { 288 voltage_swing = analogix_dp_get_adjust_request_voltage( 289 adjust_request, lane); 290 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 291 adjust_request, lane); 292 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 293 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 294 295 if (voltage_swing == VOLTAGE_LEVEL_3) 296 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 297 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 298 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 299 300 dp->link_train.training_lane[lane] = training_lane; 301 } 302 } 303 304 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp) 305 { 306 bool source_tps3_supported, sink_tps3_supported; 307 u8 dpcd = 0; 308 309 source_tps3_supported = 310 dp->video_info.max_link_rate == DP_LINK_BW_5_4; 311 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &dpcd); 312 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; 313 314 return source_tps3_supported && sink_tps3_supported; 315 } 316 317 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 318 { 319 int lane, lane_count, retval; 320 u8 voltage_swing, pre_emphasis, training_lane; 321 u8 link_status[2], adjust_request[2]; 322 u8 training_pattern = TRAINING_PTN2; 323 324 drm_dp_link_train_clock_recovery_delay(dp->dpcd); 325 326 lane_count = dp->link_train.lane_count; 327 328 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 329 if (retval < 0) 330 return retval; 331 332 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 333 if (analogix_dp_tps3_supported(dp)) 334 training_pattern = TRAINING_PTN3; 335 336 /* set training pattern for EQ */ 337 analogix_dp_set_training_pattern(dp, training_pattern); 338 339 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 340 DP_LINK_SCRAMBLING_DISABLE | 341 (training_pattern == TRAINING_PTN3 ? 342 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); 343 if (retval < 0) 344 return retval; 345 346 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 347 dp->link_train.lt_state = EQUALIZER_TRAINING; 348 349 return 0; 350 } else { 351 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 352 adjust_request, 2); 353 if (retval < 0) 354 return retval; 355 356 for (lane = 0; lane < lane_count; lane++) { 357 training_lane = analogix_dp_get_lane_link_training( 358 dp, lane); 359 voltage_swing = analogix_dp_get_adjust_request_voltage( 360 adjust_request, lane); 361 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 362 adjust_request, lane); 363 364 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 365 voltage_swing && 366 DPCD_PRE_EMPHASIS_GET(training_lane) == 367 pre_emphasis) 368 dp->link_train.cr_loop[lane]++; 369 370 /* 371 * In DP spec 1.3, Condition of CR fail are 372 * outlined in section 3.5.1.2.2.1, figure 3-20: 373 * 374 * 1. Maximum Voltage Swing reached 375 * 2. Same Voltage five times 376 */ 377 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 378 DPCD_VOLTAGE_SWING_GET(training_lane) == VOLTAGE_LEVEL_3) { 379 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 380 dp->link_train.cr_loop[lane], 381 voltage_swing, pre_emphasis); 382 analogix_dp_reduce_link_rate(dp); 383 return -EIO; 384 } 385 } 386 } 387 388 analogix_dp_get_adjust_training_lane(dp, adjust_request); 389 analogix_dp_set_lane_link_training(dp); 390 391 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 392 dp->link_train.training_lane, lane_count); 393 if (retval < 0) 394 return retval; 395 396 return 0; 397 } 398 399 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 400 { 401 int lane_count, retval; 402 u32 reg; 403 u8 link_align, link_status[2], adjust_request[2]; 404 405 drm_dp_link_train_channel_eq_delay(dp->dpcd); 406 407 lane_count = dp->link_train.lane_count; 408 409 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 410 if (retval < 0) 411 return retval; 412 413 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 414 analogix_dp_reduce_link_rate(dp); 415 return -EIO; 416 } 417 418 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 419 if (retval < 0) 420 return retval; 421 422 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 423 /* traing pattern Set to Normal */ 424 retval = analogix_dp_training_pattern_dis(dp); 425 if (retval < 0) 426 return retval; 427 428 printf("Link Training success!\n"); 429 430 analogix_dp_get_link_bandwidth(dp, ®); 431 dp->link_train.link_rate = reg; 432 analogix_dp_get_lane_count(dp, ®); 433 dp->link_train.lane_count = reg; 434 435 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 436 dp->link_train.link_rate, dp->link_train.lane_count); 437 438 dp->link_train.lt_state = FINISHED; 439 440 return 0; 441 } 442 443 /* not all locked */ 444 dp->link_train.eq_loop++; 445 446 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 447 dev_dbg(dp->dev, "EQ Max loop\n"); 448 analogix_dp_reduce_link_rate(dp); 449 return -EIO; 450 } 451 452 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, adjust_request, 2); 453 if (retval < 0) 454 return retval; 455 456 analogix_dp_get_adjust_training_lane(dp, adjust_request); 457 analogix_dp_set_lane_link_training(dp); 458 459 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 460 dp->link_train.training_lane, lane_count); 461 if (retval < 0) 462 return retval; 463 464 return 0; 465 } 466 467 static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp, 468 const struct drm_display_mode *mode, 469 unsigned int rate, unsigned int lanes) 470 { 471 u32 max_bw, req_bw; 472 u32 bpp = 3 * dp->video_info.bpc; 473 474 req_bw = mode->clock * bpp / 8; 475 max_bw = lanes * rate; 476 if (req_bw > max_bw) 477 return false; 478 479 return true; 480 } 481 482 static bool analogix_dp_link_config_validate(u8 link_rate, u8 lane_count) 483 { 484 switch (link_rate) { 485 case DP_LINK_BW_1_62: 486 case DP_LINK_BW_2_7: 487 case DP_LINK_BW_5_4: 488 /* Supported link rate in eDP 1.4 */ 489 case EDP_LINK_BW_2_16: 490 case EDP_LINK_BW_2_43: 491 case EDP_LINK_BW_3_24: 492 case EDP_LINK_BW_4_32: 493 break; 494 default: 495 return false; 496 } 497 498 switch (lane_count) { 499 case LANE_COUNT1: 500 case LANE_COUNT2: 501 case LANE_COUNT4: 502 break; 503 default: 504 return false; 505 } 506 507 return true; 508 } 509 510 static int analogix_dp_select_link_rate_from_table(struct analogix_dp_device *dp) 511 { 512 int i; 513 u8 bw_code; 514 u32 max_link_rate = drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate); 515 516 for (i = 0; i < dp->nr_link_rate_table; i++) { 517 bw_code = drm_dp_link_rate_to_bw_code(dp->link_rate_table[i]); 518 519 if (!analogix_dp_bandwidth_ok(dp, &dp->video_info.mode, dp->link_rate_table[i], 520 dp->link_train.lane_count)) 521 continue; 522 523 if (dp->link_rate_table[i] <= max_link_rate && 524 analogix_dp_link_config_validate(bw_code, dp->link_train.lane_count)) { 525 dp->link_rate_select = i; 526 return bw_code; 527 } 528 } 529 530 return 0; 531 } 532 533 static int analogix_dp_select_rx_bandwidth(struct analogix_dp_device *dp) 534 { 535 if (dp->nr_link_rate_table) 536 /* 537 * Select the smallest one among link rates which meet 538 * the bandwidth requirement for eDP 1.4 and later. 539 */ 540 dp->link_train.link_rate = analogix_dp_select_link_rate_from_table(dp); 541 else 542 /* 543 * Select the smaller one between rx DP_MAX_LINK_RATE 544 * and the max link rate supported by the platform. 545 */ 546 dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate, 547 dp->video_info.max_link_rate); 548 if (!dp->link_train.link_rate) 549 return -EINVAL; 550 551 return 0; 552 } 553 554 static int analogix_dp_init_link_rate_table(struct analogix_dp_device *dp) 555 { 556 u8 link_rate_table[DP_MAX_SUPPORTED_RATES * 2]; 557 int i; 558 int ret; 559 560 ret = drm_dp_dpcd_read(&dp->aux, DP_SUPPORTED_LINK_RATES, link_rate_table, 561 sizeof(link_rate_table)); 562 if (ret < 0) 563 return ret; 564 565 for (i = 0; i < ARRAY_SIZE(link_rate_table) / 2; i++) { 566 int val = link_rate_table[2 * i] | link_rate_table[2 * i + 1] << 8; 567 568 if (val == 0) 569 break; 570 571 /* Convert to the link_rate as drm_dp_bw_code_to_link_rate() */ 572 dp->link_rate_table[i] = (val * 20); 573 } 574 dp->nr_link_rate_table = i; 575 576 return 0; 577 } 578 579 static int analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 580 u8 *bandwidth) 581 { 582 u8 data; 583 int ret; 584 585 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_DPCD_REV, &data); 586 if (ret == 1 && data >= DP_EDP_14) { 587 u32 max_link_rate; 588 589 /* As the Table 4-23 in eDP 1.4 spec, the link rate table is required */ 590 if (!dp->nr_link_rate_table) { 591 dev_info(dp->dev, "eDP version: 0x%02x supports link rate table\n", 592 data); 593 594 if (analogix_dp_init_link_rate_table(dp)) 595 dev_err(dp->dev, "failed to read link rate table: %d\n", 596 ret); 597 } 598 max_link_rate = dp->link_rate_table[dp->nr_link_rate_table - 1]; 599 *bandwidth = drm_dp_link_rate_to_bw_code(max_link_rate); 600 } else { 601 /* 602 * For DP rev.1.1, Maximum link rate of Main Link lanes 603 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 604 * For DP rev.1.2, Maximum link rate of Main Link lanes 605 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 606 */ 607 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data); 608 if (ret < 0) 609 return ret; 610 611 *bandwidth = data; 612 } 613 614 return 0; 615 } 616 617 static int analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 618 u8 *lane_count) 619 { 620 u8 data; 621 int ret; 622 623 /* 624 * For DP rev.1.1, Maximum number of Main Link lanes 625 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 626 */ 627 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 628 if (ret < 0) 629 return ret; 630 631 *lane_count = DPCD_MAX_LANE_COUNT(data); 632 633 return 0; 634 } 635 636 static int analogix_dp_init_training(struct analogix_dp_device *dp, 637 enum link_lane_count_type max_lane, 638 int max_rate) 639 { 640 u8 dpcd; 641 642 /* 643 * MACRO_RST must be applied after the PLL_LOCK to avoid 644 * the DP inter pair skew issue for at least 10 us 645 */ 646 analogix_dp_reset_macro(dp); 647 648 /* Initialize by reading RX's DPCD */ 649 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 650 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 651 652 /* Setup TX lane count */ 653 dp->link_train.lane_count = min_t(u32, dp->link_train.lane_count, max_lane); 654 655 /* Setup TX lane rate */ 656 if (analogix_dp_select_rx_bandwidth(dp)) { 657 dev_err(dp->dev, "Select rx bandwidth failed\n"); 658 return -EINVAL; 659 } 660 661 drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &dpcd); 662 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 663 664 /* All DP analog module power up */ 665 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 666 667 return 0; 668 } 669 670 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 671 { 672 int retval = 0, training_finished = 0; 673 674 dp->link_train.lt_state = START; 675 676 /* Process here */ 677 while (!retval && !training_finished) { 678 switch (dp->link_train.lt_state) { 679 case START: 680 retval = analogix_dp_link_start(dp); 681 if (retval) 682 dev_err(dp->dev, "LT link start failed!\n"); 683 break; 684 case CLOCK_RECOVERY: 685 retval = analogix_dp_process_clock_recovery(dp); 686 if (retval) 687 dev_err(dp->dev, "LT CR failed!\n"); 688 break; 689 case EQUALIZER_TRAINING: 690 retval = analogix_dp_process_equalizer_training(dp); 691 if (retval) 692 dev_err(dp->dev, "LT EQ failed!\n"); 693 break; 694 case FINISHED: 695 training_finished = 1; 696 break; 697 case FAILED: 698 return -EREMOTEIO; 699 } 700 } 701 702 return retval; 703 } 704 705 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 706 u32 count, u32 bwtype) 707 { 708 int i, ret; 709 710 for (i = 0; i < 5; i++) { 711 ret = analogix_dp_init_training(dp, count, bwtype); 712 if (ret < 0) { 713 dev_err(dp->dev, "failed to init training\n"); 714 return ret; 715 } 716 717 ret = analogix_dp_sw_link_training(dp); 718 if (!ret) 719 break; 720 } 721 722 return ret; 723 } 724 725 static int analogix_dp_config_video(struct analogix_dp_device *dp) 726 { 727 int timeout_loop = 0; 728 int done_count = 0; 729 730 analogix_dp_config_video_slave_mode(dp); 731 732 analogix_dp_set_video_color_format(dp); 733 734 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 735 dev_err(dp->dev, "PLL is not locked yet.\n"); 736 return -EINVAL; 737 } 738 739 for (;;) { 740 timeout_loop++; 741 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 742 break; 743 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 744 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 745 return -ETIMEDOUT; 746 } 747 748 udelay(2); 749 } 750 751 /* Set to use the register calculated M/N video */ 752 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 753 754 /* For video bist, Video timing must be generated by register */ 755 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_REGISTER); 756 757 /* Disable video mute */ 758 analogix_dp_enable_video_mute(dp, 0); 759 760 /* Configure video slave mode */ 761 analogix_dp_enable_video_master(dp, 0); 762 763 /* Enable video input */ 764 analogix_dp_start_video(dp); 765 766 timeout_loop = 0; 767 768 for (;;) { 769 timeout_loop++; 770 if (analogix_dp_is_video_stream_on(dp) == 0) { 771 done_count++; 772 if (done_count > 10) 773 break; 774 } else if (done_count) { 775 done_count = 0; 776 } 777 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 778 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 779 return -ETIMEDOUT; 780 } 781 782 udelay(1001); 783 } 784 785 return 0; 786 } 787 788 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp, 789 bool enable) 790 { 791 u8 data; 792 int ret; 793 794 if (enable) { 795 analogix_dp_enable_scrambling(dp); 796 797 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, 798 &data); 799 if (ret != 1) 800 return ret; 801 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 802 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 803 } else { 804 analogix_dp_disable_scrambling(dp); 805 806 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, 807 &data); 808 if (ret != 1) 809 return ret; 810 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 811 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 812 } 813 return ret < 0 ? ret : 0; 814 } 815 816 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 817 { 818 analogix_dp_reset(dp); 819 820 analogix_dp_swreset(dp); 821 822 analogix_dp_init_analog_param(dp); 823 analogix_dp_init_interrupt(dp); 824 825 /* SW defined function Normal operation */ 826 analogix_dp_enable_sw_function(dp); 827 828 analogix_dp_config_interrupt(dp); 829 analogix_dp_init_analog_func(dp); 830 831 analogix_dp_init_hpd(dp); 832 analogix_dp_init_aux(dp); 833 } 834 835 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 836 { 837 int i; 838 unsigned char sum = 0; 839 840 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 841 sum = sum + edid_data[i]; 842 843 return sum; 844 } 845 846 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 847 { 848 unsigned char *edid = dp->edid; 849 unsigned int extend_block = 0; 850 unsigned char test_vector; 851 int retval; 852 853 /* 854 * EDID device address is 0x50. 855 * However, if necessary, you must have set upper address 856 * into E-EDID in I2C device, 0x30. 857 */ 858 859 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 860 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 861 EDID_EXTENSION_FLAG, 862 &extend_block); 863 if (retval) 864 return retval; 865 866 if (extend_block > 0) { 867 debug("EDID data includes a single extension!\n"); 868 869 /* Read EDID data */ 870 retval = analogix_dp_read_bytes_from_i2c(dp, 871 I2C_EDID_DEVICE_ADDR, 872 EDID_HEADER_PATTERN, 873 EDID_BLOCK_LENGTH, 874 &edid[EDID_HEADER_PATTERN]); 875 if (retval < 0) 876 return retval; 877 878 if (analogix_dp_calc_edid_check_sum(edid)) 879 return -EINVAL; 880 881 /* Read additional EDID data */ 882 retval = analogix_dp_read_bytes_from_i2c(dp, 883 I2C_EDID_DEVICE_ADDR, 884 EDID_BLOCK_LENGTH, 885 EDID_BLOCK_LENGTH, 886 &edid[EDID_BLOCK_LENGTH]); 887 if (retval < 0) 888 return retval; 889 890 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 891 return -EINVAL; 892 893 drm_dp_dpcd_readb(&dp->aux, DP_TEST_REQUEST, &test_vector); 894 if (test_vector & DP_TEST_LINK_EDID_READ) { 895 drm_dp_dpcd_writeb(&dp->aux, DP_TEST_EDID_CHECKSUM, 896 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 897 drm_dp_dpcd_writeb(&dp->aux, DP_TEST_RESPONSE, 898 DP_TEST_EDID_CHECKSUM_WRITE); 899 } 900 } else { 901 dev_info(dp->dev, 902 "EDID data does not include any extensions.\n"); 903 904 /* Read EDID data */ 905 retval = analogix_dp_read_bytes_from_i2c(dp, 906 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 907 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 908 if (retval < 0) 909 return retval; 910 911 if (analogix_dp_calc_edid_check_sum(edid)) 912 return -EINVAL; 913 914 drm_dp_dpcd_readb(&dp->aux, DP_TEST_REQUEST, &test_vector); 915 if (test_vector & DP_TEST_LINK_EDID_READ) { 916 drm_dp_dpcd_writeb(&dp->aux, DP_TEST_EDID_CHECKSUM, 917 edid[EDID_CHECKSUM]); 918 drm_dp_dpcd_writeb(&dp->aux, DP_TEST_RESPONSE, 919 DP_TEST_EDID_CHECKSUM_WRITE); 920 } 921 } 922 923 return 0; 924 } 925 926 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 927 { 928 u8 buf[12]; 929 int i, try = 5; 930 int retval; 931 932 retry: 933 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 934 retval = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, buf, 12); 935 if (retval < 0 && try--) { 936 mdelay(10); 937 goto retry; 938 } 939 940 if (retval) 941 return retval; 942 943 /* Read EDID */ 944 for (i = 0; i < 3; i++) { 945 retval = analogix_dp_read_edid(dp); 946 if (!retval) 947 break; 948 } 949 950 return retval; 951 } 952 953 static int analogix_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 954 { 955 struct connector_state *conn_state = &state->conn_state; 956 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 957 958 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; 959 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 960 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 961 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 962 963 reset_assert_bulk(&dp->resets); 964 udelay(1); 965 reset_deassert_bulk(&dp->resets); 966 967 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 968 generic_phy_set_mode(&dp->phy, PHY_MODE_DP); 969 generic_phy_power_on(&dp->phy); 970 analogix_dp_init_dp(dp); 971 972 return 0; 973 } 974 975 static int analogix_dp_connector_get_edid(struct rockchip_connector *conn, 976 struct display_state *state) 977 { 978 struct connector_state *conn_state = &state->conn_state; 979 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 980 int ret; 981 982 ret = analogix_dp_handle_edid(dp); 983 if (ret) { 984 dev_err(dp->dev, "failed to get edid\n"); 985 return ret; 986 } 987 988 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 989 990 return 0; 991 } 992 993 static int analogix_dp_link_power_up(struct analogix_dp_device *dp) 994 { 995 u8 value; 996 int ret; 997 998 if (dp->dpcd[DP_DPCD_REV] < 0x11) 999 return 0; 1000 1001 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 1002 if (ret < 0) 1003 return ret; 1004 1005 value &= ~DP_SET_POWER_MASK; 1006 value |= DP_SET_POWER_D0; 1007 1008 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 1009 if (ret < 0) 1010 return ret; 1011 1012 mdelay(1); 1013 1014 return 0; 1015 } 1016 1017 static int analogix_dp_link_power_down(struct analogix_dp_device *dp) 1018 { 1019 u8 value; 1020 int ret; 1021 1022 if (dp->dpcd[DP_DPCD_REV] < 0x11) 1023 return 0; 1024 1025 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 1026 if (ret < 0) 1027 return ret; 1028 1029 value &= ~DP_SET_POWER_MASK; 1030 value |= DP_SET_POWER_D3; 1031 1032 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 1033 if (ret < 0) 1034 return ret; 1035 1036 return 0; 1037 } 1038 1039 static int analogix_dp_connector_enable(struct rockchip_connector *conn, 1040 struct display_state *state) 1041 { 1042 struct connector_state *conn_state = &state->conn_state; 1043 struct crtc_state *crtc_state = &state->crtc_state; 1044 const struct rockchip_dp_chip_data *pdata = 1045 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1046 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1047 struct video_info *video = &dp->video_info; 1048 struct drm_display_mode mode; 1049 u32 val; 1050 int ret; 1051 1052 drm_mode_copy(&video->mode, &conn_state->mode); 1053 1054 if (pdata->lcdsel_grf_reg) { 1055 if (crtc_state->crtc_id) 1056 val = pdata->lcdsel_lit; 1057 else 1058 val = pdata->lcdsel_big; 1059 1060 regmap_write(dp->grf, pdata->lcdsel_grf_reg, val); 1061 } 1062 1063 if (pdata->chip_type == RK3588_EDP) 1064 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 1065 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); 1066 1067 video->bpc = conn_state->bpc; 1068 switch (video->bpc) { 1069 case 12: 1070 video->color_depth = COLOR_12; 1071 break; 1072 case 10: 1073 video->color_depth = COLOR_10; 1074 break; 1075 case 6: 1076 video->color_depth = COLOR_6; 1077 break; 1078 case 8: 1079 default: 1080 video->color_depth = COLOR_8; 1081 break; 1082 } 1083 1084 ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd, DP_RECEIVER_CAP_SIZE); 1085 if (ret < 0) { 1086 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret); 1087 return ret; 1088 } 1089 1090 ret = analogix_dp_link_power_up(dp); 1091 if (ret) { 1092 dev_err(dp->dev, "failed to power up link: %d\n", ret); 1093 return ret; 1094 } 1095 1096 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 1097 dp->video_info.max_link_rate); 1098 if (ret) { 1099 dev_err(dp->dev, "unable to do link train\n"); 1100 return ret; 1101 } 1102 1103 ret = analogix_dp_enable_scramble(dp, 1); 1104 if (ret < 0) { 1105 dev_err(dp->dev, "can not enable scramble\n"); 1106 return ret; 1107 } 1108 1109 analogix_dp_init_video(dp); 1110 1111 drm_mode_copy(&mode, &conn_state->mode); 1112 if (conn->dual_channel_mode) 1113 drm_mode_convert_to_origin_mode(&mode); 1114 analogix_dp_set_video_format(dp, &mode); 1115 1116 if (dp->video_bist_enable) 1117 analogix_dp_video_bist_enable(dp); 1118 1119 ret = analogix_dp_config_video(dp); 1120 if (ret) { 1121 dev_err(dp->dev, "unable to config video\n"); 1122 return ret; 1123 } 1124 1125 return 0; 1126 } 1127 1128 static int analogix_dp_connector_disable(struct rockchip_connector *conn, 1129 struct display_state *state) 1130 { 1131 const struct rockchip_dp_chip_data *pdata = 1132 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1133 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1134 1135 if (!analogix_dp_get_plug_in_status(dp)) 1136 analogix_dp_link_power_down(dp); 1137 1138 if (pdata->chip_type == RK3588_EDP) 1139 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 1140 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 0)); 1141 1142 return 0; 1143 } 1144 1145 static int analogix_dp_connector_detect(struct rockchip_connector *conn, 1146 struct display_state *state) 1147 { 1148 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1149 1150 return analogix_dp_detect(dp); 1151 } 1152 1153 static int analogix_dp_connector_mode_valid(struct rockchip_connector *conn, 1154 struct display_state *state) 1155 { 1156 struct connector_state *conn_state = &state->conn_state; 1157 struct videomode vm; 1158 1159 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1160 1161 if (!vm.hfront_porch || !vm.hback_porch || !vm.vfront_porch || !vm.vback_porch) { 1162 dev_err(dp->dev, "front porch or back porch can not be 0\n"); 1163 return MODE_BAD; 1164 } 1165 1166 return MODE_OK; 1167 } 1168 1169 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 1170 .init = analogix_dp_connector_init, 1171 .get_edid = analogix_dp_connector_get_edid, 1172 .enable = analogix_dp_connector_enable, 1173 .disable = analogix_dp_connector_disable, 1174 .detect = analogix_dp_connector_detect, 1175 .mode_valid = analogix_dp_connector_mode_valid, 1176 }; 1177 1178 static u32 analogix_dp_parse_link_frequencies(struct analogix_dp_device *dp) 1179 { 1180 struct udevice *dev = dp->dev; 1181 const struct device_node *endpoint; 1182 u64 frequency = 0; 1183 1184 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 1185 if (!endpoint) 1186 return 0; 1187 1188 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 1189 return 0; 1190 1191 if (!frequency) 1192 return 0; 1193 1194 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 1195 1196 switch (frequency) { 1197 case 162000: 1198 case 270000: 1199 case 540000: 1200 break; 1201 default: 1202 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 1203 return 0; 1204 } 1205 1206 return frequency; 1207 } 1208 1209 static int analogix_dp_parse_dt(struct analogix_dp_device *dp) 1210 { 1211 struct udevice *dev = dp->dev; 1212 int len; 1213 u32 num_lanes; 1214 u32 max_link_rate; 1215 int ret; 1216 1217 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1218 dp->video_bist_enable = dev_read_bool(dev, "analogix,video-bist-enable"); 1219 dp->video_info.force_stream_valid = 1220 dev_read_bool(dev, "analogix,force-stream-valid"); 1221 1222 max_link_rate = analogix_dp_parse_link_frequencies(dp); 1223 if (max_link_rate && max_link_rate < drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate)) 1224 dp->video_info.max_link_rate = drm_dp_link_rate_to_bw_code(max_link_rate); 1225 1226 if (dev_read_prop(dev, "data-lanes", &len)) { 1227 num_lanes = len / sizeof(u32); 1228 if (num_lanes < 1 || num_lanes > 4 || num_lanes == 3) { 1229 dev_err(dev, "bad number of data lanes\n"); 1230 return -EINVAL; 1231 } 1232 1233 ret = dev_read_u32_array(dev, "data-lanes", dp->lane_map, 1234 num_lanes); 1235 if (ret) 1236 return ret; 1237 1238 dp->video_info.max_lane_count = num_lanes; 1239 } else { 1240 dp->lane_map[0] = 0; 1241 dp->lane_map[1] = 1; 1242 dp->lane_map[2] = 2; 1243 dp->lane_map[3] = 3; 1244 } 1245 1246 return 0; 1247 } 1248 1249 static int analogix_dp_ddc_init(struct analogix_dp_device *dp) 1250 { 1251 dp->aux.name = "analogix-dp"; 1252 dp->aux.dev = dp->dev; 1253 dp->aux.transfer = analogix_dp_aux_transfer; 1254 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1255 1256 return 0; 1257 } 1258 1259 static int analogix_dp_probe(struct udevice *dev) 1260 { 1261 struct analogix_dp_device *dp = dev_get_priv(dev); 1262 const struct rockchip_dp_chip_data *pdata = 1263 (const struct rockchip_dp_chip_data *)dev_get_driver_data(dev); 1264 struct udevice *syscon; 1265 int ret; 1266 1267 dp->reg_base = dev_read_addr_ptr(dev); 1268 1269 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 1270 if (dp->id < 0) 1271 dp->id = 0; 1272 1273 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1274 &syscon); 1275 if (!ret) { 1276 dp->grf = syscon_get_regmap(syscon); 1277 if (!dp->grf) 1278 return -ENODEV; 1279 } 1280 1281 ret = reset_get_bulk(dev, &dp->resets); 1282 if (ret) { 1283 dev_err(dev, "failed to get reset control: %d\n", ret); 1284 return ret; 1285 } 1286 1287 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1288 GPIOD_IS_IN); 1289 if (ret && ret != -ENOENT) { 1290 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1291 return ret; 1292 } 1293 1294 generic_phy_get_by_name(dev, "dp", &dp->phy); 1295 1296 dp->plat_data.dev_type = ROCKCHIP_DP; 1297 dp->plat_data.subdev_type = pdata->chip_type; 1298 dp->plat_data.ssc = pdata->ssc; 1299 1300 dp->video_info.max_link_rate = pdata->max_link_rate; 1301 dp->video_info.max_lane_count = pdata->max_lane_count; 1302 1303 dp->dev = dev; 1304 1305 ret = analogix_dp_parse_dt(dp); 1306 if (ret) { 1307 dev_err(dev, "failed to parse DT: %d\n", ret); 1308 return ret; 1309 } 1310 1311 analogix_dp_ddc_init(dp); 1312 1313 rockchip_connector_bind(&dp->connector, dev, dp->id, &analogix_dp_connector_funcs, 1314 NULL, DRM_MODE_CONNECTOR_eDP); 1315 1316 return 0; 1317 } 1318 1319 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 1320 .lcdsel_grf_reg = 0x025c, 1321 .lcdsel_big = 0 | BIT(21), 1322 .lcdsel_lit = BIT(5) | BIT(21), 1323 .chip_type = RK3288_DP, 1324 1325 .max_link_rate = DP_LINK_BW_2_7, 1326 .max_lane_count = 4, 1327 }; 1328 1329 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 1330 .chip_type = RK3368_EDP, 1331 1332 .max_link_rate = DP_LINK_BW_2_7, 1333 .max_lane_count = 4, 1334 }; 1335 1336 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 1337 .lcdsel_grf_reg = 0x6250, 1338 .lcdsel_big = 0 | BIT(21), 1339 .lcdsel_lit = BIT(5) | BIT(21), 1340 .chip_type = RK3399_EDP, 1341 .ssc = true, 1342 1343 .max_link_rate = DP_LINK_BW_5_4, 1344 .max_lane_count = 4, 1345 }; 1346 1347 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 1348 .chip_type = RK3568_EDP, 1349 .ssc = true, 1350 1351 .max_link_rate = DP_LINK_BW_2_7, 1352 .max_lane_count = 4, 1353 }; 1354 1355 static const struct rockchip_dp_chip_data rk3576_edp_platform_data = { 1356 .chip_type = RK3576_EDP, 1357 .ssc = true, 1358 1359 .max_link_rate = DP_LINK_BW_5_4, 1360 .max_lane_count = 4, 1361 }; 1362 1363 static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { 1364 .chip_type = RK3588_EDP, 1365 .ssc = true, 1366 1367 .max_link_rate = DP_LINK_BW_5_4, 1368 .max_lane_count = 4, 1369 }; 1370 1371 static const struct udevice_id analogix_dp_ids[] = { 1372 { 1373 .compatible = "rockchip,rk3288-dp", 1374 .data = (ulong)&rk3288_edp_platform_data, 1375 }, { 1376 .compatible = "rockchip,rk3368-edp", 1377 .data = (ulong)&rk3368_edp_platform_data, 1378 }, { 1379 .compatible = "rockchip,rk3399-edp", 1380 .data = (ulong)&rk3399_edp_platform_data, 1381 }, { 1382 .compatible = "rockchip,rk3568-edp", 1383 .data = (ulong)&rk3568_edp_platform_data, 1384 }, { 1385 .compatible = "rockchip,rk3576-edp", 1386 .data = (ulong)&rk3576_edp_platform_data, 1387 }, { 1388 .compatible = "rockchip,rk3588-edp", 1389 .data = (ulong)&rk3588_edp_platform_data, 1390 }, 1391 {} 1392 }; 1393 1394 U_BOOT_DRIVER(analogix_dp) = { 1395 .name = "analogix_dp", 1396 .id = UCLASS_DISPLAY, 1397 .of_match = analogix_dp_ids, 1398 .probe = analogix_dp_probe, 1399 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1400 }; 1401