1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/bitfield.h> 17 #include <linux/list.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <asm/gpio.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "analogix_dp.h" 26 27 #define RK3588_GRF_VO1_CON0 0x0000 28 #define EDP_MODE BIT(0) 29 #define RK3588_GRF_VO1_CON1 0x0004 30 31 /** 32 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 33 * @lcdsel_grf_reg: grf register offset of lcdc select 34 * @lcdsel_big: reg value of selecting vop big for eDP 35 * @lcdsel_lit: reg value of selecting vop little for eDP 36 * @chip_type: specific chip type 37 * @ssc: check if SSC is supported by source 38 */ 39 struct rockchip_dp_chip_data { 40 u32 lcdsel_grf_reg; 41 u32 lcdsel_big; 42 u32 lcdsel_lit; 43 u32 chip_type; 44 bool ssc; 45 46 u32 max_link_rate; 47 u32 max_lane_count; 48 }; 49 50 static void 51 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 52 bool enable) 53 { 54 u8 data; 55 56 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 57 58 if (enable) 59 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 60 DP_LANE_COUNT_ENHANCED_FRAME_EN | 61 DPCD_LANE_COUNT_SET(data)); 62 else 63 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 64 DPCD_LANE_COUNT_SET(data)); 65 } 66 67 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 68 { 69 u8 data; 70 int retval; 71 72 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 73 retval = DPCD_ENHANCED_FRAME_CAP(data); 74 75 return retval; 76 } 77 78 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 79 { 80 u8 data; 81 82 data = analogix_dp_is_enhanced_mode_available(dp); 83 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 84 analogix_dp_enable_enhanced_mode(dp, data); 85 } 86 87 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 88 { 89 analogix_dp_set_training_pattern(dp, DP_NONE); 90 91 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 92 DP_TRAINING_PATTERN_DISABLE); 93 } 94 95 static int analogix_dp_link_start(struct analogix_dp_device *dp) 96 { 97 u8 buf[4]; 98 int lane, lane_count, retval; 99 100 lane_count = dp->link_train.lane_count; 101 102 dp->link_train.lt_state = CLOCK_RECOVERY; 103 dp->link_train.eq_loop = 0; 104 105 for (lane = 0; lane < lane_count; lane++) 106 dp->link_train.cr_loop[lane] = 0; 107 108 /* Set link rate and count as you want to establish*/ 109 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 110 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 111 112 /* Setup RX configuration */ 113 buf[0] = dp->link_train.link_rate; 114 buf[1] = dp->link_train.lane_count; 115 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 116 if (retval) 117 return retval; 118 119 /* Spread AMP if required, enable 8b/10b coding */ 120 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 121 buf[1] = DP_SET_ANSI_8B10B; 122 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_DOWNSPREAD_CTRL, 123 2, buf); 124 if (retval < 0) 125 return retval; 126 127 /* Set TX voltage-swing and pre-emphasis to minimum */ 128 for (lane = 0; lane < lane_count; lane++) 129 dp->link_train.training_lane[lane] = 130 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 131 DP_TRAIN_PRE_EMPH_LEVEL_0; 132 analogix_dp_set_lane_link_training(dp); 133 134 /* Set training pattern 1 */ 135 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 136 137 /* Set RX training pattern */ 138 retval = analogix_dp_write_byte_to_dpcd(dp, 139 DP_TRAINING_PATTERN_SET, 140 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 141 if (retval) 142 return retval; 143 144 for (lane = 0; lane < lane_count; lane++) 145 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 146 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 147 148 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 149 lane_count, buf); 150 151 return retval; 152 } 153 154 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 155 { 156 int shift = (lane & 1) * 4; 157 u8 link_value = link_status[lane >> 1]; 158 159 return (link_value >> shift) & 0xf; 160 } 161 162 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 163 { 164 int lane; 165 u8 lane_status; 166 167 for (lane = 0; lane < lane_count; lane++) { 168 lane_status = analogix_dp_get_lane_status(link_status, lane); 169 if ((lane_status & DP_LANE_CR_DONE) == 0) 170 return -EINVAL; 171 } 172 return 0; 173 } 174 175 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 176 int lane_count) 177 { 178 int lane; 179 u8 lane_status; 180 181 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 182 return -EINVAL; 183 184 for (lane = 0; lane < lane_count; lane++) { 185 lane_status = analogix_dp_get_lane_status(link_status, lane); 186 lane_status &= DP_CHANNEL_EQ_BITS; 187 if (lane_status != DP_CHANNEL_EQ_BITS) 188 return -EINVAL; 189 } 190 191 return 0; 192 } 193 194 static unsigned char 195 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 196 { 197 int shift = (lane & 1) * 4; 198 u8 link_value = adjust_request[lane >> 1]; 199 200 return (link_value >> shift) & 0x3; 201 } 202 203 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 204 u8 adjust_request[2], 205 int lane) 206 { 207 int shift = (lane & 1) * 4; 208 u8 link_value = adjust_request[lane >> 1]; 209 210 return ((link_value >> shift) & 0xc) >> 2; 211 } 212 213 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 214 { 215 analogix_dp_training_pattern_dis(dp); 216 analogix_dp_set_enhanced_mode(dp); 217 218 dp->link_train.lt_state = FAILED; 219 } 220 221 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 222 u8 adjust_request[2]) 223 { 224 int lane, lane_count; 225 u8 voltage_swing, pre_emphasis, training_lane; 226 227 lane_count = dp->link_train.lane_count; 228 for (lane = 0; lane < lane_count; lane++) { 229 voltage_swing = analogix_dp_get_adjust_request_voltage( 230 adjust_request, lane); 231 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 232 adjust_request, lane); 233 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 234 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 235 236 if (voltage_swing == VOLTAGE_LEVEL_3) 237 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 238 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 239 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 240 241 dp->link_train.training_lane[lane] = training_lane; 242 } 243 } 244 245 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp) 246 { 247 bool source_tps3_supported, sink_tps3_supported; 248 u8 dpcd = 0; 249 250 source_tps3_supported = 251 dp->video_info.max_link_rate == DP_LINK_BW_5_4; 252 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &dpcd); 253 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; 254 255 return source_tps3_supported && sink_tps3_supported; 256 } 257 258 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 259 { 260 int lane, lane_count, retval; 261 u8 voltage_swing, pre_emphasis, training_lane; 262 u8 link_status[2], adjust_request[2]; 263 u8 training_pattern = TRAINING_PTN2; 264 265 drm_dp_link_train_clock_recovery_delay(dp->dpcd); 266 267 lane_count = dp->link_train.lane_count; 268 269 retval = analogix_dp_read_bytes_from_dpcd(dp, 270 DP_LANE0_1_STATUS, 2, link_status); 271 if (retval) 272 return retval; 273 274 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 275 if (analogix_dp_tps3_supported(dp)) 276 training_pattern = TRAINING_PTN3; 277 278 /* set training pattern for EQ */ 279 analogix_dp_set_training_pattern(dp, training_pattern); 280 281 retval = analogix_dp_write_byte_to_dpcd(dp, 282 DP_TRAINING_PATTERN_SET, 283 (training_pattern == TRAINING_PTN3 ? 284 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); 285 if (retval) 286 return retval; 287 288 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 289 dp->link_train.lt_state = EQUALIZER_TRAINING; 290 291 return 0; 292 } else { 293 retval = analogix_dp_read_bytes_from_dpcd(dp, 294 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 295 if (retval) 296 return retval; 297 298 for (lane = 0; lane < lane_count; lane++) { 299 training_lane = analogix_dp_get_lane_link_training( 300 dp, lane); 301 voltage_swing = analogix_dp_get_adjust_request_voltage( 302 adjust_request, lane); 303 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 304 adjust_request, lane); 305 306 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 307 voltage_swing && 308 DPCD_PRE_EMPHASIS_GET(training_lane) == 309 pre_emphasis) 310 dp->link_train.cr_loop[lane]++; 311 312 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 313 voltage_swing == VOLTAGE_LEVEL_3 || 314 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 315 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 316 dp->link_train.cr_loop[lane], 317 voltage_swing, pre_emphasis); 318 analogix_dp_reduce_link_rate(dp); 319 return -EIO; 320 } 321 } 322 } 323 324 analogix_dp_get_adjust_training_lane(dp, adjust_request); 325 analogix_dp_set_lane_link_training(dp); 326 327 retval = analogix_dp_write_bytes_to_dpcd(dp, 328 DP_TRAINING_LANE0_SET, lane_count, 329 dp->link_train.training_lane); 330 if (retval) 331 return retval; 332 333 return retval; 334 } 335 336 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 337 { 338 int lane_count, retval; 339 u32 reg; 340 u8 link_align, link_status[2], adjust_request[2]; 341 342 drm_dp_link_train_channel_eq_delay(dp->dpcd); 343 344 lane_count = dp->link_train.lane_count; 345 346 retval = analogix_dp_read_bytes_from_dpcd(dp, 347 DP_LANE0_1_STATUS, 2, link_status); 348 if (retval) 349 return retval; 350 351 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 352 analogix_dp_reduce_link_rate(dp); 353 return -EIO; 354 } 355 356 retval = analogix_dp_read_byte_from_dpcd(dp, 357 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 358 if (retval) 359 return retval; 360 361 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 362 /* traing pattern Set to Normal */ 363 analogix_dp_training_pattern_dis(dp); 364 365 printf("Link Training success!\n"); 366 367 analogix_dp_get_link_bandwidth(dp, ®); 368 dp->link_train.link_rate = reg; 369 analogix_dp_get_lane_count(dp, ®); 370 dp->link_train.lane_count = reg; 371 372 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 373 dp->link_train.link_rate, dp->link_train.lane_count); 374 375 /* set enhanced mode if available */ 376 analogix_dp_set_enhanced_mode(dp); 377 dp->link_train.lt_state = FINISHED; 378 379 return 0; 380 } 381 382 /* not all locked */ 383 dp->link_train.eq_loop++; 384 385 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 386 dev_dbg(dp->dev, "EQ Max loop\n"); 387 analogix_dp_reduce_link_rate(dp); 388 return -EIO; 389 } 390 391 retval = analogix_dp_read_bytes_from_dpcd(dp, 392 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 393 if (retval) 394 return retval; 395 396 analogix_dp_get_adjust_training_lane(dp, adjust_request); 397 analogix_dp_set_lane_link_training(dp); 398 399 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 400 lane_count, dp->link_train.training_lane); 401 402 return retval; 403 } 404 405 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 406 u8 *bandwidth) 407 { 408 u8 data; 409 410 /* 411 * For DP rev.1.1, Maximum link rate of Main Link lanes 412 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 413 * For DP rev.1.2, Maximum link rate of Main Link lanes 414 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 415 */ 416 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 417 *bandwidth = data; 418 } 419 420 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 421 u8 *lane_count) 422 { 423 u8 data; 424 425 /* 426 * For DP rev.1.1, Maximum number of Main Link lanes 427 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 428 */ 429 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 430 *lane_count = DPCD_MAX_LANE_COUNT(data); 431 } 432 433 static int analogix_dp_init_training(struct analogix_dp_device *dp, 434 enum link_lane_count_type max_lane, 435 int max_rate) 436 { 437 u8 dpcd; 438 439 /* 440 * MACRO_RST must be applied after the PLL_LOCK to avoid 441 * the DP inter pair skew issue for at least 10 us 442 */ 443 analogix_dp_reset_macro(dp); 444 445 /* Initialize by reading RX's DPCD */ 446 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 447 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 448 449 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 450 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 451 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 452 dev_err(dp->dev, "failed to get Rx Max Link Rate\n"); 453 return -ENODEV; 454 } 455 456 if (dp->link_train.lane_count == 0) { 457 dev_err(dp->dev, "failed to get Rx Max Lane Count\n"); 458 return -ENODEV; 459 } 460 461 /* Setup TX lane count & rate */ 462 if (dp->link_train.lane_count > max_lane) 463 dp->link_train.lane_count = max_lane; 464 if (dp->link_train.link_rate > max_rate) 465 dp->link_train.link_rate = max_rate; 466 467 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_DOWNSPREAD, &dpcd); 468 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 469 470 /* All DP analog module power up */ 471 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 472 473 return 0; 474 } 475 476 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 477 { 478 int retval = 0, training_finished = 0; 479 480 dp->link_train.lt_state = START; 481 482 /* Process here */ 483 while (!retval && !training_finished) { 484 switch (dp->link_train.lt_state) { 485 case START: 486 retval = analogix_dp_link_start(dp); 487 if (retval) 488 dev_err(dp->dev, "LT link start failed!\n"); 489 break; 490 case CLOCK_RECOVERY: 491 retval = analogix_dp_process_clock_recovery(dp); 492 if (retval) 493 dev_err(dp->dev, "LT CR failed!\n"); 494 break; 495 case EQUALIZER_TRAINING: 496 retval = analogix_dp_process_equalizer_training(dp); 497 if (retval) 498 dev_err(dp->dev, "LT EQ failed!\n"); 499 break; 500 case FINISHED: 501 training_finished = 1; 502 break; 503 case FAILED: 504 return -EREMOTEIO; 505 } 506 } 507 508 return retval; 509 } 510 511 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 512 u32 count, u32 bwtype) 513 { 514 int i, ret; 515 516 for (i = 0; i < 5; i++) { 517 ret = analogix_dp_init_training(dp, count, bwtype); 518 if (ret < 0) { 519 dev_err(dp->dev, "failed to init training\n"); 520 return ret; 521 } 522 523 ret = analogix_dp_sw_link_training(dp); 524 if (!ret) 525 break; 526 } 527 528 return ret; 529 } 530 531 static int analogix_dp_config_video(struct analogix_dp_device *dp) 532 { 533 int timeout_loop = 0; 534 int done_count = 0; 535 536 analogix_dp_config_video_slave_mode(dp); 537 538 analogix_dp_set_video_color_format(dp); 539 540 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 541 dev_err(dp->dev, "PLL is not locked yet.\n"); 542 return -EINVAL; 543 } 544 545 for (;;) { 546 timeout_loop++; 547 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 548 break; 549 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 550 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 551 return -ETIMEDOUT; 552 } 553 554 udelay(2); 555 } 556 557 /* Set to use the register calculated M/N video */ 558 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 559 560 /* For video bist, Video timing must be generated by register */ 561 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 562 563 /* Disable video mute */ 564 analogix_dp_enable_video_mute(dp, 0); 565 566 /* Configure video slave mode */ 567 analogix_dp_enable_video_master(dp, 0); 568 569 /* Enable video input */ 570 analogix_dp_start_video(dp); 571 572 timeout_loop = 0; 573 574 for (;;) { 575 timeout_loop++; 576 if (analogix_dp_is_video_stream_on(dp) == 0) { 577 done_count++; 578 if (done_count > 10) 579 break; 580 } else if (done_count) { 581 done_count = 0; 582 } 583 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 584 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 585 return -ETIMEDOUT; 586 } 587 588 udelay(1001); 589 } 590 591 return 0; 592 } 593 594 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 595 bool enable) 596 { 597 u8 data; 598 599 if (enable) { 600 analogix_dp_enable_scrambling(dp); 601 602 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 603 &data); 604 analogix_dp_write_byte_to_dpcd(dp, 605 DP_TRAINING_PATTERN_SET, 606 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 607 } else { 608 analogix_dp_disable_scrambling(dp); 609 610 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 611 &data); 612 analogix_dp_write_byte_to_dpcd(dp, 613 DP_TRAINING_PATTERN_SET, 614 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 615 } 616 } 617 618 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 619 { 620 analogix_dp_reset(dp); 621 622 analogix_dp_swreset(dp); 623 624 analogix_dp_init_analog_param(dp); 625 analogix_dp_init_interrupt(dp); 626 627 /* SW defined function Normal operation */ 628 analogix_dp_enable_sw_function(dp); 629 630 analogix_dp_config_interrupt(dp); 631 analogix_dp_init_analog_func(dp); 632 633 analogix_dp_init_hpd(dp); 634 analogix_dp_init_aux(dp); 635 } 636 637 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 638 { 639 int i; 640 unsigned char sum = 0; 641 642 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 643 sum = sum + edid_data[i]; 644 645 return sum; 646 } 647 648 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 649 { 650 unsigned char *edid = dp->edid; 651 unsigned int extend_block = 0; 652 unsigned char test_vector; 653 int retval; 654 655 /* 656 * EDID device address is 0x50. 657 * However, if necessary, you must have set upper address 658 * into E-EDID in I2C device, 0x30. 659 */ 660 661 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 662 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 663 EDID_EXTENSION_FLAG, 664 &extend_block); 665 if (retval) 666 return retval; 667 668 if (extend_block > 0) { 669 debug("EDID data includes a single extension!\n"); 670 671 /* Read EDID data */ 672 retval = analogix_dp_read_bytes_from_i2c(dp, 673 I2C_EDID_DEVICE_ADDR, 674 EDID_HEADER_PATTERN, 675 EDID_BLOCK_LENGTH, 676 &edid[EDID_HEADER_PATTERN]); 677 if (retval < 0) 678 return retval; 679 680 if (analogix_dp_calc_edid_check_sum(edid)) 681 return -EINVAL; 682 683 /* Read additional EDID data */ 684 retval = analogix_dp_read_bytes_from_i2c(dp, 685 I2C_EDID_DEVICE_ADDR, 686 EDID_BLOCK_LENGTH, 687 EDID_BLOCK_LENGTH, 688 &edid[EDID_BLOCK_LENGTH]); 689 if (retval < 0) 690 return retval; 691 692 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 693 return -EINVAL; 694 695 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 696 &test_vector); 697 if (test_vector & DP_TEST_LINK_EDID_READ) { 698 analogix_dp_write_byte_to_dpcd(dp, 699 DP_TEST_EDID_CHECKSUM, 700 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 701 analogix_dp_write_byte_to_dpcd(dp, 702 DP_TEST_RESPONSE, 703 DP_TEST_EDID_CHECKSUM_WRITE); 704 } 705 } else { 706 dev_info(dp->dev, 707 "EDID data does not include any extensions.\n"); 708 709 /* Read EDID data */ 710 retval = analogix_dp_read_bytes_from_i2c(dp, 711 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 712 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 713 if (retval < 0) 714 return retval; 715 716 if (analogix_dp_calc_edid_check_sum(edid)) 717 return -EINVAL; 718 719 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 720 &test_vector); 721 if (test_vector & DP_TEST_LINK_EDID_READ) { 722 analogix_dp_write_byte_to_dpcd(dp, 723 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 724 analogix_dp_write_byte_to_dpcd(dp, 725 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 726 } 727 } 728 729 return 0; 730 } 731 732 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 733 { 734 u8 buf[12]; 735 int i, try = 5; 736 int retval; 737 738 retry: 739 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 740 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 741 742 if (retval && try--) { 743 mdelay(10); 744 goto retry; 745 } 746 747 if (retval) 748 return retval; 749 750 /* Read EDID */ 751 for (i = 0; i < 3; i++) { 752 retval = analogix_dp_read_edid(dp); 753 if (!retval) 754 break; 755 } 756 757 return retval; 758 } 759 760 static int analogix_dp_connector_pre_init(struct display_state *state) 761 { 762 struct connector_state *conn_state = &state->conn_state; 763 764 conn_state->type = DRM_MODE_CONNECTOR_eDP; 765 766 return 0; 767 } 768 769 static int analogix_dp_connector_init(struct display_state *state) 770 { 771 struct connector_state *conn_state = &state->conn_state; 772 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 773 774 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; 775 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 776 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 777 778 reset_assert_bulk(&dp->resets); 779 udelay(1); 780 reset_deassert_bulk(&dp->resets); 781 782 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 783 generic_phy_set_mode(&dp->phy, PHY_MODE_DP); 784 generic_phy_power_on(&dp->phy); 785 analogix_dp_init_dp(dp); 786 787 return 0; 788 } 789 790 static int analogix_dp_connector_get_edid(struct display_state *state) 791 { 792 struct connector_state *conn_state = &state->conn_state; 793 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 794 int ret; 795 796 ret = analogix_dp_handle_edid(dp); 797 if (ret) { 798 dev_err(dp->dev, "failed to get edid\n"); 799 return ret; 800 } 801 802 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 803 804 return 0; 805 } 806 807 static int analogix_dp_link_power_up(struct analogix_dp_device *dp) 808 { 809 u8 value; 810 int ret; 811 812 if (dp->dpcd[DP_DPCD_REV] < 0x11) 813 return 0; 814 815 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 816 if (ret < 0) 817 return ret; 818 819 value &= ~DP_SET_POWER_MASK; 820 value |= DP_SET_POWER_D0; 821 822 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 823 if (ret < 0) 824 return ret; 825 826 mdelay(1); 827 828 return 0; 829 } 830 831 static int analogix_dp_link_power_down(struct analogix_dp_device *dp) 832 { 833 u8 value; 834 int ret; 835 836 if (dp->dpcd[DP_DPCD_REV] < 0x11) 837 return 0; 838 839 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 840 if (ret < 0) 841 return ret; 842 843 value &= ~DP_SET_POWER_MASK; 844 value |= DP_SET_POWER_D3; 845 846 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 847 if (ret < 0) 848 return ret; 849 850 return 0; 851 } 852 853 static int analogix_dp_connector_enable(struct display_state *state) 854 { 855 struct connector_state *conn_state = &state->conn_state; 856 struct crtc_state *crtc_state = &state->crtc_state; 857 const struct rockchip_connector *connector = conn_state->connector; 858 const struct rockchip_dp_chip_data *pdata = connector->data; 859 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 860 struct video_info *video = &dp->video_info; 861 u32 val; 862 int ret; 863 864 if (pdata->lcdsel_grf_reg) { 865 if (crtc_state->crtc_id) 866 val = pdata->lcdsel_lit; 867 else 868 val = pdata->lcdsel_big; 869 870 regmap_write(dp->grf, pdata->lcdsel_grf_reg, val); 871 } 872 873 if (pdata->chip_type == RK3588_EDP) 874 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 875 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); 876 877 switch (conn_state->bpc) { 878 case 12: 879 video->color_depth = COLOR_12; 880 break; 881 case 10: 882 video->color_depth = COLOR_10; 883 break; 884 case 6: 885 video->color_depth = COLOR_6; 886 break; 887 case 8: 888 default: 889 video->color_depth = COLOR_8; 890 break; 891 } 892 893 ret = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 894 DP_RECEIVER_CAP_SIZE, dp->dpcd); 895 if (ret) { 896 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret); 897 return ret; 898 } 899 900 ret = analogix_dp_link_power_up(dp); 901 if (ret) { 902 dev_err(dp->dev, "failed to power up link: %d\n", ret); 903 return ret; 904 } 905 906 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 907 dp->video_info.max_link_rate); 908 if (ret) { 909 dev_err(dp->dev, "unable to do link train\n"); 910 return ret; 911 } 912 913 analogix_dp_enable_scramble(dp, 1); 914 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 915 analogix_dp_enable_enhanced_mode(dp, 1); 916 917 analogix_dp_init_video(dp); 918 ret = analogix_dp_config_video(dp); 919 if (ret) { 920 dev_err(dp->dev, "unable to config video\n"); 921 return ret; 922 } 923 924 return 0; 925 } 926 927 static int analogix_dp_connector_disable(struct display_state *state) 928 { 929 struct connector_state *conn_state = &state->conn_state; 930 const struct rockchip_connector *connector = conn_state->connector; 931 const struct rockchip_dp_chip_data *pdata = connector->data; 932 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 933 934 if (!analogix_dp_get_plug_in_status(dp)) 935 analogix_dp_link_power_down(dp); 936 937 if (pdata->chip_type == RK3588_EDP) 938 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 939 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 0)); 940 941 return 0; 942 } 943 944 static int analogix_dp_connector_detect(struct display_state *state) 945 { 946 struct connector_state *conn_state = &state->conn_state; 947 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 948 949 return analogix_dp_detect(dp); 950 } 951 952 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 953 .pre_init = analogix_dp_connector_pre_init, 954 .init = analogix_dp_connector_init, 955 .get_edid = analogix_dp_connector_get_edid, 956 .enable = analogix_dp_connector_enable, 957 .disable = analogix_dp_connector_disable, 958 .detect = analogix_dp_connector_detect, 959 }; 960 961 static int analogix_dp_probe(struct udevice *dev) 962 { 963 struct analogix_dp_device *dp = dev_get_priv(dev); 964 const struct rockchip_connector *connector = 965 (const struct rockchip_connector *)dev_get_driver_data(dev); 966 const struct rockchip_dp_chip_data *pdata = connector->data; 967 struct udevice *syscon; 968 int ret; 969 970 dp->reg_base = dev_read_addr_ptr(dev); 971 972 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 973 if (dp->id < 0) 974 dp->id = 0; 975 976 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 977 &syscon); 978 if (!ret) { 979 dp->grf = syscon_get_regmap(syscon); 980 if (!dp->grf) 981 return -ENODEV; 982 } 983 984 ret = reset_get_bulk(dev, &dp->resets); 985 if (ret) { 986 dev_err(dev, "failed to get reset control: %d\n", ret); 987 return ret; 988 } 989 990 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 991 GPIOD_IS_IN); 992 if (ret && ret != -ENOENT) { 993 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 994 return ret; 995 } 996 997 generic_phy_get_by_name(dev, "dp", &dp->phy); 998 999 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1000 1001 dp->plat_data.dev_type = ROCKCHIP_DP; 1002 dp->plat_data.subdev_type = pdata->chip_type; 1003 dp->plat_data.ssc = pdata->ssc; 1004 1005 dp->video_info.max_link_rate = pdata->max_link_rate; 1006 dp->video_info.max_lane_count = pdata->max_lane_count; 1007 1008 dp->dev = dev; 1009 1010 return 0; 1011 } 1012 1013 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 1014 .lcdsel_grf_reg = 0x025c, 1015 .lcdsel_big = 0 | BIT(21), 1016 .lcdsel_lit = BIT(5) | BIT(21), 1017 .chip_type = RK3288_DP, 1018 1019 .max_link_rate = DP_LINK_BW_2_7, 1020 .max_lane_count = 4, 1021 }; 1022 1023 static const struct rockchip_connector rk3288_edp_driver_data = { 1024 .funcs = &analogix_dp_connector_funcs, 1025 .data = &rk3288_edp_platform_data, 1026 }; 1027 1028 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 1029 .chip_type = RK3368_EDP, 1030 1031 .max_link_rate = DP_LINK_BW_2_7, 1032 .max_lane_count = 4, 1033 }; 1034 1035 static const struct rockchip_connector rk3368_edp_driver_data = { 1036 .funcs = &analogix_dp_connector_funcs, 1037 .data = &rk3368_edp_platform_data, 1038 }; 1039 1040 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 1041 .lcdsel_grf_reg = 0x6250, 1042 .lcdsel_big = 0 | BIT(21), 1043 .lcdsel_lit = BIT(5) | BIT(21), 1044 .chip_type = RK3399_EDP, 1045 1046 .max_link_rate = DP_LINK_BW_2_7, 1047 .max_lane_count = 4, 1048 }; 1049 1050 static const struct rockchip_connector rk3399_edp_driver_data = { 1051 .funcs = &analogix_dp_connector_funcs, 1052 .data = &rk3399_edp_platform_data, 1053 }; 1054 1055 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 1056 .chip_type = RK3568_EDP, 1057 .ssc = true, 1058 1059 .max_link_rate = DP_LINK_BW_2_7, 1060 .max_lane_count = 4, 1061 }; 1062 1063 static const struct rockchip_connector rk3568_edp_driver_data = { 1064 .funcs = &analogix_dp_connector_funcs, 1065 .data = &rk3568_edp_platform_data, 1066 }; 1067 1068 static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { 1069 .chip_type = RK3588_EDP, 1070 .ssc = true, 1071 1072 .max_link_rate = DP_LINK_BW_5_4, 1073 .max_lane_count = 4, 1074 }; 1075 1076 static const struct rockchip_connector rk3588_edp_driver_data = { 1077 .funcs = &analogix_dp_connector_funcs, 1078 .data = &rk3588_edp_platform_data, 1079 }; 1080 1081 static const struct udevice_id analogix_dp_ids[] = { 1082 { 1083 .compatible = "rockchip,rk3288-dp", 1084 .data = (ulong)&rk3288_edp_driver_data, 1085 }, { 1086 .compatible = "rockchip,rk3368-edp", 1087 .data = (ulong)&rk3368_edp_driver_data, 1088 }, { 1089 .compatible = "rockchip,rk3399-edp", 1090 .data = (ulong)&rk3399_edp_driver_data, 1091 }, { 1092 .compatible = "rockchip,rk3568-edp", 1093 .data = (ulong)&rk3568_edp_driver_data, 1094 }, { 1095 .compatible = "rockchip,rk3588-edp", 1096 .data = (ulong)&rk3588_edp_driver_data, 1097 }, 1098 {} 1099 }; 1100 1101 U_BOOT_DRIVER(analogix_dp) = { 1102 .name = "analogix_dp", 1103 .id = UCLASS_DISPLAY, 1104 .of_match = analogix_dp_ids, 1105 .probe = analogix_dp_probe, 1106 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1107 }; 1108