1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/bitfield.h> 17 #include <linux/list.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <asm/gpio.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "analogix_dp.h" 26 27 #define RK3588_GRF_VO1_CON0 0x0000 28 #define EDP_MODE BIT(0) 29 #define RK3588_GRF_VO1_CON1 0x0004 30 31 /** 32 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 33 * @lcdsel_grf_reg: grf register offset of lcdc select 34 * @lcdsel_big: reg value of selecting vop big for eDP 35 * @lcdsel_lit: reg value of selecting vop little for eDP 36 * @chip_type: specific chip type 37 * @ssc: check if SSC is supported by source 38 */ 39 struct rockchip_dp_chip_data { 40 u32 lcdsel_grf_reg; 41 u32 lcdsel_big; 42 u32 lcdsel_lit; 43 u32 chip_type; 44 bool ssc; 45 46 u32 max_link_rate; 47 u32 max_lane_count; 48 }; 49 50 static void 51 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 52 bool enable) 53 { 54 u8 data; 55 56 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 57 58 if (enable) 59 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 60 DP_LANE_COUNT_ENHANCED_FRAME_EN | 61 DPCD_LANE_COUNT_SET(data)); 62 else 63 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 64 DPCD_LANE_COUNT_SET(data)); 65 } 66 67 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 68 { 69 u8 data; 70 int retval; 71 72 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 73 retval = DPCD_ENHANCED_FRAME_CAP(data); 74 75 return retval; 76 } 77 78 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 79 { 80 u8 data; 81 82 data = analogix_dp_is_enhanced_mode_available(dp); 83 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 84 analogix_dp_enable_enhanced_mode(dp, data); 85 } 86 87 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 88 { 89 analogix_dp_set_training_pattern(dp, DP_NONE); 90 91 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 92 DP_TRAINING_PATTERN_DISABLE); 93 } 94 95 static int analogix_dp_link_start(struct analogix_dp_device *dp) 96 { 97 u8 buf[4]; 98 int lane, lane_count, retval; 99 100 lane_count = dp->link_train.lane_count; 101 102 dp->link_train.lt_state = CLOCK_RECOVERY; 103 dp->link_train.eq_loop = 0; 104 105 for (lane = 0; lane < lane_count; lane++) 106 dp->link_train.cr_loop[lane] = 0; 107 108 /* Set link rate and count as you want to establish*/ 109 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 110 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 111 112 /* Setup RX configuration */ 113 buf[0] = dp->link_train.link_rate; 114 buf[1] = dp->link_train.lane_count; 115 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 116 if (retval) 117 return retval; 118 119 /* Spread AMP if required, enable 8b/10b coding */ 120 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 121 buf[1] = DP_SET_ANSI_8B10B; 122 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_DOWNSPREAD_CTRL, 123 2, buf); 124 if (retval < 0) 125 return retval; 126 127 /* Set TX voltage-swing and pre-emphasis to minimum */ 128 for (lane = 0; lane < lane_count; lane++) 129 dp->link_train.training_lane[lane] = 130 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 131 DP_TRAIN_PRE_EMPH_LEVEL_0; 132 analogix_dp_set_lane_link_training(dp); 133 134 /* Set training pattern 1 */ 135 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 136 137 /* Set RX training pattern */ 138 retval = analogix_dp_write_byte_to_dpcd(dp, 139 DP_TRAINING_PATTERN_SET, 140 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 141 if (retval) 142 return retval; 143 144 for (lane = 0; lane < lane_count; lane++) 145 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 146 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 147 148 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 149 lane_count, buf); 150 151 return retval; 152 } 153 154 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 155 { 156 int shift = (lane & 1) * 4; 157 u8 link_value = link_status[lane >> 1]; 158 159 return (link_value >> shift) & 0xf; 160 } 161 162 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 163 { 164 int lane; 165 u8 lane_status; 166 167 for (lane = 0; lane < lane_count; lane++) { 168 lane_status = analogix_dp_get_lane_status(link_status, lane); 169 if ((lane_status & DP_LANE_CR_DONE) == 0) 170 return -EINVAL; 171 } 172 return 0; 173 } 174 175 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 176 int lane_count) 177 { 178 int lane; 179 u8 lane_status; 180 181 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 182 return -EINVAL; 183 184 for (lane = 0; lane < lane_count; lane++) { 185 lane_status = analogix_dp_get_lane_status(link_status, lane); 186 lane_status &= DP_CHANNEL_EQ_BITS; 187 if (lane_status != DP_CHANNEL_EQ_BITS) 188 return -EINVAL; 189 } 190 191 return 0; 192 } 193 194 static unsigned char 195 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 196 { 197 int shift = (lane & 1) * 4; 198 u8 link_value = adjust_request[lane >> 1]; 199 200 return (link_value >> shift) & 0x3; 201 } 202 203 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 204 u8 adjust_request[2], 205 int lane) 206 { 207 int shift = (lane & 1) * 4; 208 u8 link_value = adjust_request[lane >> 1]; 209 210 return ((link_value >> shift) & 0xc) >> 2; 211 } 212 213 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 214 { 215 analogix_dp_training_pattern_dis(dp); 216 analogix_dp_set_enhanced_mode(dp); 217 218 dp->link_train.lt_state = FAILED; 219 } 220 221 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 222 u8 adjust_request[2]) 223 { 224 int lane, lane_count; 225 u8 voltage_swing, pre_emphasis, training_lane; 226 227 lane_count = dp->link_train.lane_count; 228 for (lane = 0; lane < lane_count; lane++) { 229 voltage_swing = analogix_dp_get_adjust_request_voltage( 230 adjust_request, lane); 231 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 232 adjust_request, lane); 233 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 234 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 235 236 if (voltage_swing == VOLTAGE_LEVEL_3) 237 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 238 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 239 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 240 241 dp->link_train.training_lane[lane] = training_lane; 242 } 243 } 244 245 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp) 246 { 247 bool source_tps3_supported, sink_tps3_supported; 248 u8 dpcd = 0; 249 250 source_tps3_supported = 251 dp->video_info.max_link_rate == DP_LINK_BW_5_4; 252 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &dpcd); 253 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; 254 255 return source_tps3_supported && sink_tps3_supported; 256 } 257 258 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 259 { 260 int lane, lane_count, retval; 261 u8 voltage_swing, pre_emphasis, training_lane; 262 u8 link_status[2], adjust_request[2]; 263 u8 training_pattern = TRAINING_PTN2; 264 265 drm_dp_link_train_clock_recovery_delay(dp->dpcd); 266 267 lane_count = dp->link_train.lane_count; 268 269 retval = analogix_dp_read_bytes_from_dpcd(dp, 270 DP_LANE0_1_STATUS, 2, link_status); 271 if (retval) 272 return retval; 273 274 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 275 if (analogix_dp_tps3_supported(dp)) 276 training_pattern = TRAINING_PTN3; 277 278 /* set training pattern for EQ */ 279 analogix_dp_set_training_pattern(dp, training_pattern); 280 281 retval = analogix_dp_write_byte_to_dpcd(dp, 282 DP_TRAINING_PATTERN_SET, 283 (training_pattern == TRAINING_PTN3 ? 284 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); 285 if (retval) 286 return retval; 287 288 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 289 dp->link_train.lt_state = EQUALIZER_TRAINING; 290 291 return 0; 292 } else { 293 retval = analogix_dp_read_bytes_from_dpcd(dp, 294 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 295 if (retval) 296 return retval; 297 298 for (lane = 0; lane < lane_count; lane++) { 299 training_lane = analogix_dp_get_lane_link_training( 300 dp, lane); 301 voltage_swing = analogix_dp_get_adjust_request_voltage( 302 adjust_request, lane); 303 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 304 adjust_request, lane); 305 306 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 307 voltage_swing && 308 DPCD_PRE_EMPHASIS_GET(training_lane) == 309 pre_emphasis) 310 dp->link_train.cr_loop[lane]++; 311 312 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 313 voltage_swing == VOLTAGE_LEVEL_3 || 314 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 315 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 316 dp->link_train.cr_loop[lane], 317 voltage_swing, pre_emphasis); 318 analogix_dp_reduce_link_rate(dp); 319 return -EIO; 320 } 321 } 322 } 323 324 analogix_dp_get_adjust_training_lane(dp, adjust_request); 325 analogix_dp_set_lane_link_training(dp); 326 327 retval = analogix_dp_write_bytes_to_dpcd(dp, 328 DP_TRAINING_LANE0_SET, lane_count, 329 dp->link_train.training_lane); 330 if (retval) 331 return retval; 332 333 return retval; 334 } 335 336 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 337 { 338 int lane_count, retval; 339 u32 reg; 340 u8 link_align, link_status[2], adjust_request[2]; 341 342 drm_dp_link_train_channel_eq_delay(dp->dpcd); 343 344 lane_count = dp->link_train.lane_count; 345 346 retval = analogix_dp_read_bytes_from_dpcd(dp, 347 DP_LANE0_1_STATUS, 2, link_status); 348 if (retval) 349 return retval; 350 351 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 352 analogix_dp_reduce_link_rate(dp); 353 return -EIO; 354 } 355 356 retval = analogix_dp_read_byte_from_dpcd(dp, 357 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 358 if (retval) 359 return retval; 360 361 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 362 /* traing pattern Set to Normal */ 363 analogix_dp_training_pattern_dis(dp); 364 365 printf("Link Training success!\n"); 366 367 analogix_dp_get_link_bandwidth(dp, ®); 368 dp->link_train.link_rate = reg; 369 analogix_dp_get_lane_count(dp, ®); 370 dp->link_train.lane_count = reg; 371 372 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 373 dp->link_train.link_rate, dp->link_train.lane_count); 374 375 /* set enhanced mode if available */ 376 analogix_dp_set_enhanced_mode(dp); 377 dp->link_train.lt_state = FINISHED; 378 379 return 0; 380 } 381 382 /* not all locked */ 383 dp->link_train.eq_loop++; 384 385 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 386 dev_dbg(dp->dev, "EQ Max loop\n"); 387 analogix_dp_reduce_link_rate(dp); 388 return -EIO; 389 } 390 391 retval = analogix_dp_read_bytes_from_dpcd(dp, 392 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 393 if (retval) 394 return retval; 395 396 analogix_dp_get_adjust_training_lane(dp, adjust_request); 397 analogix_dp_set_lane_link_training(dp); 398 399 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 400 lane_count, dp->link_train.training_lane); 401 402 return retval; 403 } 404 405 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 406 u8 *bandwidth) 407 { 408 u8 data; 409 410 /* 411 * For DP rev.1.1, Maximum link rate of Main Link lanes 412 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 413 * For DP rev.1.2, Maximum link rate of Main Link lanes 414 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 415 */ 416 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 417 *bandwidth = data; 418 } 419 420 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 421 u8 *lane_count) 422 { 423 u8 data; 424 425 /* 426 * For DP rev.1.1, Maximum number of Main Link lanes 427 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 428 */ 429 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 430 *lane_count = DPCD_MAX_LANE_COUNT(data); 431 } 432 433 static int analogix_dp_init_training(struct analogix_dp_device *dp, 434 enum link_lane_count_type max_lane, 435 int max_rate) 436 { 437 u8 dpcd; 438 439 /* 440 * MACRO_RST must be applied after the PLL_LOCK to avoid 441 * the DP inter pair skew issue for at least 10 us 442 */ 443 analogix_dp_reset_macro(dp); 444 445 /* Initialize by reading RX's DPCD */ 446 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 447 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 448 449 /* Setup TX lane count & rate */ 450 dp->link_train.lane_count = min_t(u8, dp->link_train.lane_count, 451 max_lane); 452 dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate, 453 max_rate); 454 455 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_DOWNSPREAD, &dpcd); 456 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 457 458 /* All DP analog module power up */ 459 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 460 461 return 0; 462 } 463 464 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 465 { 466 int retval = 0, training_finished = 0; 467 468 dp->link_train.lt_state = START; 469 470 /* Process here */ 471 while (!retval && !training_finished) { 472 switch (dp->link_train.lt_state) { 473 case START: 474 retval = analogix_dp_link_start(dp); 475 if (retval) 476 dev_err(dp->dev, "LT link start failed!\n"); 477 break; 478 case CLOCK_RECOVERY: 479 retval = analogix_dp_process_clock_recovery(dp); 480 if (retval) 481 dev_err(dp->dev, "LT CR failed!\n"); 482 break; 483 case EQUALIZER_TRAINING: 484 retval = analogix_dp_process_equalizer_training(dp); 485 if (retval) 486 dev_err(dp->dev, "LT EQ failed!\n"); 487 break; 488 case FINISHED: 489 training_finished = 1; 490 break; 491 case FAILED: 492 return -EREMOTEIO; 493 } 494 } 495 496 return retval; 497 } 498 499 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 500 u32 count, u32 bwtype) 501 { 502 int i, ret; 503 504 for (i = 0; i < 5; i++) { 505 ret = analogix_dp_init_training(dp, count, bwtype); 506 if (ret < 0) { 507 dev_err(dp->dev, "failed to init training\n"); 508 return ret; 509 } 510 511 ret = analogix_dp_sw_link_training(dp); 512 if (!ret) 513 break; 514 } 515 516 return ret; 517 } 518 519 static int analogix_dp_config_video(struct analogix_dp_device *dp) 520 { 521 int timeout_loop = 0; 522 int done_count = 0; 523 524 analogix_dp_config_video_slave_mode(dp); 525 526 analogix_dp_set_video_color_format(dp); 527 528 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 529 dev_err(dp->dev, "PLL is not locked yet.\n"); 530 return -EINVAL; 531 } 532 533 for (;;) { 534 timeout_loop++; 535 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 536 break; 537 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 538 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 539 return -ETIMEDOUT; 540 } 541 542 udelay(2); 543 } 544 545 /* Set to use the register calculated M/N video */ 546 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 547 548 /* For video bist, Video timing must be generated by register */ 549 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_REGISTER); 550 551 /* Disable video mute */ 552 analogix_dp_enable_video_mute(dp, 0); 553 554 /* Configure video slave mode */ 555 analogix_dp_enable_video_master(dp, 0); 556 557 /* Enable video input */ 558 analogix_dp_start_video(dp); 559 560 timeout_loop = 0; 561 562 for (;;) { 563 timeout_loop++; 564 if (analogix_dp_is_video_stream_on(dp) == 0) { 565 done_count++; 566 if (done_count > 10) 567 break; 568 } else if (done_count) { 569 done_count = 0; 570 } 571 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 572 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 573 return -ETIMEDOUT; 574 } 575 576 udelay(1001); 577 } 578 579 return 0; 580 } 581 582 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 583 bool enable) 584 { 585 u8 data; 586 587 if (enable) { 588 analogix_dp_enable_scrambling(dp); 589 590 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 591 &data); 592 analogix_dp_write_byte_to_dpcd(dp, 593 DP_TRAINING_PATTERN_SET, 594 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 595 } else { 596 analogix_dp_disable_scrambling(dp); 597 598 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 599 &data); 600 analogix_dp_write_byte_to_dpcd(dp, 601 DP_TRAINING_PATTERN_SET, 602 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 603 } 604 } 605 606 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 607 { 608 analogix_dp_reset(dp); 609 610 analogix_dp_swreset(dp); 611 612 analogix_dp_init_analog_param(dp); 613 analogix_dp_init_interrupt(dp); 614 615 /* SW defined function Normal operation */ 616 analogix_dp_enable_sw_function(dp); 617 618 analogix_dp_config_interrupt(dp); 619 analogix_dp_init_analog_func(dp); 620 621 analogix_dp_init_hpd(dp); 622 analogix_dp_init_aux(dp); 623 } 624 625 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 626 { 627 int i; 628 unsigned char sum = 0; 629 630 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 631 sum = sum + edid_data[i]; 632 633 return sum; 634 } 635 636 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 637 { 638 unsigned char *edid = dp->edid; 639 unsigned int extend_block = 0; 640 unsigned char test_vector; 641 int retval; 642 643 /* 644 * EDID device address is 0x50. 645 * However, if necessary, you must have set upper address 646 * into E-EDID in I2C device, 0x30. 647 */ 648 649 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 650 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 651 EDID_EXTENSION_FLAG, 652 &extend_block); 653 if (retval) 654 return retval; 655 656 if (extend_block > 0) { 657 debug("EDID data includes a single extension!\n"); 658 659 /* Read EDID data */ 660 retval = analogix_dp_read_bytes_from_i2c(dp, 661 I2C_EDID_DEVICE_ADDR, 662 EDID_HEADER_PATTERN, 663 EDID_BLOCK_LENGTH, 664 &edid[EDID_HEADER_PATTERN]); 665 if (retval < 0) 666 return retval; 667 668 if (analogix_dp_calc_edid_check_sum(edid)) 669 return -EINVAL; 670 671 /* Read additional EDID data */ 672 retval = analogix_dp_read_bytes_from_i2c(dp, 673 I2C_EDID_DEVICE_ADDR, 674 EDID_BLOCK_LENGTH, 675 EDID_BLOCK_LENGTH, 676 &edid[EDID_BLOCK_LENGTH]); 677 if (retval < 0) 678 return retval; 679 680 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 681 return -EINVAL; 682 683 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 684 &test_vector); 685 if (test_vector & DP_TEST_LINK_EDID_READ) { 686 analogix_dp_write_byte_to_dpcd(dp, 687 DP_TEST_EDID_CHECKSUM, 688 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 689 analogix_dp_write_byte_to_dpcd(dp, 690 DP_TEST_RESPONSE, 691 DP_TEST_EDID_CHECKSUM_WRITE); 692 } 693 } else { 694 dev_info(dp->dev, 695 "EDID data does not include any extensions.\n"); 696 697 /* Read EDID data */ 698 retval = analogix_dp_read_bytes_from_i2c(dp, 699 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 700 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 701 if (retval < 0) 702 return retval; 703 704 if (analogix_dp_calc_edid_check_sum(edid)) 705 return -EINVAL; 706 707 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 708 &test_vector); 709 if (test_vector & DP_TEST_LINK_EDID_READ) { 710 analogix_dp_write_byte_to_dpcd(dp, 711 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 712 analogix_dp_write_byte_to_dpcd(dp, 713 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 714 } 715 } 716 717 return 0; 718 } 719 720 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 721 { 722 u8 buf[12]; 723 int i, try = 5; 724 int retval; 725 726 retry: 727 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 728 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 729 730 if (retval && try--) { 731 mdelay(10); 732 goto retry; 733 } 734 735 if (retval) 736 return retval; 737 738 /* Read EDID */ 739 for (i = 0; i < 3; i++) { 740 retval = analogix_dp_read_edid(dp); 741 if (!retval) 742 break; 743 } 744 745 return retval; 746 } 747 748 static int analogix_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 749 { 750 struct connector_state *conn_state = &state->conn_state; 751 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 752 753 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; 754 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 755 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 756 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 757 758 reset_assert_bulk(&dp->resets); 759 udelay(1); 760 reset_deassert_bulk(&dp->resets); 761 762 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 763 generic_phy_set_mode(&dp->phy, PHY_MODE_DP); 764 generic_phy_power_on(&dp->phy); 765 analogix_dp_init_dp(dp); 766 767 return 0; 768 } 769 770 static int analogix_dp_connector_get_edid(struct rockchip_connector *conn, 771 struct display_state *state) 772 { 773 struct connector_state *conn_state = &state->conn_state; 774 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 775 int ret; 776 777 ret = analogix_dp_handle_edid(dp); 778 if (ret) { 779 dev_err(dp->dev, "failed to get edid\n"); 780 return ret; 781 } 782 783 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 784 785 return 0; 786 } 787 788 static int analogix_dp_link_power_up(struct analogix_dp_device *dp) 789 { 790 u8 value; 791 int ret; 792 793 if (dp->dpcd[DP_DPCD_REV] < 0x11) 794 return 0; 795 796 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 797 if (ret < 0) 798 return ret; 799 800 value &= ~DP_SET_POWER_MASK; 801 value |= DP_SET_POWER_D0; 802 803 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 804 if (ret < 0) 805 return ret; 806 807 mdelay(1); 808 809 return 0; 810 } 811 812 static int analogix_dp_link_power_down(struct analogix_dp_device *dp) 813 { 814 u8 value; 815 int ret; 816 817 if (dp->dpcd[DP_DPCD_REV] < 0x11) 818 return 0; 819 820 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 821 if (ret < 0) 822 return ret; 823 824 value &= ~DP_SET_POWER_MASK; 825 value |= DP_SET_POWER_D3; 826 827 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 828 if (ret < 0) 829 return ret; 830 831 return 0; 832 } 833 834 static int analogix_dp_connector_enable(struct rockchip_connector *conn, 835 struct display_state *state) 836 { 837 struct connector_state *conn_state = &state->conn_state; 838 struct crtc_state *crtc_state = &state->crtc_state; 839 const struct rockchip_dp_chip_data *pdata = 840 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 841 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 842 struct video_info *video = &dp->video_info; 843 u32 val; 844 int ret; 845 846 if (pdata->lcdsel_grf_reg) { 847 if (crtc_state->crtc_id) 848 val = pdata->lcdsel_lit; 849 else 850 val = pdata->lcdsel_big; 851 852 regmap_write(dp->grf, pdata->lcdsel_grf_reg, val); 853 } 854 855 if (pdata->chip_type == RK3588_EDP) 856 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 857 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); 858 859 switch (conn_state->bpc) { 860 case 12: 861 video->color_depth = COLOR_12; 862 break; 863 case 10: 864 video->color_depth = COLOR_10; 865 break; 866 case 6: 867 video->color_depth = COLOR_6; 868 break; 869 case 8: 870 default: 871 video->color_depth = COLOR_8; 872 break; 873 } 874 875 ret = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 876 DP_RECEIVER_CAP_SIZE, dp->dpcd); 877 if (ret) { 878 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret); 879 return ret; 880 } 881 882 ret = analogix_dp_link_power_up(dp); 883 if (ret) { 884 dev_err(dp->dev, "failed to power up link: %d\n", ret); 885 return ret; 886 } 887 888 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 889 dp->video_info.max_link_rate); 890 if (ret) { 891 dev_err(dp->dev, "unable to do link train\n"); 892 return ret; 893 } 894 895 analogix_dp_enable_scramble(dp, 1); 896 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 897 analogix_dp_enable_enhanced_mode(dp, 1); 898 899 analogix_dp_init_video(dp); 900 analogix_dp_set_video_format(dp, &conn_state->mode); 901 902 if (dp->video_bist_enable) 903 analogix_dp_video_bist_enable(dp); 904 905 ret = analogix_dp_config_video(dp); 906 if (ret) { 907 dev_err(dp->dev, "unable to config video\n"); 908 return ret; 909 } 910 911 return 0; 912 } 913 914 static int analogix_dp_connector_disable(struct rockchip_connector *conn, 915 struct display_state *state) 916 { 917 const struct rockchip_dp_chip_data *pdata = 918 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 919 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 920 921 if (!analogix_dp_get_plug_in_status(dp)) 922 analogix_dp_link_power_down(dp); 923 924 if (pdata->chip_type == RK3588_EDP) 925 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 926 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 0)); 927 928 return 0; 929 } 930 931 static int analogix_dp_connector_detect(struct rockchip_connector *conn, 932 struct display_state *state) 933 { 934 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 935 936 return analogix_dp_detect(dp); 937 } 938 939 static int analogix_dp_connector_mode_valid(struct rockchip_connector *conn, 940 struct display_state *state) 941 { 942 struct connector_state *conn_state = &state->conn_state; 943 struct videomode vm; 944 945 drm_display_mode_to_videomode(&conn_state->mode, &vm); 946 947 if (!vm.hfront_porch || !vm.hback_porch || !vm.vfront_porch || !vm.vback_porch) { 948 dev_err(dp->dev, "front porch or back porch can not be 0\n"); 949 return MODE_BAD; 950 } 951 952 return MODE_OK; 953 } 954 955 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 956 .init = analogix_dp_connector_init, 957 .get_edid = analogix_dp_connector_get_edid, 958 .enable = analogix_dp_connector_enable, 959 .disable = analogix_dp_connector_disable, 960 .detect = analogix_dp_connector_detect, 961 .mode_valid = analogix_dp_connector_mode_valid, 962 }; 963 964 static u32 analogix_dp_parse_link_frequencies(struct analogix_dp_device *dp) 965 { 966 struct udevice *dev = dp->dev; 967 const struct device_node *endpoint; 968 u64 frequency = 0; 969 970 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 971 if (!endpoint) 972 return 0; 973 974 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 975 return 0; 976 977 if (!frequency) 978 return 0; 979 980 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 981 982 switch (frequency) { 983 case 162000: 984 case 270000: 985 case 540000: 986 break; 987 default: 988 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 989 return 0; 990 } 991 992 return frequency; 993 } 994 995 static int analogix_dp_parse_dt(struct analogix_dp_device *dp) 996 { 997 struct udevice *dev = dp->dev; 998 int len; 999 u32 num_lanes; 1000 u32 max_link_rate; 1001 int ret; 1002 1003 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1004 dp->video_bist_enable = dev_read_bool(dev, "analogix,video-bist-enable"); 1005 dp->video_info.force_stream_valid = 1006 dev_read_bool(dev, "analogix,force-stream-valid"); 1007 1008 max_link_rate = analogix_dp_parse_link_frequencies(dp); 1009 if (max_link_rate && max_link_rate < drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate)) 1010 dp->video_info.max_link_rate = drm_dp_link_rate_to_bw_code(max_link_rate); 1011 1012 if (dev_read_prop(dev, "data-lanes", &len)) { 1013 num_lanes = len / sizeof(u32); 1014 if (num_lanes < 1 || num_lanes > 4 || num_lanes == 3) { 1015 dev_err(dev, "bad number of data lanes\n"); 1016 return -EINVAL; 1017 } 1018 1019 ret = dev_read_u32_array(dev, "data-lanes", dp->lane_map, 1020 num_lanes); 1021 if (ret) 1022 return ret; 1023 1024 dp->video_info.max_lane_count = num_lanes; 1025 } else { 1026 dp->lane_map[0] = 0; 1027 dp->lane_map[1] = 1; 1028 dp->lane_map[2] = 2; 1029 dp->lane_map[3] = 3; 1030 } 1031 1032 return 0; 1033 } 1034 1035 static int analogix_dp_probe(struct udevice *dev) 1036 { 1037 struct analogix_dp_device *dp = dev_get_priv(dev); 1038 const struct rockchip_dp_chip_data *pdata = 1039 (const struct rockchip_dp_chip_data *)dev_get_driver_data(dev); 1040 struct udevice *syscon; 1041 int ret; 1042 1043 dp->reg_base = dev_read_addr_ptr(dev); 1044 1045 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 1046 if (dp->id < 0) 1047 dp->id = 0; 1048 1049 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1050 &syscon); 1051 if (!ret) { 1052 dp->grf = syscon_get_regmap(syscon); 1053 if (!dp->grf) 1054 return -ENODEV; 1055 } 1056 1057 ret = reset_get_bulk(dev, &dp->resets); 1058 if (ret) { 1059 dev_err(dev, "failed to get reset control: %d\n", ret); 1060 return ret; 1061 } 1062 1063 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1064 GPIOD_IS_IN); 1065 if (ret && ret != -ENOENT) { 1066 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1067 return ret; 1068 } 1069 1070 generic_phy_get_by_name(dev, "dp", &dp->phy); 1071 1072 dp->plat_data.dev_type = ROCKCHIP_DP; 1073 dp->plat_data.subdev_type = pdata->chip_type; 1074 dp->plat_data.ssc = pdata->ssc; 1075 1076 dp->video_info.max_link_rate = pdata->max_link_rate; 1077 dp->video_info.max_lane_count = pdata->max_lane_count; 1078 1079 dp->dev = dev; 1080 1081 ret = analogix_dp_parse_dt(dp); 1082 if (ret) { 1083 dev_err(dev, "failed to parse DT: %d\n", ret); 1084 return ret; 1085 } 1086 1087 rockchip_connector_bind(&dp->connector, dev, dp->id, &analogix_dp_connector_funcs, 1088 NULL, DRM_MODE_CONNECTOR_eDP); 1089 1090 return 0; 1091 } 1092 1093 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 1094 .lcdsel_grf_reg = 0x025c, 1095 .lcdsel_big = 0 | BIT(21), 1096 .lcdsel_lit = BIT(5) | BIT(21), 1097 .chip_type = RK3288_DP, 1098 1099 .max_link_rate = DP_LINK_BW_2_7, 1100 .max_lane_count = 4, 1101 }; 1102 1103 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 1104 .chip_type = RK3368_EDP, 1105 1106 .max_link_rate = DP_LINK_BW_2_7, 1107 .max_lane_count = 4, 1108 }; 1109 1110 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 1111 .lcdsel_grf_reg = 0x6250, 1112 .lcdsel_big = 0 | BIT(21), 1113 .lcdsel_lit = BIT(5) | BIT(21), 1114 .chip_type = RK3399_EDP, 1115 .ssc = true, 1116 1117 .max_link_rate = DP_LINK_BW_5_4, 1118 .max_lane_count = 4, 1119 }; 1120 1121 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 1122 .chip_type = RK3568_EDP, 1123 .ssc = true, 1124 1125 .max_link_rate = DP_LINK_BW_2_7, 1126 .max_lane_count = 4, 1127 }; 1128 1129 static const struct rockchip_dp_chip_data rk3576_edp_platform_data = { 1130 .chip_type = RK3576_EDP, 1131 .ssc = true, 1132 1133 .max_link_rate = DP_LINK_BW_5_4, 1134 .max_lane_count = 4, 1135 }; 1136 1137 static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { 1138 .chip_type = RK3588_EDP, 1139 .ssc = true, 1140 1141 .max_link_rate = DP_LINK_BW_5_4, 1142 .max_lane_count = 4, 1143 }; 1144 1145 static const struct udevice_id analogix_dp_ids[] = { 1146 { 1147 .compatible = "rockchip,rk3288-dp", 1148 .data = (ulong)&rk3288_edp_platform_data, 1149 }, { 1150 .compatible = "rockchip,rk3368-edp", 1151 .data = (ulong)&rk3368_edp_platform_data, 1152 }, { 1153 .compatible = "rockchip,rk3399-edp", 1154 .data = (ulong)&rk3399_edp_platform_data, 1155 }, { 1156 .compatible = "rockchip,rk3568-edp", 1157 .data = (ulong)&rk3568_edp_platform_data, 1158 }, { 1159 .compatible = "rockchip,rk3576-edp", 1160 .data = (ulong)&rk3576_edp_platform_data, 1161 }, { 1162 .compatible = "rockchip,rk3588-edp", 1163 .data = (ulong)&rk3588_edp_platform_data, 1164 }, 1165 {} 1166 }; 1167 1168 U_BOOT_DRIVER(analogix_dp) = { 1169 .name = "analogix_dp", 1170 .id = UCLASS_DISPLAY, 1171 .of_match = analogix_dp_ids, 1172 .probe = analogix_dp_probe, 1173 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1174 }; 1175