1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/bitfield.h> 17 #include <linux/list.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <asm/gpio.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "analogix_dp.h" 26 27 #define RK3588_GRF_VO1_CON0 0x0000 28 #define EDP_MODE BIT(0) 29 #define RK3588_GRF_VO1_CON1 0x0004 30 31 /** 32 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 33 * @lcdsel_grf_reg: grf register offset of lcdc select 34 * @lcdsel_big: reg value of selecting vop big for eDP 35 * @lcdsel_lit: reg value of selecting vop little for eDP 36 * @chip_type: specific chip type 37 * @ssc: check if SSC is supported by source 38 */ 39 struct rockchip_dp_chip_data { 40 u32 lcdsel_grf_reg; 41 u32 lcdsel_big; 42 u32 lcdsel_lit; 43 u32 chip_type; 44 bool ssc; 45 46 u32 max_link_rate; 47 u32 max_lane_count; 48 }; 49 50 static int 51 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 52 bool enable) 53 { 54 u8 data; 55 int ret; 56 57 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); 58 if (ret != 1) 59 return ret; 60 61 if (enable) 62 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 63 DP_LANE_COUNT_ENHANCED_FRAME_EN | 64 DPCD_LANE_COUNT_SET(data)); 65 else 66 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 67 DPCD_LANE_COUNT_SET(data)); 68 69 return ret < 0 ? ret : 0; 70 } 71 72 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp, 73 u8 *enhanced_mode_support) 74 { 75 u8 data; 76 int ret; 77 78 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 79 if (ret != 1) { 80 *enhanced_mode_support = 0; 81 return ret; 82 } 83 84 *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data); 85 86 return 0; 87 } 88 89 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 90 { 91 u8 data; 92 int ret; 93 94 ret = analogix_dp_is_enhanced_mode_available(dp, &data); 95 if (ret < 0) 96 return ret; 97 98 ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data); 99 if (ret < 0) 100 return ret; 101 102 analogix_dp_enable_enhanced_mode(dp, data); 103 104 return 0; 105 } 106 107 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 108 { 109 int ret; 110 111 analogix_dp_set_training_pattern(dp, DP_NONE); 112 113 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 114 DP_TRAINING_PATTERN_DISABLE); 115 116 return ret < 0 ? ret : 0; 117 } 118 119 static int analogix_dp_link_start(struct analogix_dp_device *dp) 120 { 121 u8 buf[4]; 122 int lane, lane_count, retval; 123 124 lane_count = dp->link_train.lane_count; 125 126 dp->link_train.lt_state = CLOCK_RECOVERY; 127 dp->link_train.eq_loop = 0; 128 129 for (lane = 0; lane < lane_count; lane++) 130 dp->link_train.cr_loop[lane] = 0; 131 132 /* Set link rate and count as you want to establish */ 133 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 134 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 135 136 if (dp->nr_link_rate_table) { 137 /* Setup DP_LINK_RATE_SET for eDP 1.4 and later */ 138 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, dp->link_train.lane_count); 139 drm_dp_dpcd_writeb(&dp->aux, DP_LINK_RATE_SET, dp->link_rate_select); 140 } else { 141 /* Setup DP_LINK_BW_SET for eDP 1.3 and earlier */ 142 buf[0] = dp->link_train.link_rate; 143 buf[1] = dp->link_train.lane_count; 144 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2); 145 if (retval < 0) 146 return retval; 147 } 148 149 /* Spread AMP if required, enable 8b/10b coding */ 150 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 151 buf[1] = DP_SET_ANSI_8B10B; 152 retval = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 2); 153 if (retval < 0) 154 return retval; 155 156 /* Set TX voltage-swing and pre-emphasis to minimum */ 157 for (lane = 0; lane < lane_count; lane++) 158 dp->link_train.training_lane[lane] = 159 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 160 DP_TRAIN_PRE_EMPH_LEVEL_0; 161 analogix_dp_set_lane_link_training(dp); 162 163 /* Set training pattern 1 */ 164 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 165 166 /* Set RX training pattern */ 167 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 168 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 169 if (retval < 0) 170 return retval; 171 172 for (lane = 0; lane < lane_count; lane++) 173 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 174 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 175 176 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, 177 lane_count); 178 if (retval < 0) 179 return retval; 180 181 return 0; 182 } 183 184 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 185 { 186 int shift = (lane & 1) * 4; 187 u8 link_value = link_status[lane >> 1]; 188 189 return (link_value >> shift) & 0xf; 190 } 191 192 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 193 { 194 int lane; 195 u8 lane_status; 196 197 for (lane = 0; lane < lane_count; lane++) { 198 lane_status = analogix_dp_get_lane_status(link_status, lane); 199 if ((lane_status & DP_LANE_CR_DONE) == 0) 200 return -EINVAL; 201 } 202 return 0; 203 } 204 205 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 206 int lane_count) 207 { 208 int lane; 209 u8 lane_status; 210 211 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 212 return -EINVAL; 213 214 for (lane = 0; lane < lane_count; lane++) { 215 lane_status = analogix_dp_get_lane_status(link_status, lane); 216 lane_status &= DP_CHANNEL_EQ_BITS; 217 if (lane_status != DP_CHANNEL_EQ_BITS) 218 return -EINVAL; 219 } 220 221 return 0; 222 } 223 224 static unsigned char 225 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 226 { 227 int shift = (lane & 1) * 4; 228 u8 link_value = adjust_request[lane >> 1]; 229 230 return (link_value >> shift) & 0x3; 231 } 232 233 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 234 u8 adjust_request[2], 235 int lane) 236 { 237 int shift = (lane & 1) * 4; 238 u8 link_value = adjust_request[lane >> 1]; 239 240 return ((link_value >> shift) & 0xc) >> 2; 241 } 242 243 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 244 { 245 analogix_dp_training_pattern_dis(dp); 246 analogix_dp_set_enhanced_mode(dp); 247 248 dp->link_train.lt_state = FAILED; 249 } 250 251 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 252 u8 adjust_request[2]) 253 { 254 int lane, lane_count; 255 u8 voltage_swing, pre_emphasis, training_lane; 256 257 lane_count = dp->link_train.lane_count; 258 for (lane = 0; lane < lane_count; lane++) { 259 voltage_swing = analogix_dp_get_adjust_request_voltage( 260 adjust_request, lane); 261 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 262 adjust_request, lane); 263 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 264 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 265 266 if (voltage_swing == VOLTAGE_LEVEL_3) 267 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 268 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 269 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 270 271 dp->link_train.training_lane[lane] = training_lane; 272 } 273 } 274 275 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp) 276 { 277 bool source_tps3_supported, sink_tps3_supported; 278 u8 dpcd = 0; 279 280 source_tps3_supported = 281 dp->video_info.max_link_rate == DP_LINK_BW_5_4; 282 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &dpcd); 283 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; 284 285 return source_tps3_supported && sink_tps3_supported; 286 } 287 288 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 289 { 290 int lane, lane_count, retval; 291 u8 voltage_swing, pre_emphasis, training_lane; 292 u8 link_status[2], adjust_request[2]; 293 u8 training_pattern = TRAINING_PTN2; 294 295 drm_dp_link_train_clock_recovery_delay(dp->dpcd); 296 297 lane_count = dp->link_train.lane_count; 298 299 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 300 if (retval < 0) 301 return retval; 302 303 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 304 if (analogix_dp_tps3_supported(dp)) 305 training_pattern = TRAINING_PTN3; 306 307 /* set training pattern for EQ */ 308 analogix_dp_set_training_pattern(dp, training_pattern); 309 310 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 311 DP_LINK_SCRAMBLING_DISABLE | 312 (training_pattern == TRAINING_PTN3 ? 313 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); 314 if (retval < 0) 315 return retval; 316 317 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 318 dp->link_train.lt_state = EQUALIZER_TRAINING; 319 320 return 0; 321 } else { 322 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 323 adjust_request, 2); 324 if (retval < 0) 325 return retval; 326 327 for (lane = 0; lane < lane_count; lane++) { 328 training_lane = analogix_dp_get_lane_link_training( 329 dp, lane); 330 voltage_swing = analogix_dp_get_adjust_request_voltage( 331 adjust_request, lane); 332 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 333 adjust_request, lane); 334 335 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 336 voltage_swing && 337 DPCD_PRE_EMPHASIS_GET(training_lane) == 338 pre_emphasis) 339 dp->link_train.cr_loop[lane]++; 340 341 /* 342 * In DP spec 1.3, Condition of CR fail are 343 * outlined in section 3.5.1.2.2.1, figure 3-20: 344 * 345 * 1. Maximum Voltage Swing reached 346 * 2. Same Voltage five times 347 */ 348 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 349 DPCD_VOLTAGE_SWING_GET(training_lane) == VOLTAGE_LEVEL_3) { 350 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 351 dp->link_train.cr_loop[lane], 352 voltage_swing, pre_emphasis); 353 analogix_dp_reduce_link_rate(dp); 354 return -EIO; 355 } 356 } 357 } 358 359 analogix_dp_get_adjust_training_lane(dp, adjust_request); 360 analogix_dp_set_lane_link_training(dp); 361 362 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 363 dp->link_train.training_lane, lane_count); 364 if (retval < 0) 365 return retval; 366 367 return 0; 368 } 369 370 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 371 { 372 int lane_count, retval; 373 u32 reg; 374 u8 link_align, link_status[2], adjust_request[2]; 375 376 drm_dp_link_train_channel_eq_delay(dp->dpcd); 377 378 lane_count = dp->link_train.lane_count; 379 380 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 381 if (retval < 0) 382 return retval; 383 384 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 385 analogix_dp_reduce_link_rate(dp); 386 return -EIO; 387 } 388 389 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 390 if (retval < 0) 391 return retval; 392 393 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 394 /* traing pattern Set to Normal */ 395 retval = analogix_dp_training_pattern_dis(dp); 396 if (retval < 0) 397 return retval; 398 399 printf("Link Training success!\n"); 400 401 analogix_dp_get_link_bandwidth(dp, ®); 402 dp->link_train.link_rate = reg; 403 analogix_dp_get_lane_count(dp, ®); 404 dp->link_train.lane_count = reg; 405 406 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 407 dp->link_train.link_rate, dp->link_train.lane_count); 408 409 /* set enhanced mode if available */ 410 retval = analogix_dp_set_enhanced_mode(dp); 411 if (retval < 0) { 412 dev_err(dp->dev, "failed to set enhance mode\n"); 413 return retval; 414 } 415 416 dp->link_train.lt_state = FINISHED; 417 418 return 0; 419 } 420 421 /* not all locked */ 422 dp->link_train.eq_loop++; 423 424 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 425 dev_dbg(dp->dev, "EQ Max loop\n"); 426 analogix_dp_reduce_link_rate(dp); 427 return -EIO; 428 } 429 430 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, adjust_request, 2); 431 if (retval < 0) 432 return retval; 433 434 analogix_dp_get_adjust_training_lane(dp, adjust_request); 435 analogix_dp_set_lane_link_training(dp); 436 437 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 438 dp->link_train.training_lane, lane_count); 439 if (retval < 0) 440 return retval; 441 442 return 0; 443 } 444 445 static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp, 446 const struct drm_display_mode *mode, 447 unsigned int rate, unsigned int lanes) 448 { 449 u32 max_bw, req_bw; 450 u32 bpp = 3 * dp->video_info.bpc; 451 452 req_bw = mode->clock * bpp / 8; 453 max_bw = lanes * rate; 454 if (req_bw > max_bw) 455 return false; 456 457 return true; 458 } 459 460 static bool analogix_dp_link_config_validate(u8 link_rate, u8 lane_count) 461 { 462 switch (link_rate) { 463 case DP_LINK_BW_1_62: 464 case DP_LINK_BW_2_7: 465 case DP_LINK_BW_5_4: 466 /* Supported link rate in eDP 1.4 */ 467 case EDP_LINK_BW_2_16: 468 case EDP_LINK_BW_2_43: 469 case EDP_LINK_BW_3_24: 470 case EDP_LINK_BW_4_32: 471 break; 472 default: 473 return false; 474 } 475 476 switch (lane_count) { 477 case LANE_COUNT1: 478 case LANE_COUNT2: 479 case LANE_COUNT4: 480 break; 481 default: 482 return false; 483 } 484 485 return true; 486 } 487 488 static int analogix_dp_select_link_rate_from_table(struct analogix_dp_device *dp) 489 { 490 int i; 491 u8 bw_code; 492 u32 max_link_rate = drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate); 493 494 for (i = 0; i < dp->nr_link_rate_table; i++) { 495 bw_code = drm_dp_link_rate_to_bw_code(dp->link_rate_table[i]); 496 497 if (!analogix_dp_bandwidth_ok(dp, &dp->video_info.mode, dp->link_rate_table[i], 498 dp->link_train.lane_count)) 499 continue; 500 501 if (dp->link_rate_table[i] <= max_link_rate && 502 analogix_dp_link_config_validate(bw_code, dp->link_train.lane_count)) { 503 dp->link_rate_select = i; 504 return bw_code; 505 } 506 } 507 508 return 0; 509 } 510 511 static int analogix_dp_select_rx_bandwidth(struct analogix_dp_device *dp) 512 { 513 if (dp->nr_link_rate_table) 514 /* 515 * Select the smallest one among link rates which meet 516 * the bandwidth requirement for eDP 1.4 and later. 517 */ 518 dp->link_train.link_rate = analogix_dp_select_link_rate_from_table(dp); 519 else 520 /* 521 * Select the smaller one between rx DP_MAX_LINK_RATE 522 * and the max link rate supported by the platform. 523 */ 524 dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate, 525 dp->video_info.max_link_rate); 526 if (!dp->link_train.link_rate) 527 return -EINVAL; 528 529 return 0; 530 } 531 532 static int analogix_dp_init_link_rate_table(struct analogix_dp_device *dp) 533 { 534 u8 link_rate_table[DP_MAX_SUPPORTED_RATES * 2]; 535 int i; 536 int ret; 537 538 ret = drm_dp_dpcd_read(&dp->aux, DP_SUPPORTED_LINK_RATES, link_rate_table, 539 sizeof(link_rate_table)); 540 if (ret < 0) 541 return ret; 542 543 for (i = 0; i < ARRAY_SIZE(link_rate_table) / 2; i++) { 544 int val = link_rate_table[2 * i] | link_rate_table[2 * i + 1] << 8; 545 546 if (val == 0) 547 break; 548 549 /* Convert to the link_rate as drm_dp_bw_code_to_link_rate() */ 550 dp->link_rate_table[i] = (val * 20); 551 } 552 dp->nr_link_rate_table = i; 553 554 return 0; 555 } 556 557 static int analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 558 u8 *bandwidth) 559 { 560 u8 data; 561 int ret; 562 563 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_DPCD_REV, &data); 564 if (ret == 1 && data >= DP_EDP_14) { 565 u32 max_link_rate; 566 567 /* As the Table 4-23 in eDP 1.4 spec, the link rate table is required */ 568 if (!dp->nr_link_rate_table) { 569 dev_info(dp->dev, "eDP version: 0x%02x supports link rate table\n", 570 data); 571 572 if (analogix_dp_init_link_rate_table(dp)) 573 dev_err(dp->dev, "failed to read link rate table: %d\n", 574 ret); 575 } 576 max_link_rate = dp->link_rate_table[dp->nr_link_rate_table - 1]; 577 *bandwidth = drm_dp_link_rate_to_bw_code(max_link_rate); 578 } else { 579 /* 580 * For DP rev.1.1, Maximum link rate of Main Link lanes 581 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 582 * For DP rev.1.2, Maximum link rate of Main Link lanes 583 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 584 */ 585 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data); 586 if (ret < 0) 587 return ret; 588 589 *bandwidth = data; 590 } 591 592 return 0; 593 } 594 595 static int analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 596 u8 *lane_count) 597 { 598 u8 data; 599 int ret; 600 601 /* 602 * For DP rev.1.1, Maximum number of Main Link lanes 603 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 604 */ 605 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 606 if (ret < 0) 607 return ret; 608 609 *lane_count = DPCD_MAX_LANE_COUNT(data); 610 611 return 0; 612 } 613 614 static int analogix_dp_init_training(struct analogix_dp_device *dp, 615 enum link_lane_count_type max_lane, 616 int max_rate) 617 { 618 u8 dpcd; 619 620 /* 621 * MACRO_RST must be applied after the PLL_LOCK to avoid 622 * the DP inter pair skew issue for at least 10 us 623 */ 624 analogix_dp_reset_macro(dp); 625 626 /* Initialize by reading RX's DPCD */ 627 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 628 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 629 630 /* Setup TX lane count */ 631 dp->link_train.lane_count = min_t(u32, dp->link_train.lane_count, max_lane); 632 633 /* Setup TX lane rate */ 634 if (analogix_dp_select_rx_bandwidth(dp)) { 635 dev_err(dp->dev, "Select rx bandwidth failed\n"); 636 return -EINVAL; 637 } 638 639 drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &dpcd); 640 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 641 642 /* All DP analog module power up */ 643 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 644 645 return 0; 646 } 647 648 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 649 { 650 int retval = 0, training_finished = 0; 651 652 dp->link_train.lt_state = START; 653 654 /* Process here */ 655 while (!retval && !training_finished) { 656 switch (dp->link_train.lt_state) { 657 case START: 658 retval = analogix_dp_link_start(dp); 659 if (retval) 660 dev_err(dp->dev, "LT link start failed!\n"); 661 break; 662 case CLOCK_RECOVERY: 663 retval = analogix_dp_process_clock_recovery(dp); 664 if (retval) 665 dev_err(dp->dev, "LT CR failed!\n"); 666 break; 667 case EQUALIZER_TRAINING: 668 retval = analogix_dp_process_equalizer_training(dp); 669 if (retval) 670 dev_err(dp->dev, "LT EQ failed!\n"); 671 break; 672 case FINISHED: 673 training_finished = 1; 674 break; 675 case FAILED: 676 return -EREMOTEIO; 677 } 678 } 679 680 return retval; 681 } 682 683 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 684 u32 count, u32 bwtype) 685 { 686 int i, ret; 687 688 for (i = 0; i < 5; i++) { 689 ret = analogix_dp_init_training(dp, count, bwtype); 690 if (ret < 0) { 691 dev_err(dp->dev, "failed to init training\n"); 692 return ret; 693 } 694 695 ret = analogix_dp_sw_link_training(dp); 696 if (!ret) 697 break; 698 } 699 700 return ret; 701 } 702 703 static int analogix_dp_config_video(struct analogix_dp_device *dp) 704 { 705 int timeout_loop = 0; 706 int done_count = 0; 707 708 analogix_dp_config_video_slave_mode(dp); 709 710 analogix_dp_set_video_color_format(dp); 711 712 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 713 dev_err(dp->dev, "PLL is not locked yet.\n"); 714 return -EINVAL; 715 } 716 717 for (;;) { 718 timeout_loop++; 719 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 720 break; 721 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 722 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 723 return -ETIMEDOUT; 724 } 725 726 udelay(2); 727 } 728 729 /* Set to use the register calculated M/N video */ 730 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 731 732 /* For video bist, Video timing must be generated by register */ 733 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_REGISTER); 734 735 /* Disable video mute */ 736 analogix_dp_enable_video_mute(dp, 0); 737 738 /* Configure video slave mode */ 739 analogix_dp_enable_video_master(dp, 0); 740 741 /* Enable video input */ 742 analogix_dp_start_video(dp); 743 744 timeout_loop = 0; 745 746 for (;;) { 747 timeout_loop++; 748 if (analogix_dp_is_video_stream_on(dp) == 0) { 749 done_count++; 750 if (done_count > 10) 751 break; 752 } else if (done_count) { 753 done_count = 0; 754 } 755 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 756 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 757 return -ETIMEDOUT; 758 } 759 760 udelay(1001); 761 } 762 763 return 0; 764 } 765 766 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp, 767 bool enable) 768 { 769 u8 data; 770 int ret; 771 772 if (enable) { 773 analogix_dp_enable_scrambling(dp); 774 775 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, 776 &data); 777 if (ret != 1) 778 return ret; 779 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 780 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 781 } else { 782 analogix_dp_disable_scrambling(dp); 783 784 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, 785 &data); 786 if (ret != 1) 787 return ret; 788 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 789 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 790 } 791 return ret < 0 ? ret : 0; 792 } 793 794 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 795 { 796 analogix_dp_reset(dp); 797 798 analogix_dp_swreset(dp); 799 800 analogix_dp_init_analog_param(dp); 801 analogix_dp_init_interrupt(dp); 802 803 /* SW defined function Normal operation */ 804 analogix_dp_enable_sw_function(dp); 805 806 analogix_dp_config_interrupt(dp); 807 analogix_dp_init_analog_func(dp); 808 809 analogix_dp_init_hpd(dp); 810 analogix_dp_init_aux(dp); 811 } 812 813 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 814 { 815 int i; 816 unsigned char sum = 0; 817 818 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 819 sum = sum + edid_data[i]; 820 821 return sum; 822 } 823 824 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 825 { 826 unsigned char *edid = dp->edid; 827 unsigned int extend_block = 0; 828 unsigned char test_vector; 829 int retval; 830 831 /* 832 * EDID device address is 0x50. 833 * However, if necessary, you must have set upper address 834 * into E-EDID in I2C device, 0x30. 835 */ 836 837 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 838 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 839 EDID_EXTENSION_FLAG, 840 &extend_block); 841 if (retval) 842 return retval; 843 844 if (extend_block > 0) { 845 debug("EDID data includes a single extension!\n"); 846 847 /* Read EDID data */ 848 retval = analogix_dp_read_bytes_from_i2c(dp, 849 I2C_EDID_DEVICE_ADDR, 850 EDID_HEADER_PATTERN, 851 EDID_BLOCK_LENGTH, 852 &edid[EDID_HEADER_PATTERN]); 853 if (retval < 0) 854 return retval; 855 856 if (analogix_dp_calc_edid_check_sum(edid)) 857 return -EINVAL; 858 859 /* Read additional EDID data */ 860 retval = analogix_dp_read_bytes_from_i2c(dp, 861 I2C_EDID_DEVICE_ADDR, 862 EDID_BLOCK_LENGTH, 863 EDID_BLOCK_LENGTH, 864 &edid[EDID_BLOCK_LENGTH]); 865 if (retval < 0) 866 return retval; 867 868 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 869 return -EINVAL; 870 871 drm_dp_dpcd_readb(&dp->aux, DP_TEST_REQUEST, &test_vector); 872 if (test_vector & DP_TEST_LINK_EDID_READ) { 873 drm_dp_dpcd_writeb(&dp->aux, DP_TEST_EDID_CHECKSUM, 874 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 875 drm_dp_dpcd_writeb(&dp->aux, DP_TEST_RESPONSE, 876 DP_TEST_EDID_CHECKSUM_WRITE); 877 } 878 } else { 879 dev_info(dp->dev, 880 "EDID data does not include any extensions.\n"); 881 882 /* Read EDID data */ 883 retval = analogix_dp_read_bytes_from_i2c(dp, 884 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 885 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 886 if (retval < 0) 887 return retval; 888 889 if (analogix_dp_calc_edid_check_sum(edid)) 890 return -EINVAL; 891 892 drm_dp_dpcd_readb(&dp->aux, DP_TEST_REQUEST, &test_vector); 893 if (test_vector & DP_TEST_LINK_EDID_READ) { 894 drm_dp_dpcd_writeb(&dp->aux, DP_TEST_EDID_CHECKSUM, 895 edid[EDID_CHECKSUM]); 896 drm_dp_dpcd_writeb(&dp->aux, DP_TEST_RESPONSE, 897 DP_TEST_EDID_CHECKSUM_WRITE); 898 } 899 } 900 901 return 0; 902 } 903 904 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 905 { 906 u8 buf[12]; 907 int i, try = 5; 908 int retval; 909 910 retry: 911 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 912 retval = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, buf, 12); 913 if (retval < 0 && try--) { 914 mdelay(10); 915 goto retry; 916 } 917 918 if (retval) 919 return retval; 920 921 /* Read EDID */ 922 for (i = 0; i < 3; i++) { 923 retval = analogix_dp_read_edid(dp); 924 if (!retval) 925 break; 926 } 927 928 return retval; 929 } 930 931 static int analogix_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 932 { 933 struct connector_state *conn_state = &state->conn_state; 934 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 935 936 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; 937 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 938 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 939 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 940 941 reset_assert_bulk(&dp->resets); 942 udelay(1); 943 reset_deassert_bulk(&dp->resets); 944 945 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 946 generic_phy_set_mode(&dp->phy, PHY_MODE_DP); 947 generic_phy_power_on(&dp->phy); 948 analogix_dp_init_dp(dp); 949 950 return 0; 951 } 952 953 static int analogix_dp_connector_get_edid(struct rockchip_connector *conn, 954 struct display_state *state) 955 { 956 struct connector_state *conn_state = &state->conn_state; 957 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 958 int ret; 959 960 ret = analogix_dp_handle_edid(dp); 961 if (ret) { 962 dev_err(dp->dev, "failed to get edid\n"); 963 return ret; 964 } 965 966 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 967 968 return 0; 969 } 970 971 static int analogix_dp_link_power_up(struct analogix_dp_device *dp) 972 { 973 u8 value; 974 int ret; 975 976 if (dp->dpcd[DP_DPCD_REV] < 0x11) 977 return 0; 978 979 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 980 if (ret < 0) 981 return ret; 982 983 value &= ~DP_SET_POWER_MASK; 984 value |= DP_SET_POWER_D0; 985 986 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 987 if (ret < 0) 988 return ret; 989 990 mdelay(1); 991 992 return 0; 993 } 994 995 static int analogix_dp_link_power_down(struct analogix_dp_device *dp) 996 { 997 u8 value; 998 int ret; 999 1000 if (dp->dpcd[DP_DPCD_REV] < 0x11) 1001 return 0; 1002 1003 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 1004 if (ret < 0) 1005 return ret; 1006 1007 value &= ~DP_SET_POWER_MASK; 1008 value |= DP_SET_POWER_D3; 1009 1010 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 1011 if (ret < 0) 1012 return ret; 1013 1014 return 0; 1015 } 1016 1017 static int analogix_dp_connector_enable(struct rockchip_connector *conn, 1018 struct display_state *state) 1019 { 1020 struct connector_state *conn_state = &state->conn_state; 1021 struct crtc_state *crtc_state = &state->crtc_state; 1022 const struct rockchip_dp_chip_data *pdata = 1023 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1024 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1025 struct video_info *video = &dp->video_info; 1026 struct drm_display_mode mode; 1027 u32 val; 1028 int ret; 1029 1030 drm_mode_copy(&video->mode, &conn_state->mode); 1031 1032 if (pdata->lcdsel_grf_reg) { 1033 if (crtc_state->crtc_id) 1034 val = pdata->lcdsel_lit; 1035 else 1036 val = pdata->lcdsel_big; 1037 1038 regmap_write(dp->grf, pdata->lcdsel_grf_reg, val); 1039 } 1040 1041 if (pdata->chip_type == RK3588_EDP) 1042 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 1043 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); 1044 1045 video->bpc = conn_state->bpc; 1046 switch (video->bpc) { 1047 case 12: 1048 video->color_depth = COLOR_12; 1049 break; 1050 case 10: 1051 video->color_depth = COLOR_10; 1052 break; 1053 case 6: 1054 video->color_depth = COLOR_6; 1055 break; 1056 case 8: 1057 default: 1058 video->color_depth = COLOR_8; 1059 break; 1060 } 1061 1062 ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd, DP_RECEIVER_CAP_SIZE); 1063 if (ret < 0) { 1064 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret); 1065 return ret; 1066 } 1067 1068 ret = analogix_dp_link_power_up(dp); 1069 if (ret) { 1070 dev_err(dp->dev, "failed to power up link: %d\n", ret); 1071 return ret; 1072 } 1073 1074 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 1075 dp->video_info.max_link_rate); 1076 if (ret) { 1077 dev_err(dp->dev, "unable to do link train\n"); 1078 return ret; 1079 } 1080 1081 ret = analogix_dp_enable_scramble(dp, 1); 1082 if (ret < 0) { 1083 dev_err(dp->dev, "can not enable scramble\n"); 1084 return ret; 1085 } 1086 1087 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 1088 analogix_dp_enable_enhanced_mode(dp, 1); 1089 1090 analogix_dp_init_video(dp); 1091 1092 drm_mode_copy(&mode, &conn_state->mode); 1093 if (conn->dual_channel_mode) 1094 drm_mode_convert_to_origin_mode(&mode); 1095 analogix_dp_set_video_format(dp, &mode); 1096 1097 if (dp->video_bist_enable) 1098 analogix_dp_video_bist_enable(dp); 1099 1100 ret = analogix_dp_config_video(dp); 1101 if (ret) { 1102 dev_err(dp->dev, "unable to config video\n"); 1103 return ret; 1104 } 1105 1106 return 0; 1107 } 1108 1109 static int analogix_dp_connector_disable(struct rockchip_connector *conn, 1110 struct display_state *state) 1111 { 1112 const struct rockchip_dp_chip_data *pdata = 1113 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1114 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1115 1116 if (!analogix_dp_get_plug_in_status(dp)) 1117 analogix_dp_link_power_down(dp); 1118 1119 if (pdata->chip_type == RK3588_EDP) 1120 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 1121 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 0)); 1122 1123 return 0; 1124 } 1125 1126 static int analogix_dp_connector_detect(struct rockchip_connector *conn, 1127 struct display_state *state) 1128 { 1129 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1130 1131 return analogix_dp_detect(dp); 1132 } 1133 1134 static int analogix_dp_connector_mode_valid(struct rockchip_connector *conn, 1135 struct display_state *state) 1136 { 1137 struct connector_state *conn_state = &state->conn_state; 1138 struct videomode vm; 1139 1140 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1141 1142 if (!vm.hfront_porch || !vm.hback_porch || !vm.vfront_porch || !vm.vback_porch) { 1143 dev_err(dp->dev, "front porch or back porch can not be 0\n"); 1144 return MODE_BAD; 1145 } 1146 1147 return MODE_OK; 1148 } 1149 1150 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 1151 .init = analogix_dp_connector_init, 1152 .get_edid = analogix_dp_connector_get_edid, 1153 .enable = analogix_dp_connector_enable, 1154 .disable = analogix_dp_connector_disable, 1155 .detect = analogix_dp_connector_detect, 1156 .mode_valid = analogix_dp_connector_mode_valid, 1157 }; 1158 1159 static u32 analogix_dp_parse_link_frequencies(struct analogix_dp_device *dp) 1160 { 1161 struct udevice *dev = dp->dev; 1162 const struct device_node *endpoint; 1163 u64 frequency = 0; 1164 1165 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 1166 if (!endpoint) 1167 return 0; 1168 1169 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 1170 return 0; 1171 1172 if (!frequency) 1173 return 0; 1174 1175 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 1176 1177 switch (frequency) { 1178 case 162000: 1179 case 270000: 1180 case 540000: 1181 break; 1182 default: 1183 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 1184 return 0; 1185 } 1186 1187 return frequency; 1188 } 1189 1190 static int analogix_dp_parse_dt(struct analogix_dp_device *dp) 1191 { 1192 struct udevice *dev = dp->dev; 1193 int len; 1194 u32 num_lanes; 1195 u32 max_link_rate; 1196 int ret; 1197 1198 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1199 dp->video_bist_enable = dev_read_bool(dev, "analogix,video-bist-enable"); 1200 dp->video_info.force_stream_valid = 1201 dev_read_bool(dev, "analogix,force-stream-valid"); 1202 1203 max_link_rate = analogix_dp_parse_link_frequencies(dp); 1204 if (max_link_rate && max_link_rate < drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate)) 1205 dp->video_info.max_link_rate = drm_dp_link_rate_to_bw_code(max_link_rate); 1206 1207 if (dev_read_prop(dev, "data-lanes", &len)) { 1208 num_lanes = len / sizeof(u32); 1209 if (num_lanes < 1 || num_lanes > 4 || num_lanes == 3) { 1210 dev_err(dev, "bad number of data lanes\n"); 1211 return -EINVAL; 1212 } 1213 1214 ret = dev_read_u32_array(dev, "data-lanes", dp->lane_map, 1215 num_lanes); 1216 if (ret) 1217 return ret; 1218 1219 dp->video_info.max_lane_count = num_lanes; 1220 } else { 1221 dp->lane_map[0] = 0; 1222 dp->lane_map[1] = 1; 1223 dp->lane_map[2] = 2; 1224 dp->lane_map[3] = 3; 1225 } 1226 1227 return 0; 1228 } 1229 1230 static int analogix_dp_ddc_init(struct analogix_dp_device *dp) 1231 { 1232 dp->aux.name = "analogix-dp"; 1233 dp->aux.dev = dp->dev; 1234 dp->aux.transfer = analogix_dp_aux_transfer; 1235 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1236 1237 return 0; 1238 } 1239 1240 static int analogix_dp_probe(struct udevice *dev) 1241 { 1242 struct analogix_dp_device *dp = dev_get_priv(dev); 1243 const struct rockchip_dp_chip_data *pdata = 1244 (const struct rockchip_dp_chip_data *)dev_get_driver_data(dev); 1245 struct udevice *syscon; 1246 int ret; 1247 1248 dp->reg_base = dev_read_addr_ptr(dev); 1249 1250 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 1251 if (dp->id < 0) 1252 dp->id = 0; 1253 1254 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1255 &syscon); 1256 if (!ret) { 1257 dp->grf = syscon_get_regmap(syscon); 1258 if (!dp->grf) 1259 return -ENODEV; 1260 } 1261 1262 ret = reset_get_bulk(dev, &dp->resets); 1263 if (ret) { 1264 dev_err(dev, "failed to get reset control: %d\n", ret); 1265 return ret; 1266 } 1267 1268 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1269 GPIOD_IS_IN); 1270 if (ret && ret != -ENOENT) { 1271 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1272 return ret; 1273 } 1274 1275 generic_phy_get_by_name(dev, "dp", &dp->phy); 1276 1277 dp->plat_data.dev_type = ROCKCHIP_DP; 1278 dp->plat_data.subdev_type = pdata->chip_type; 1279 dp->plat_data.ssc = pdata->ssc; 1280 1281 dp->video_info.max_link_rate = pdata->max_link_rate; 1282 dp->video_info.max_lane_count = pdata->max_lane_count; 1283 1284 dp->dev = dev; 1285 1286 ret = analogix_dp_parse_dt(dp); 1287 if (ret) { 1288 dev_err(dev, "failed to parse DT: %d\n", ret); 1289 return ret; 1290 } 1291 1292 analogix_dp_ddc_init(dp); 1293 1294 rockchip_connector_bind(&dp->connector, dev, dp->id, &analogix_dp_connector_funcs, 1295 NULL, DRM_MODE_CONNECTOR_eDP); 1296 1297 return 0; 1298 } 1299 1300 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 1301 .lcdsel_grf_reg = 0x025c, 1302 .lcdsel_big = 0 | BIT(21), 1303 .lcdsel_lit = BIT(5) | BIT(21), 1304 .chip_type = RK3288_DP, 1305 1306 .max_link_rate = DP_LINK_BW_2_7, 1307 .max_lane_count = 4, 1308 }; 1309 1310 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 1311 .chip_type = RK3368_EDP, 1312 1313 .max_link_rate = DP_LINK_BW_2_7, 1314 .max_lane_count = 4, 1315 }; 1316 1317 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 1318 .lcdsel_grf_reg = 0x6250, 1319 .lcdsel_big = 0 | BIT(21), 1320 .lcdsel_lit = BIT(5) | BIT(21), 1321 .chip_type = RK3399_EDP, 1322 .ssc = true, 1323 1324 .max_link_rate = DP_LINK_BW_5_4, 1325 .max_lane_count = 4, 1326 }; 1327 1328 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 1329 .chip_type = RK3568_EDP, 1330 .ssc = true, 1331 1332 .max_link_rate = DP_LINK_BW_2_7, 1333 .max_lane_count = 4, 1334 }; 1335 1336 static const struct rockchip_dp_chip_data rk3576_edp_platform_data = { 1337 .chip_type = RK3576_EDP, 1338 .ssc = true, 1339 1340 .max_link_rate = DP_LINK_BW_5_4, 1341 .max_lane_count = 4, 1342 }; 1343 1344 static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { 1345 .chip_type = RK3588_EDP, 1346 .ssc = true, 1347 1348 .max_link_rate = DP_LINK_BW_5_4, 1349 .max_lane_count = 4, 1350 }; 1351 1352 static const struct udevice_id analogix_dp_ids[] = { 1353 { 1354 .compatible = "rockchip,rk3288-dp", 1355 .data = (ulong)&rk3288_edp_platform_data, 1356 }, { 1357 .compatible = "rockchip,rk3368-edp", 1358 .data = (ulong)&rk3368_edp_platform_data, 1359 }, { 1360 .compatible = "rockchip,rk3399-edp", 1361 .data = (ulong)&rk3399_edp_platform_data, 1362 }, { 1363 .compatible = "rockchip,rk3568-edp", 1364 .data = (ulong)&rk3568_edp_platform_data, 1365 }, { 1366 .compatible = "rockchip,rk3576-edp", 1367 .data = (ulong)&rk3576_edp_platform_data, 1368 }, { 1369 .compatible = "rockchip,rk3588-edp", 1370 .data = (ulong)&rk3588_edp_platform_data, 1371 }, 1372 {} 1373 }; 1374 1375 U_BOOT_DRIVER(analogix_dp) = { 1376 .name = "analogix_dp", 1377 .id = UCLASS_DISPLAY, 1378 .of_match = analogix_dp_ids, 1379 .probe = analogix_dp_probe, 1380 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1381 }; 1382