1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/read.h> 15 #include <linux/list.h> 16 #include <syscon.h> 17 #include <asm/arch-rockchip/clock.h> 18 #include <asm/gpio.h> 19 20 #include "rockchip_display.h" 21 #include "rockchip_crtc.h" 22 #include "rockchip_connector.h" 23 #include "analogix_dp.h" 24 25 /** 26 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 27 * @lcdsel_grf_reg: grf register offset of lcdc select 28 * @lcdsel_big: reg value of selecting vop big for eDP 29 * @lcdsel_lit: reg value of selecting vop little for eDP 30 */ 31 struct rockchip_dp_chip_data { 32 u32 lcdsel_grf_reg; 33 u32 lcdsel_big; 34 u32 lcdsel_lit; 35 u32 chip_type; 36 bool has_vop_sel; 37 }; 38 39 static void 40 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 41 bool enable) 42 { 43 u8 data; 44 45 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 46 47 if (enable) 48 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 49 DP_LANE_COUNT_ENHANCED_FRAME_EN | 50 DPCD_LANE_COUNT_SET(data)); 51 else 52 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 53 DPCD_LANE_COUNT_SET(data)); 54 } 55 56 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 57 { 58 u8 data; 59 int retval; 60 61 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 62 retval = DPCD_ENHANCED_FRAME_CAP(data); 63 64 return retval; 65 } 66 67 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 68 { 69 u8 data; 70 71 data = analogix_dp_is_enhanced_mode_available(dp); 72 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 73 analogix_dp_enable_enhanced_mode(dp, data); 74 } 75 76 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 77 { 78 analogix_dp_set_training_pattern(dp, DP_NONE); 79 80 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 81 DP_TRAINING_PATTERN_DISABLE); 82 } 83 84 static int analogix_dp_link_start(struct analogix_dp_device *dp) 85 { 86 u8 buf[4]; 87 int lane, lane_count, pll_tries, retval; 88 89 lane_count = dp->link_train.lane_count; 90 91 dp->link_train.lt_state = CLOCK_RECOVERY; 92 dp->link_train.eq_loop = 0; 93 94 for (lane = 0; lane < lane_count; lane++) 95 dp->link_train.cr_loop[lane] = 0; 96 97 /* Set link rate and count as you want to establish*/ 98 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 99 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 100 101 /* Setup RX configuration */ 102 buf[0] = dp->link_train.link_rate; 103 buf[1] = dp->link_train.lane_count; 104 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 105 if (retval) 106 return retval; 107 108 /* Set TX voltage-swing and pre-emphasis to minimum */ 109 for (lane = 0; lane < lane_count; lane++) 110 dp->link_train.training_lane[lane] = 111 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 112 DP_TRAIN_PRE_EMPH_LEVEL_0; 113 analogix_dp_set_lane_link_training(dp); 114 115 /* Wait for PLL lock */ 116 pll_tries = 0; 117 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 118 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { 119 dev_err(dp->dev, "Wait for PLL lock timed out\n"); 120 return -ETIMEDOUT; 121 } 122 123 pll_tries++; 124 udelay(120); 125 } 126 127 /* Set training pattern 1 */ 128 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 129 130 /* Set RX training pattern */ 131 retval = analogix_dp_write_byte_to_dpcd(dp, 132 DP_TRAINING_PATTERN_SET, 133 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 134 if (retval) 135 return retval; 136 137 for (lane = 0; lane < lane_count; lane++) 138 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 139 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 140 141 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 142 lane_count, buf); 143 144 return retval; 145 } 146 147 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 148 { 149 int shift = (lane & 1) * 4; 150 u8 link_value = link_status[lane >> 1]; 151 152 return (link_value >> shift) & 0xf; 153 } 154 155 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 156 { 157 int lane; 158 u8 lane_status; 159 160 for (lane = 0; lane < lane_count; lane++) { 161 lane_status = analogix_dp_get_lane_status(link_status, lane); 162 if ((lane_status & DP_LANE_CR_DONE) == 0) 163 return -EINVAL; 164 } 165 return 0; 166 } 167 168 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 169 int lane_count) 170 { 171 int lane; 172 u8 lane_status; 173 174 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 175 return -EINVAL; 176 177 for (lane = 0; lane < lane_count; lane++) { 178 lane_status = analogix_dp_get_lane_status(link_status, lane); 179 lane_status &= DP_CHANNEL_EQ_BITS; 180 if (lane_status != DP_CHANNEL_EQ_BITS) 181 return -EINVAL; 182 } 183 184 return 0; 185 } 186 187 static unsigned char 188 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 189 { 190 int shift = (lane & 1) * 4; 191 u8 link_value = adjust_request[lane >> 1]; 192 193 return (link_value >> shift) & 0x3; 194 } 195 196 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 197 u8 adjust_request[2], 198 int lane) 199 { 200 int shift = (lane & 1) * 4; 201 u8 link_value = adjust_request[lane >> 1]; 202 203 return ((link_value >> shift) & 0xc) >> 2; 204 } 205 206 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 207 { 208 analogix_dp_training_pattern_dis(dp); 209 analogix_dp_set_enhanced_mode(dp); 210 211 dp->link_train.lt_state = FAILED; 212 } 213 214 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 215 u8 adjust_request[2]) 216 { 217 int lane, lane_count; 218 u8 voltage_swing, pre_emphasis, training_lane; 219 220 lane_count = dp->link_train.lane_count; 221 for (lane = 0; lane < lane_count; lane++) { 222 voltage_swing = analogix_dp_get_adjust_request_voltage( 223 adjust_request, lane); 224 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 225 adjust_request, lane); 226 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 227 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 228 229 if (voltage_swing == VOLTAGE_LEVEL_3) 230 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 231 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 232 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 233 234 dp->link_train.training_lane[lane] = training_lane; 235 } 236 } 237 238 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 239 { 240 int lane, lane_count, retval; 241 u8 voltage_swing, pre_emphasis, training_lane; 242 u8 link_status[2], adjust_request[2]; 243 244 udelay(101); 245 246 lane_count = dp->link_train.lane_count; 247 248 retval = analogix_dp_read_bytes_from_dpcd(dp, 249 DP_LANE0_1_STATUS, 2, link_status); 250 if (retval) 251 return retval; 252 253 retval = analogix_dp_read_bytes_from_dpcd(dp, 254 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 255 if (retval) 256 return retval; 257 258 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 259 /* set training pattern 2 for EQ */ 260 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 261 262 retval = analogix_dp_write_byte_to_dpcd(dp, 263 DP_TRAINING_PATTERN_SET, 264 DP_LINK_SCRAMBLING_DISABLE | 265 DP_TRAINING_PATTERN_2); 266 if (retval) 267 return retval; 268 269 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 270 dp->link_train.lt_state = EQUALIZER_TRAINING; 271 } else { 272 for (lane = 0; lane < lane_count; lane++) { 273 training_lane = analogix_dp_get_lane_link_training( 274 dp, lane); 275 voltage_swing = analogix_dp_get_adjust_request_voltage( 276 adjust_request, lane); 277 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 278 adjust_request, lane); 279 280 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 281 voltage_swing && 282 DPCD_PRE_EMPHASIS_GET(training_lane) == 283 pre_emphasis) 284 dp->link_train.cr_loop[lane]++; 285 286 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 287 voltage_swing == VOLTAGE_LEVEL_3 || 288 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 289 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 290 dp->link_train.cr_loop[lane], 291 voltage_swing, pre_emphasis); 292 analogix_dp_reduce_link_rate(dp); 293 return -EIO; 294 } 295 } 296 } 297 298 analogix_dp_get_adjust_training_lane(dp, adjust_request); 299 analogix_dp_set_lane_link_training(dp); 300 301 retval = analogix_dp_write_bytes_to_dpcd(dp, 302 DP_TRAINING_LANE0_SET, lane_count, 303 dp->link_train.training_lane); 304 if (retval) 305 return retval; 306 307 return retval; 308 } 309 310 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 311 { 312 int lane_count, retval; 313 u32 reg; 314 u8 link_align, link_status[2], adjust_request[2]; 315 316 udelay(401); 317 318 lane_count = dp->link_train.lane_count; 319 320 retval = analogix_dp_read_bytes_from_dpcd(dp, 321 DP_LANE0_1_STATUS, 2, link_status); 322 if (retval) 323 return retval; 324 325 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 326 analogix_dp_reduce_link_rate(dp); 327 return -EIO; 328 } 329 330 retval = analogix_dp_read_bytes_from_dpcd(dp, 331 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 332 if (retval) 333 return retval; 334 335 retval = analogix_dp_read_byte_from_dpcd(dp, 336 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 337 if (retval) 338 return retval; 339 340 analogix_dp_get_adjust_training_lane(dp, adjust_request); 341 342 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 343 /* traing pattern Set to Normal */ 344 analogix_dp_training_pattern_dis(dp); 345 346 printf("Link Training success!\n"); 347 348 analogix_dp_get_link_bandwidth(dp, ®); 349 dp->link_train.link_rate = reg; 350 analogix_dp_get_lane_count(dp, ®); 351 dp->link_train.lane_count = reg; 352 353 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 354 dp->link_train.link_rate, dp->link_train.lane_count); 355 356 /* set enhanced mode if available */ 357 analogix_dp_set_enhanced_mode(dp); 358 dp->link_train.lt_state = FINISHED; 359 360 return 0; 361 } 362 363 /* not all locked */ 364 dp->link_train.eq_loop++; 365 366 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 367 dev_dbg(dp->dev, "EQ Max loop\n"); 368 analogix_dp_reduce_link_rate(dp); 369 return -EIO; 370 } 371 372 analogix_dp_set_lane_link_training(dp); 373 374 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 375 lane_count, dp->link_train.training_lane); 376 377 return retval; 378 } 379 380 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 381 u8 *bandwidth) 382 { 383 u8 data; 384 385 /* 386 * For DP rev.1.1, Maximum link rate of Main Link lanes 387 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 388 * For DP rev.1.2, Maximum link rate of Main Link lanes 389 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 390 */ 391 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 392 *bandwidth = data; 393 } 394 395 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 396 u8 *lane_count) 397 { 398 u8 data; 399 400 /* 401 * For DP rev.1.1, Maximum number of Main Link lanes 402 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 403 */ 404 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 405 *lane_count = DPCD_MAX_LANE_COUNT(data); 406 } 407 408 static int analogix_dp_init_training(struct analogix_dp_device *dp, 409 enum link_lane_count_type max_lane, 410 int max_rate) 411 { 412 /* 413 * MACRO_RST must be applied after the PLL_LOCK to avoid 414 * the DP inter pair skew issue for at least 10 us 415 */ 416 analogix_dp_reset_macro(dp); 417 418 /* Initialize by reading RX's DPCD */ 419 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 420 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 421 422 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 423 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 424 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 425 dev_err(dp->dev, "failed to get Rx Max Link Rate\n"); 426 return -ENODEV; 427 } 428 429 if (dp->link_train.lane_count == 0) { 430 dev_err(dp->dev, "failed to get Rx Max Lane Count\n"); 431 return -ENODEV; 432 } 433 434 /* Setup TX lane count & rate */ 435 if (dp->link_train.lane_count > max_lane) 436 dp->link_train.lane_count = max_lane; 437 if (dp->link_train.link_rate > max_rate) 438 dp->link_train.link_rate = max_rate; 439 440 /* All DP analog module power up */ 441 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 442 443 return 0; 444 } 445 446 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 447 { 448 int retval = 0, training_finished = 0; 449 450 dp->link_train.lt_state = START; 451 452 /* Process here */ 453 while (!retval && !training_finished) { 454 switch (dp->link_train.lt_state) { 455 case START: 456 retval = analogix_dp_link_start(dp); 457 if (retval) 458 dev_err(dp->dev, "LT link start failed!\n"); 459 break; 460 case CLOCK_RECOVERY: 461 retval = analogix_dp_process_clock_recovery(dp); 462 if (retval) 463 dev_err(dp->dev, "LT CR failed!\n"); 464 break; 465 case EQUALIZER_TRAINING: 466 retval = analogix_dp_process_equalizer_training(dp); 467 if (retval) 468 dev_err(dp->dev, "LT EQ failed!\n"); 469 break; 470 case FINISHED: 471 training_finished = 1; 472 break; 473 case FAILED: 474 return -EREMOTEIO; 475 } 476 } 477 478 return retval; 479 } 480 481 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 482 u32 count, u32 bwtype) 483 { 484 int ret; 485 486 ret = analogix_dp_init_training(dp, count, bwtype); 487 if (ret < 0) { 488 dev_err(dp->dev, "failed to init training\n"); 489 return ret; 490 } 491 492 ret = analogix_dp_sw_link_training(dp); 493 if (ret < 0) { 494 dev_err(dp->dev, "failed to do sw link training\n"); 495 return ret; 496 } 497 498 return 0; 499 } 500 501 static int analogix_dp_config_video(struct analogix_dp_device *dp) 502 { 503 int timeout_loop = 0; 504 int done_count = 0; 505 506 analogix_dp_config_video_slave_mode(dp); 507 508 analogix_dp_set_video_color_format(dp); 509 510 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 511 dev_err(dp->dev, "PLL is not locked yet.\n"); 512 return -EINVAL; 513 } 514 515 for (;;) { 516 timeout_loop++; 517 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 518 break; 519 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 520 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 521 return -ETIMEDOUT; 522 } 523 524 udelay(2); 525 } 526 527 /* Set to use the register calculated M/N video */ 528 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 529 530 /* For video bist, Video timing must be generated by register */ 531 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 532 533 /* Disable video mute */ 534 analogix_dp_enable_video_mute(dp, 0); 535 536 /* Configure video slave mode */ 537 analogix_dp_enable_video_master(dp, 0); 538 539 /* Enable video input */ 540 analogix_dp_start_video(dp); 541 542 timeout_loop = 0; 543 544 for (;;) { 545 timeout_loop++; 546 if (analogix_dp_is_video_stream_on(dp) == 0) { 547 done_count++; 548 if (done_count > 10) 549 break; 550 } else if (done_count) { 551 done_count = 0; 552 } 553 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 554 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 555 return -ETIMEDOUT; 556 } 557 558 udelay(1001); 559 } 560 561 return 0; 562 } 563 564 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 565 bool enable) 566 { 567 u8 data; 568 569 if (enable) { 570 analogix_dp_enable_scrambling(dp); 571 572 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 573 &data); 574 analogix_dp_write_byte_to_dpcd(dp, 575 DP_TRAINING_PATTERN_SET, 576 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 577 } else { 578 analogix_dp_disable_scrambling(dp); 579 580 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 581 &data); 582 analogix_dp_write_byte_to_dpcd(dp, 583 DP_TRAINING_PATTERN_SET, 584 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 585 } 586 } 587 588 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 589 { 590 analogix_dp_reset(dp); 591 592 analogix_dp_swreset(dp); 593 594 analogix_dp_init_analog_param(dp); 595 analogix_dp_init_interrupt(dp); 596 597 /* SW defined function Normal operation */ 598 analogix_dp_enable_sw_function(dp); 599 600 analogix_dp_config_interrupt(dp); 601 analogix_dp_init_analog_func(dp); 602 603 analogix_dp_init_hpd(dp); 604 analogix_dp_init_aux(dp); 605 } 606 607 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 608 { 609 int i; 610 unsigned char sum = 0; 611 612 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 613 sum = sum + edid_data[i]; 614 615 return sum; 616 } 617 618 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 619 { 620 unsigned char *edid = dp->edid; 621 unsigned int extend_block = 0; 622 unsigned char test_vector; 623 int retval; 624 625 /* 626 * EDID device address is 0x50. 627 * However, if necessary, you must have set upper address 628 * into E-EDID in I2C device, 0x30. 629 */ 630 631 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 632 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 633 EDID_EXTENSION_FLAG, 634 &extend_block); 635 if (retval) 636 return retval; 637 638 if (extend_block > 0) { 639 debug("EDID data includes a single extension!\n"); 640 641 /* Read EDID data */ 642 retval = analogix_dp_read_bytes_from_i2c(dp, 643 I2C_EDID_DEVICE_ADDR, 644 EDID_HEADER_PATTERN, 645 EDID_BLOCK_LENGTH, 646 &edid[EDID_HEADER_PATTERN]); 647 if (retval < 0) 648 return retval; 649 650 if (analogix_dp_calc_edid_check_sum(edid)) 651 return -EINVAL; 652 653 /* Read additional EDID data */ 654 retval = analogix_dp_read_bytes_from_i2c(dp, 655 I2C_EDID_DEVICE_ADDR, 656 EDID_BLOCK_LENGTH, 657 EDID_BLOCK_LENGTH, 658 &edid[EDID_BLOCK_LENGTH]); 659 if (retval < 0) 660 return retval; 661 662 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 663 return -EINVAL; 664 665 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 666 &test_vector); 667 if (test_vector & DP_TEST_LINK_EDID_READ) { 668 analogix_dp_write_byte_to_dpcd(dp, 669 DP_TEST_EDID_CHECKSUM, 670 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 671 analogix_dp_write_byte_to_dpcd(dp, 672 DP_TEST_RESPONSE, 673 DP_TEST_EDID_CHECKSUM_WRITE); 674 } 675 } else { 676 dev_info(dp->dev, 677 "EDID data does not include any extensions.\n"); 678 679 /* Read EDID data */ 680 retval = analogix_dp_read_bytes_from_i2c(dp, 681 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 682 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 683 if (retval < 0) 684 return retval; 685 686 if (analogix_dp_calc_edid_check_sum(edid)) 687 return -EINVAL; 688 689 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 690 &test_vector); 691 if (test_vector & DP_TEST_LINK_EDID_READ) { 692 analogix_dp_write_byte_to_dpcd(dp, 693 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 694 analogix_dp_write_byte_to_dpcd(dp, 695 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 696 } 697 } 698 699 return 0; 700 } 701 702 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 703 { 704 u8 buf[12]; 705 int i, try = 5; 706 int retval; 707 708 retry: 709 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 710 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 711 712 if (retval && try--) { 713 mdelay(10); 714 goto retry; 715 } 716 717 if (retval) 718 return retval; 719 720 /* Read EDID */ 721 for (i = 0; i < 3; i++) { 722 retval = analogix_dp_read_edid(dp); 723 if (!retval) 724 break; 725 } 726 727 return retval; 728 } 729 730 static int analogix_dp_connector_init(struct display_state *state) 731 { 732 struct connector_state *conn_state = &state->conn_state; 733 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 734 735 conn_state->type = DRM_MODE_CONNECTOR_eDP; 736 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 737 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 738 739 /* eDP software reset request */ 740 reset_assert(&dp->reset); 741 udelay(1); 742 reset_deassert(&dp->reset); 743 744 analogix_dp_init_dp(dp); 745 746 return 0; 747 } 748 749 static int analogix_dp_connector_get_edid(struct display_state *state) 750 { 751 struct connector_state *conn_state = &state->conn_state; 752 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 753 int ret; 754 755 ret = analogix_dp_handle_edid(dp); 756 if (ret) { 757 dev_err(dp->dev, "failed to get edid\n"); 758 return ret; 759 } 760 761 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 762 763 return 0; 764 } 765 766 static int analogix_dp_connector_enable(struct display_state *state) 767 { 768 struct connector_state *conn_state = &state->conn_state; 769 struct crtc_state *crtc_state = &state->crtc_state; 770 const struct rockchip_connector *connector = conn_state->connector; 771 const struct rockchip_dp_chip_data *pdata = connector->data; 772 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 773 struct video_info *video = &dp->video_info; 774 u32 val; 775 int ret; 776 777 if (pdata->has_vop_sel) { 778 if (crtc_state->crtc_id) 779 val = pdata->lcdsel_lit; 780 else 781 val = pdata->lcdsel_big; 782 783 writel(val, dp->grf + pdata->lcdsel_grf_reg); 784 } 785 786 switch (conn_state->bpc) { 787 case 12: 788 video->color_depth = COLOR_12; 789 break; 790 case 10: 791 video->color_depth = COLOR_10; 792 break; 793 case 6: 794 video->color_depth = COLOR_6; 795 break; 796 case 8: 797 default: 798 video->color_depth = COLOR_8; 799 break; 800 } 801 802 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 803 dp->video_info.max_link_rate); 804 if (ret) { 805 dev_err(dp->dev, "unable to do link train\n"); 806 return ret; 807 } 808 809 analogix_dp_enable_scramble(dp, 1); 810 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 811 analogix_dp_enable_enhanced_mode(dp, 1); 812 813 analogix_dp_init_video(dp); 814 ret = analogix_dp_config_video(dp); 815 if (ret) { 816 dev_err(dp->dev, "unable to config video\n"); 817 return ret; 818 } 819 820 return 0; 821 } 822 823 static int analogix_dp_connector_disable(struct display_state *state) 824 { 825 /* TODO */ 826 827 return 0; 828 } 829 830 static int analogix_dp_connector_detect(struct display_state *state) 831 { 832 struct connector_state *conn_state = &state->conn_state; 833 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 834 835 return analogix_dp_detect(dp); 836 } 837 838 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 839 .init = analogix_dp_connector_init, 840 .get_edid = analogix_dp_connector_get_edid, 841 .enable = analogix_dp_connector_enable, 842 .disable = analogix_dp_connector_disable, 843 .detect = analogix_dp_connector_detect, 844 }; 845 846 static int analogix_dp_probe(struct udevice *dev) 847 { 848 struct analogix_dp_device *dp = dev_get_priv(dev); 849 const struct rockchip_connector *connector = 850 (const struct rockchip_connector *)dev_get_driver_data(dev); 851 const struct rockchip_dp_chip_data *pdata = connector->data; 852 int ret; 853 854 dp->reg_base = dev_read_addr_ptr(dev); 855 dp->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 856 if (IS_ERR(dp->grf)) 857 return PTR_ERR(dp->grf); 858 859 ret = reset_get_by_name(dev, "dp", &dp->reset); 860 if (ret) { 861 dev_err(dev, "failed to get reset control: %d\n", ret); 862 return ret; 863 } 864 865 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 866 GPIOD_IS_IN); 867 if (ret && ret != -ENOENT) { 868 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 869 return ret; 870 } 871 872 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 873 874 dp->plat_data.dev_type = ROCKCHIP_DP; 875 dp->plat_data.subdev_type = pdata->chip_type; 876 /* 877 * Like Rockchip DisplayPort TRM indicate that "Main link 878 * containing 4 physical lanes of 2.7/1.62 Gbps/lane". 879 */ 880 dp->video_info.max_link_rate = 0x0A; 881 dp->video_info.max_lane_count = 0x04; 882 883 dp->dev = dev; 884 885 return 0; 886 } 887 888 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 889 .lcdsel_grf_reg = 0x025c, 890 .lcdsel_big = 0 | BIT(21), 891 .lcdsel_lit = BIT(5) | BIT(21), 892 .chip_type = RK3288_DP, 893 .has_vop_sel = true, 894 }; 895 896 static const struct rockchip_connector rk3288_edp_driver_data = { 897 .funcs = &analogix_dp_connector_funcs, 898 .data = &rk3288_edp_platform_data, 899 }; 900 901 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 902 .chip_type = RK3368_EDP, 903 .has_vop_sel = false, 904 }; 905 906 static const struct rockchip_connector rk3368_edp_driver_data = { 907 .funcs = &analogix_dp_connector_funcs, 908 .data = &rk3368_edp_platform_data, 909 }; 910 911 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 912 .lcdsel_grf_reg = 0x6250, 913 .lcdsel_big = 0 | BIT(21), 914 .lcdsel_lit = BIT(5) | BIT(21), 915 .chip_type = RK3399_EDP, 916 .has_vop_sel = true, 917 }; 918 919 static const struct rockchip_connector rk3399_edp_driver_data = { 920 .funcs = &analogix_dp_connector_funcs, 921 .data = &rk3399_edp_platform_data, 922 }; 923 924 static const struct udevice_id analogix_dp_ids[] = { 925 { 926 .compatible = "rockchip,rk3288-dp", 927 .data = (ulong)&rk3288_edp_driver_data, 928 }, { 929 .compatible = "rockchip,rk3368-edp", 930 .data = (ulong)&rk3368_edp_driver_data, 931 }, { 932 .compatible = "rockchip,rk3399-edp", 933 .data = (ulong)&rk3399_edp_driver_data, 934 }, 935 {} 936 }; 937 938 U_BOOT_DRIVER(analogix_dp) = { 939 .name = "analogix_dp", 940 .id = UCLASS_DISPLAY, 941 .of_match = analogix_dp_ids, 942 .probe = analogix_dp_probe, 943 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 944 }; 945