1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/bitfield.h> 17 #include <linux/list.h> 18 #include <linux/media-bus-format.h> 19 #include <syscon.h> 20 #include <asm/arch-rockchip/clock.h> 21 #include <asm/gpio.h> 22 23 #include "rockchip_display.h" 24 #include "rockchip_crtc.h" 25 #include "rockchip_connector.h" 26 #include "analogix_dp.h" 27 28 #define RK3588_GRF_VO1_CON0 0x0000 29 #define EDP_MODE BIT(0) 30 #define RK3588_GRF_VO1_CON1 0x0004 31 32 /** 33 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 34 * @lcdsel_grf_reg: grf register offset of lcdc select 35 * @lcdsel_big: reg value of selecting vop big for eDP 36 * @lcdsel_lit: reg value of selecting vop little for eDP 37 * @chip_type: specific chip type 38 * @ssc: check if SSC is supported by source 39 * @max_link_rate: max supported link rate 40 * @max_lane_count: max supported lane count 41 * @format_yuv: check if yuv color format is supported 42 * @max_bpc: max supported bpc which set to 8 by default 43 */ 44 struct rockchip_dp_chip_data { 45 u32 lcdsel_grf_reg; 46 u32 lcdsel_big; 47 u32 lcdsel_lit; 48 u32 chip_type; 49 bool ssc; 50 51 u32 max_link_rate; 52 u32 max_lane_count; 53 bool format_yuv; 54 u8 max_bpc; 55 }; 56 57 static const struct analogix_dp_output_format possible_output_fmts[] = { 58 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 10 }, 59 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 8 }, 60 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 6 }, 61 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 10 }, 62 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 8}, 63 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 10 }, 64 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 8 }, 65 }; 66 67 static u8 analogix_dp_get_output_bpp(const struct analogix_dp_output_format *fmt) 68 { 69 switch (fmt->color_format) { 70 case DRM_COLOR_FORMAT_YCRCB422: 71 return fmt->bpc * 2; 72 case DRM_COLOR_FORMAT_RGB444: 73 case DRM_COLOR_FORMAT_YCRCB444: 74 default: 75 return fmt->bpc * 3; 76 } 77 } 78 79 static int 80 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 81 bool enable) 82 { 83 u8 data; 84 int ret; 85 86 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); 87 if (ret != 1) 88 return ret; 89 90 if (enable) 91 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 92 DP_LANE_COUNT_ENHANCED_FRAME_EN | 93 DPCD_LANE_COUNT_SET(data)); 94 else 95 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 96 DPCD_LANE_COUNT_SET(data)); 97 98 return ret < 0 ? ret : 0; 99 } 100 101 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 102 { 103 bool enhanced_frame_en; 104 u8 data; 105 int ret; 106 107 enhanced_frame_en = drm_dp_enhanced_frame_cap(dp->dpcd); 108 109 ret = analogix_dp_enable_rx_to_enhanced_mode(dp, enhanced_frame_en); 110 if (ret < 0) 111 return ret; 112 113 if (!enhanced_frame_en) { 114 /* 115 * As the Table 3-4 in eDP v1.2 spec: 116 * DPCD 0000Dh: 117 * Bit 1 = FRAMING_CHANGE_CAPABLE 118 * A setting of 1 indicates that this is an eDP device that 119 * uses only Enhanced Framing, independently of the setting by 120 * the source of ENHANCED_FRAME_EN 121 * 122 * And as the Table 3-3 in eDP v1.4 spec: 123 * DPCD 0000Dh: 124 * Bit 1 = RESERVED for eDP 125 * New to eDP v1.4.(Read all 0s) 126 */ 127 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_CONFIGURATION_CAP, 128 &data); 129 if (ret < 0) 130 return ret; 131 132 enhanced_frame_en = !!(data & DP_FRAMING_CHANGE_CAP); 133 } 134 135 analogix_dp_enable_enhanced_mode(dp, enhanced_frame_en); 136 137 return 0; 138 } 139 140 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 141 { 142 int ret; 143 144 analogix_dp_set_training_pattern(dp, DP_NONE); 145 146 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 147 DP_TRAINING_PATTERN_DISABLE); 148 149 return ret < 0 ? ret : 0; 150 } 151 152 static int analogix_dp_link_start(struct analogix_dp_device *dp) 153 { 154 u8 buf[4]; 155 int lane, lane_count, retval; 156 157 lane_count = dp->link_train.lane_count; 158 159 dp->link_train.lt_state = CLOCK_RECOVERY; 160 dp->link_train.eq_loop = 0; 161 162 for (lane = 0; lane < lane_count; lane++) 163 dp->link_train.cr_loop[lane] = 0; 164 165 /* Set link rate and count as you want to establish */ 166 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 167 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 168 169 if (dp->nr_link_rate_table) { 170 /* Setup DP_LINK_RATE_SET for eDP 1.4 and later */ 171 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, dp->link_train.lane_count); 172 drm_dp_dpcd_writeb(&dp->aux, DP_LINK_RATE_SET, dp->link_rate_select); 173 } else { 174 /* Setup DP_LINK_BW_SET for eDP 1.3 and earlier */ 175 buf[0] = dp->link_train.link_rate; 176 buf[1] = dp->link_train.lane_count; 177 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2); 178 if (retval < 0) 179 return retval; 180 } 181 182 /* Spread AMP if required, enable 8b/10b coding */ 183 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 184 buf[1] = DP_SET_ANSI_8B10B; 185 retval = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 2); 186 if (retval < 0) 187 return retval; 188 189 /* set enhanced mode if available */ 190 retval = analogix_dp_set_enhanced_mode(dp); 191 if (retval < 0) { 192 dev_err(dp->dev, "failed to set enhance mode\n"); 193 return retval; 194 } 195 196 /* Set TX voltage-swing and pre-emphasis to minimum */ 197 for (lane = 0; lane < lane_count; lane++) 198 dp->link_train.training_lane[lane] = 199 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 200 DP_TRAIN_PRE_EMPH_LEVEL_0; 201 analogix_dp_set_lane_link_training(dp); 202 203 /* Set training pattern 1 */ 204 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 205 206 /* Set RX training pattern */ 207 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 208 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 209 if (retval < 0) 210 return retval; 211 212 for (lane = 0; lane < lane_count; lane++) 213 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 214 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 215 216 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, 217 lane_count); 218 if (retval < 0) 219 return retval; 220 221 return 0; 222 } 223 224 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 225 { 226 int shift = (lane & 1) * 4; 227 u8 link_value = link_status[lane >> 1]; 228 229 return (link_value >> shift) & 0xf; 230 } 231 232 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 233 { 234 int lane; 235 u8 lane_status; 236 237 for (lane = 0; lane < lane_count; lane++) { 238 lane_status = analogix_dp_get_lane_status(link_status, lane); 239 if ((lane_status & DP_LANE_CR_DONE) == 0) 240 return -EINVAL; 241 } 242 return 0; 243 } 244 245 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 246 int lane_count) 247 { 248 int lane; 249 u8 lane_status; 250 251 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 252 return -EINVAL; 253 254 for (lane = 0; lane < lane_count; lane++) { 255 lane_status = analogix_dp_get_lane_status(link_status, lane); 256 lane_status &= DP_CHANNEL_EQ_BITS; 257 if (lane_status != DP_CHANNEL_EQ_BITS) 258 return -EINVAL; 259 } 260 261 return 0; 262 } 263 264 static unsigned char 265 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 266 { 267 int shift = (lane & 1) * 4; 268 u8 link_value = adjust_request[lane >> 1]; 269 270 return (link_value >> shift) & 0x3; 271 } 272 273 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 274 u8 adjust_request[2], 275 int lane) 276 { 277 int shift = (lane & 1) * 4; 278 u8 link_value = adjust_request[lane >> 1]; 279 280 return ((link_value >> shift) & 0xc) >> 2; 281 } 282 283 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 284 { 285 analogix_dp_training_pattern_dis(dp); 286 analogix_dp_set_enhanced_mode(dp); 287 288 dp->link_train.lt_state = FAILED; 289 } 290 291 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 292 u8 adjust_request[2]) 293 { 294 int lane, lane_count; 295 u8 voltage_swing, pre_emphasis, training_lane; 296 297 lane_count = dp->link_train.lane_count; 298 for (lane = 0; lane < lane_count; lane++) { 299 voltage_swing = analogix_dp_get_adjust_request_voltage( 300 adjust_request, lane); 301 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 302 adjust_request, lane); 303 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 304 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 305 306 if (voltage_swing == VOLTAGE_LEVEL_3) 307 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 308 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 309 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 310 311 dp->link_train.training_lane[lane] = training_lane; 312 } 313 } 314 315 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp) 316 { 317 bool source_tps3_supported, sink_tps3_supported; 318 u8 dpcd = 0; 319 320 source_tps3_supported = 321 dp->video_info.max_link_rate == DP_LINK_BW_5_4; 322 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &dpcd); 323 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; 324 325 return source_tps3_supported && sink_tps3_supported; 326 } 327 328 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 329 { 330 int lane, lane_count, retval; 331 u8 voltage_swing, pre_emphasis, training_lane; 332 u8 link_status[2], adjust_request[2]; 333 u8 training_pattern = TRAINING_PTN2; 334 335 drm_dp_link_train_clock_recovery_delay(dp->dpcd); 336 337 lane_count = dp->link_train.lane_count; 338 339 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 340 if (retval < 0) 341 return retval; 342 343 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 344 if (analogix_dp_tps3_supported(dp)) 345 training_pattern = TRAINING_PTN3; 346 347 /* set training pattern for EQ */ 348 analogix_dp_set_training_pattern(dp, training_pattern); 349 350 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 351 DP_LINK_SCRAMBLING_DISABLE | 352 (training_pattern == TRAINING_PTN3 ? 353 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); 354 if (retval < 0) 355 return retval; 356 357 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 358 dp->link_train.lt_state = EQUALIZER_TRAINING; 359 360 return 0; 361 } else { 362 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 363 adjust_request, 2); 364 if (retval < 0) 365 return retval; 366 367 for (lane = 0; lane < lane_count; lane++) { 368 training_lane = analogix_dp_get_lane_link_training( 369 dp, lane); 370 voltage_swing = analogix_dp_get_adjust_request_voltage( 371 adjust_request, lane); 372 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 373 adjust_request, lane); 374 375 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 376 voltage_swing && 377 DPCD_PRE_EMPHASIS_GET(training_lane) == 378 pre_emphasis) 379 dp->link_train.cr_loop[lane]++; 380 381 /* 382 * In DP spec 1.3, Condition of CR fail are 383 * outlined in section 3.5.1.2.2.1, figure 3-20: 384 * 385 * 1. Maximum Voltage Swing reached 386 * 2. Same Voltage five times 387 */ 388 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 389 DPCD_VOLTAGE_SWING_GET(training_lane) == VOLTAGE_LEVEL_3) { 390 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 391 dp->link_train.cr_loop[lane], 392 voltage_swing, pre_emphasis); 393 analogix_dp_reduce_link_rate(dp); 394 return -EIO; 395 } 396 } 397 } 398 399 analogix_dp_get_adjust_training_lane(dp, adjust_request); 400 analogix_dp_set_lane_link_training(dp); 401 402 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 403 dp->link_train.training_lane, lane_count); 404 if (retval < 0) 405 return retval; 406 407 return 0; 408 } 409 410 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 411 { 412 int lane_count, retval; 413 u32 reg; 414 u8 link_align, link_status[2], adjust_request[2]; 415 416 drm_dp_link_train_channel_eq_delay(dp->dpcd); 417 418 lane_count = dp->link_train.lane_count; 419 420 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 421 if (retval < 0) 422 return retval; 423 424 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 425 analogix_dp_reduce_link_rate(dp); 426 return -EIO; 427 } 428 429 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 430 if (retval < 0) 431 return retval; 432 433 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 434 /* traing pattern Set to Normal */ 435 retval = analogix_dp_training_pattern_dis(dp); 436 if (retval < 0) 437 return retval; 438 439 printf("Link Training success!\n"); 440 441 analogix_dp_get_link_bandwidth(dp, ®); 442 dp->link_train.link_rate = reg; 443 analogix_dp_get_lane_count(dp, ®); 444 dp->link_train.lane_count = reg; 445 446 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 447 dp->link_train.link_rate, dp->link_train.lane_count); 448 449 dp->link_train.lt_state = FINISHED; 450 451 return 0; 452 } 453 454 /* not all locked */ 455 dp->link_train.eq_loop++; 456 457 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 458 dev_dbg(dp->dev, "EQ Max loop\n"); 459 analogix_dp_reduce_link_rate(dp); 460 return -EIO; 461 } 462 463 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, adjust_request, 2); 464 if (retval < 0) 465 return retval; 466 467 analogix_dp_get_adjust_training_lane(dp, adjust_request); 468 analogix_dp_set_lane_link_training(dp); 469 470 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 471 dp->link_train.training_lane, lane_count); 472 if (retval < 0) 473 return retval; 474 475 return 0; 476 } 477 478 static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp, 479 const struct drm_display_mode *mode, u32 bpp, 480 unsigned int rate, unsigned int lanes) 481 { 482 u32 max_bw, req_bw; 483 484 req_bw = mode->clock * bpp / 8; 485 max_bw = lanes * rate; 486 if (req_bw > max_bw) 487 return false; 488 489 return true; 490 } 491 492 static bool analogix_dp_link_config_validate(u8 link_rate, u8 lane_count) 493 { 494 switch (link_rate) { 495 case DP_LINK_BW_1_62: 496 case DP_LINK_BW_2_7: 497 case DP_LINK_BW_5_4: 498 /* Supported link rate in eDP 1.4 */ 499 case EDP_LINK_BW_2_16: 500 case EDP_LINK_BW_2_43: 501 case EDP_LINK_BW_3_24: 502 case EDP_LINK_BW_4_32: 503 break; 504 default: 505 return false; 506 } 507 508 switch (lane_count) { 509 case LANE_COUNT1: 510 case LANE_COUNT2: 511 case LANE_COUNT4: 512 break; 513 default: 514 return false; 515 } 516 517 return true; 518 } 519 520 static int analogix_dp_select_link_rate_from_table(struct analogix_dp_device *dp) 521 { 522 int i; 523 u8 bw_code; 524 u32 max_link_rate = drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate); 525 526 for (i = 0; i < dp->nr_link_rate_table; i++) { 527 bw_code = drm_dp_link_rate_to_bw_code(dp->link_rate_table[i]); 528 529 if (!analogix_dp_bandwidth_ok(dp, &dp->video_info.mode, 530 analogix_dp_get_output_bpp(dp->output_fmt), 531 dp->link_rate_table[i], dp->link_train.lane_count)) 532 continue; 533 534 if (dp->link_rate_table[i] <= max_link_rate && 535 analogix_dp_link_config_validate(bw_code, dp->link_train.lane_count)) { 536 dp->link_rate_select = i; 537 return bw_code; 538 } 539 } 540 541 return 0; 542 } 543 544 static int analogix_dp_select_rx_bandwidth(struct analogix_dp_device *dp) 545 { 546 if (dp->nr_link_rate_table) 547 /* 548 * Select the smallest one among link rates which meet 549 * the bandwidth requirement for eDP 1.4 and later. 550 */ 551 dp->link_train.link_rate = analogix_dp_select_link_rate_from_table(dp); 552 else 553 /* 554 * Select the smaller one between rx DP_MAX_LINK_RATE 555 * and the max link rate supported by the platform. 556 */ 557 dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate, 558 dp->video_info.max_link_rate); 559 if (!dp->link_train.link_rate) 560 return -EINVAL; 561 562 return 0; 563 } 564 565 static int analogix_dp_init_link_rate_table(struct analogix_dp_device *dp) 566 { 567 u8 link_rate_table[DP_MAX_SUPPORTED_RATES * 2]; 568 int i; 569 int ret; 570 571 ret = drm_dp_dpcd_read(&dp->aux, DP_SUPPORTED_LINK_RATES, link_rate_table, 572 sizeof(link_rate_table)); 573 if (ret < 0) 574 return ret; 575 576 for (i = 0; i < ARRAY_SIZE(link_rate_table) / 2; i++) { 577 int val = link_rate_table[2 * i] | link_rate_table[2 * i + 1] << 8; 578 579 if (val == 0) 580 break; 581 582 /* Convert to the link_rate as drm_dp_bw_code_to_link_rate() */ 583 dp->link_rate_table[i] = (val * 20); 584 } 585 dp->nr_link_rate_table = i; 586 587 return 0; 588 } 589 590 static int analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 591 u8 *bandwidth) 592 { 593 u8 data; 594 int ret; 595 596 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_DPCD_REV, &data); 597 if (ret == 1 && data >= DP_EDP_14) { 598 u32 max_link_rate; 599 600 /* As the Table 4-23 in eDP 1.4 spec, the link rate table is required */ 601 if (!dp->nr_link_rate_table) { 602 dev_info(dp->dev, "eDP version: 0x%02x supports link rate table\n", 603 data); 604 605 if (analogix_dp_init_link_rate_table(dp)) 606 dev_err(dp->dev, "failed to read link rate table: %d\n", 607 ret); 608 } 609 max_link_rate = dp->link_rate_table[dp->nr_link_rate_table - 1]; 610 *bandwidth = drm_dp_link_rate_to_bw_code(max_link_rate); 611 } else { 612 /* 613 * For DP rev.1.1, Maximum link rate of Main Link lanes 614 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 615 * For DP rev.1.2, Maximum link rate of Main Link lanes 616 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 617 */ 618 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data); 619 if (ret < 0) 620 return ret; 621 622 *bandwidth = data; 623 } 624 625 return 0; 626 } 627 628 static int analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 629 u8 *lane_count) 630 { 631 u8 data; 632 int ret; 633 634 /* 635 * For DP rev.1.1, Maximum number of Main Link lanes 636 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 637 */ 638 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 639 if (ret < 0) 640 return ret; 641 642 *lane_count = DPCD_MAX_LANE_COUNT(data); 643 644 return 0; 645 } 646 647 static int analogix_dp_init_training(struct analogix_dp_device *dp, 648 enum link_lane_count_type max_lane, 649 int max_rate) 650 { 651 u8 dpcd; 652 653 /* 654 * MACRO_RST must be applied after the PLL_LOCK to avoid 655 * the DP inter pair skew issue for at least 10 us 656 */ 657 analogix_dp_reset_macro(dp); 658 659 /* Setup TX lane count */ 660 dp->link_train.lane_count = min_t(u32, dp->link_train.lane_count, max_lane); 661 662 /* Setup TX lane rate */ 663 if (analogix_dp_select_rx_bandwidth(dp)) { 664 dev_err(dp->dev, "Select rx bandwidth failed\n"); 665 return -EINVAL; 666 } 667 668 drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &dpcd); 669 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 670 671 /* All DP analog module power up */ 672 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 673 674 return 0; 675 } 676 677 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 678 { 679 int retval = 0, training_finished = 0; 680 681 dp->link_train.lt_state = START; 682 683 /* Process here */ 684 while (!retval && !training_finished) { 685 switch (dp->link_train.lt_state) { 686 case START: 687 retval = analogix_dp_link_start(dp); 688 if (retval) 689 dev_err(dp->dev, "LT link start failed!\n"); 690 break; 691 case CLOCK_RECOVERY: 692 retval = analogix_dp_process_clock_recovery(dp); 693 if (retval) 694 dev_err(dp->dev, "LT CR failed!\n"); 695 break; 696 case EQUALIZER_TRAINING: 697 retval = analogix_dp_process_equalizer_training(dp); 698 if (retval) 699 dev_err(dp->dev, "LT EQ failed!\n"); 700 break; 701 case FINISHED: 702 training_finished = 1; 703 break; 704 case FAILED: 705 return -EREMOTEIO; 706 } 707 } 708 709 return retval; 710 } 711 712 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 713 u32 count, u32 bwtype) 714 { 715 int i, ret; 716 717 for (i = 0; i < 5; i++) { 718 ret = analogix_dp_init_training(dp, count, bwtype); 719 if (ret < 0) { 720 dev_err(dp->dev, "failed to init training\n"); 721 return ret; 722 } 723 724 ret = analogix_dp_sw_link_training(dp); 725 if (!ret) 726 break; 727 } 728 729 return ret; 730 } 731 732 static int analogix_dp_config_video(struct analogix_dp_device *dp) 733 { 734 int timeout_loop = 0; 735 int done_count = 0; 736 737 analogix_dp_config_video_slave_mode(dp); 738 739 analogix_dp_set_video_color_format(dp); 740 741 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 742 dev_err(dp->dev, "PLL is not locked yet.\n"); 743 return -EINVAL; 744 } 745 746 for (;;) { 747 timeout_loop++; 748 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 749 break; 750 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 751 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 752 return -ETIMEDOUT; 753 } 754 755 udelay(2); 756 } 757 758 /* Set to use the register calculated M/N video */ 759 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 760 761 /* For video bist, Video timing must be generated by register */ 762 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_REGISTER); 763 764 /* Disable video mute */ 765 analogix_dp_enable_video_mute(dp, 0); 766 767 /* Configure video slave mode */ 768 analogix_dp_enable_video_master(dp, 0); 769 770 /* Enable video input */ 771 analogix_dp_start_video(dp); 772 773 timeout_loop = 0; 774 775 for (;;) { 776 timeout_loop++; 777 if (analogix_dp_is_video_stream_on(dp) == 0) { 778 done_count++; 779 if (done_count > 10) 780 break; 781 } else if (done_count) { 782 done_count = 0; 783 } 784 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 785 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 786 return -ETIMEDOUT; 787 } 788 789 udelay(1001); 790 } 791 792 return 0; 793 } 794 795 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp, 796 bool enable) 797 { 798 u8 data; 799 int ret; 800 801 if (enable) { 802 analogix_dp_enable_scrambling(dp); 803 804 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, 805 &data); 806 if (ret != 1) 807 return ret; 808 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 809 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 810 } else { 811 analogix_dp_disable_scrambling(dp); 812 813 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, 814 &data); 815 if (ret != 1) 816 return ret; 817 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 818 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 819 } 820 return ret < 0 ? ret : 0; 821 } 822 823 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 824 { 825 analogix_dp_reset(dp); 826 827 analogix_dp_swreset(dp); 828 829 analogix_dp_init_analog_param(dp); 830 analogix_dp_init_interrupt(dp); 831 832 /* SW defined function Normal operation */ 833 analogix_dp_enable_sw_function(dp); 834 835 analogix_dp_config_interrupt(dp); 836 analogix_dp_init_analog_func(dp); 837 838 analogix_dp_init_hpd(dp); 839 analogix_dp_init_aux(dp); 840 } 841 842 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 843 { 844 int i; 845 unsigned char sum = 0; 846 847 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 848 sum = sum + edid_data[i]; 849 850 return sum; 851 } 852 853 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 854 { 855 unsigned char *edid = dp->edid; 856 unsigned int extend_block = 0; 857 unsigned char test_vector; 858 int retval; 859 860 /* 861 * EDID device address is 0x50. 862 * However, if necessary, you must have set upper address 863 * into E-EDID in I2C device, 0x30. 864 */ 865 866 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 867 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 868 EDID_EXTENSION_FLAG, 869 &extend_block); 870 if (retval) 871 return retval; 872 873 if (extend_block > 0) { 874 debug("EDID data includes a single extension!\n"); 875 876 /* Read EDID data */ 877 retval = analogix_dp_read_bytes_from_i2c(dp, 878 I2C_EDID_DEVICE_ADDR, 879 EDID_HEADER_PATTERN, 880 EDID_BLOCK_LENGTH, 881 &edid[EDID_HEADER_PATTERN]); 882 if (retval < 0) 883 return retval; 884 885 if (analogix_dp_calc_edid_check_sum(edid)) 886 return -EINVAL; 887 888 /* Read additional EDID data */ 889 retval = analogix_dp_read_bytes_from_i2c(dp, 890 I2C_EDID_DEVICE_ADDR, 891 EDID_BLOCK_LENGTH, 892 EDID_BLOCK_LENGTH, 893 &edid[EDID_BLOCK_LENGTH]); 894 if (retval < 0) 895 return retval; 896 897 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 898 return -EINVAL; 899 900 drm_dp_dpcd_readb(&dp->aux, DP_TEST_REQUEST, &test_vector); 901 if (test_vector & DP_TEST_LINK_EDID_READ) { 902 drm_dp_dpcd_writeb(&dp->aux, DP_TEST_EDID_CHECKSUM, 903 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 904 drm_dp_dpcd_writeb(&dp->aux, DP_TEST_RESPONSE, 905 DP_TEST_EDID_CHECKSUM_WRITE); 906 } 907 } else { 908 dev_info(dp->dev, 909 "EDID data does not include any extensions.\n"); 910 911 /* Read EDID data */ 912 retval = analogix_dp_read_bytes_from_i2c(dp, 913 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 914 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 915 if (retval < 0) 916 return retval; 917 918 if (analogix_dp_calc_edid_check_sum(edid)) 919 return -EINVAL; 920 921 drm_dp_dpcd_readb(&dp->aux, DP_TEST_REQUEST, &test_vector); 922 if (test_vector & DP_TEST_LINK_EDID_READ) { 923 drm_dp_dpcd_writeb(&dp->aux, DP_TEST_EDID_CHECKSUM, 924 edid[EDID_CHECKSUM]); 925 drm_dp_dpcd_writeb(&dp->aux, DP_TEST_RESPONSE, 926 DP_TEST_EDID_CHECKSUM_WRITE); 927 } 928 } 929 930 return 0; 931 } 932 933 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 934 { 935 u8 buf[12]; 936 int i, try = 5; 937 int retval; 938 939 retry: 940 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 941 retval = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, buf, 12); 942 if (retval < 0 && try--) { 943 mdelay(10); 944 goto retry; 945 } 946 947 if (retval) 948 return retval; 949 950 /* Read EDID */ 951 for (i = 0; i < 3; i++) { 952 retval = analogix_dp_read_edid(dp); 953 if (!retval) 954 break; 955 } 956 957 return retval; 958 } 959 960 static int analogix_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 961 { 962 struct connector_state *conn_state = &state->conn_state; 963 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 964 965 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; 966 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 967 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 968 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 969 970 reset_assert_bulk(&dp->resets); 971 udelay(1); 972 reset_deassert_bulk(&dp->resets); 973 974 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 975 generic_phy_set_mode(&dp->phy, PHY_MODE_DP); 976 generic_phy_power_on(&dp->phy); 977 analogix_dp_init_dp(dp); 978 979 return 0; 980 } 981 982 static int analogix_dp_connector_get_edid(struct rockchip_connector *conn, 983 struct display_state *state) 984 { 985 struct connector_state *conn_state = &state->conn_state; 986 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 987 int ret; 988 989 ret = analogix_dp_handle_edid(dp); 990 if (ret) { 991 dev_err(dp->dev, "failed to get edid\n"); 992 return ret; 993 } 994 995 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 996 997 return 0; 998 } 999 1000 static int analogix_dp_link_power_up(struct analogix_dp_device *dp) 1001 { 1002 u8 value; 1003 int ret; 1004 1005 if (dp->dpcd[DP_DPCD_REV] < 0x11) 1006 return 0; 1007 1008 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 1009 if (ret < 0) 1010 return ret; 1011 1012 value &= ~DP_SET_POWER_MASK; 1013 value |= DP_SET_POWER_D0; 1014 1015 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 1016 if (ret < 0) 1017 return ret; 1018 1019 mdelay(1); 1020 1021 return 0; 1022 } 1023 1024 static int analogix_dp_link_power_down(struct analogix_dp_device *dp) 1025 { 1026 u8 value; 1027 int ret; 1028 1029 if (dp->dpcd[DP_DPCD_REV] < 0x11) 1030 return 0; 1031 1032 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 1033 if (ret < 0) 1034 return ret; 1035 1036 value &= ~DP_SET_POWER_MASK; 1037 value |= DP_SET_POWER_D3; 1038 1039 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 1040 if (ret < 0) 1041 return ret; 1042 1043 return 0; 1044 } 1045 1046 static u32 analogix_dp_get_output_format(struct analogix_dp_device *dp, u32 bus_format) 1047 { 1048 unsigned int i; 1049 1050 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1051 const struct analogix_dp_output_format *fmt = &possible_output_fmts[i]; 1052 1053 if (fmt->bus_format == bus_format) 1054 break; 1055 } 1056 1057 if (i == ARRAY_SIZE(possible_output_fmts)) 1058 return 1; 1059 1060 return i; 1061 } 1062 1063 static u32 analogix_dp_get_output_format_by_edid(struct analogix_dp_device *dp, 1064 struct hdmi_edid_data *edid_data) 1065 { 1066 unsigned int i; 1067 1068 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1069 const struct analogix_dp_output_format *fmt = &possible_output_fmts[i]; 1070 1071 if (fmt->bpc > edid_data->display_info.bpc || fmt->bpc > dp->plat_data.max_bpc) 1072 continue; 1073 1074 if (!(edid_data->display_info.color_formats & fmt->color_format)) 1075 continue; 1076 1077 if (!analogix_dp_bandwidth_ok(dp, edid_data->preferred_mode, 1078 analogix_dp_get_output_bpp(fmt), 1079 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate), 1080 dp->link_train.lane_count)) 1081 continue; 1082 1083 break; 1084 } 1085 1086 if (i == ARRAY_SIZE(possible_output_fmts)) 1087 return 1; 1088 1089 return i; 1090 } 1091 1092 static int analogix_dp_connector_enable(struct rockchip_connector *conn, 1093 struct display_state *state) 1094 { 1095 struct connector_state *conn_state = &state->conn_state; 1096 struct crtc_state *crtc_state = &state->crtc_state; 1097 const struct rockchip_dp_chip_data *pdata = 1098 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1099 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1100 struct video_info *video = &dp->video_info; 1101 struct drm_display_mode mode; 1102 u32 fmt_id; 1103 u32 val; 1104 int ret; 1105 1106 drm_mode_copy(&video->mode, &conn_state->mode); 1107 1108 if (pdata->lcdsel_grf_reg) { 1109 if (crtc_state->crtc_id) 1110 val = pdata->lcdsel_lit; 1111 else 1112 val = pdata->lcdsel_big; 1113 1114 regmap_write(dp->grf, pdata->lcdsel_grf_reg, val); 1115 } 1116 1117 if (pdata->chip_type == RK3588_EDP) 1118 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 1119 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); 1120 1121 if (!dp->output_fmt) { 1122 fmt_id = analogix_dp_get_output_format(dp, conn_state->bus_format); 1123 dp->output_fmt = &possible_output_fmts[fmt_id]; 1124 } 1125 1126 switch (dp->output_fmt->bpc) { 1127 case 12: 1128 video->color_depth = COLOR_12; 1129 break; 1130 case 10: 1131 video->color_depth = COLOR_10; 1132 break; 1133 case 6: 1134 video->color_depth = COLOR_6; 1135 break; 1136 case 8: 1137 default: 1138 video->color_depth = COLOR_8; 1139 break; 1140 } 1141 if (dp->output_fmt->color_format == DRM_COLOR_FORMAT_YCRCB444) { 1142 video->color_space = COLOR_YCBCR444; 1143 video->ycbcr_coeff = COLOR_YCBCR709; 1144 } else if (dp->output_fmt->color_format == DRM_COLOR_FORMAT_YCRCB422) { 1145 video->color_space = COLOR_YCBCR422; 1146 video->ycbcr_coeff = COLOR_YCBCR709; 1147 } else { 1148 video->color_space = COLOR_RGB; 1149 video->ycbcr_coeff = COLOR_YCBCR601; 1150 } 1151 1152 ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd, DP_RECEIVER_CAP_SIZE); 1153 if (ret < 0) { 1154 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret); 1155 return ret; 1156 } 1157 1158 ret = analogix_dp_link_power_up(dp); 1159 if (ret) { 1160 dev_err(dp->dev, "failed to power up link: %d\n", ret); 1161 return ret; 1162 } 1163 1164 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 1165 dp->video_info.max_link_rate); 1166 if (ret) { 1167 dev_err(dp->dev, "unable to do link train\n"); 1168 return ret; 1169 } 1170 1171 ret = analogix_dp_enable_scramble(dp, 1); 1172 if (ret < 0) { 1173 dev_err(dp->dev, "can not enable scramble\n"); 1174 return ret; 1175 } 1176 1177 analogix_dp_init_video(dp); 1178 1179 drm_mode_copy(&mode, &conn_state->mode); 1180 if (conn->dual_channel_mode) 1181 drm_mode_convert_to_origin_mode(&mode); 1182 analogix_dp_set_video_format(dp, &mode); 1183 1184 if (dp->video_bist_enable) 1185 analogix_dp_video_bist_enable(dp); 1186 1187 ret = analogix_dp_config_video(dp); 1188 if (ret) { 1189 dev_err(dp->dev, "unable to config video\n"); 1190 return ret; 1191 } 1192 1193 return 0; 1194 } 1195 1196 static int analogix_dp_connector_disable(struct rockchip_connector *conn, 1197 struct display_state *state) 1198 { 1199 const struct rockchip_dp_chip_data *pdata = 1200 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1201 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1202 1203 if (!analogix_dp_get_plug_in_status(dp)) 1204 analogix_dp_link_power_down(dp); 1205 1206 if (pdata->chip_type == RK3588_EDP) 1207 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 1208 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 0)); 1209 1210 return 0; 1211 } 1212 1213 static int analogix_dp_connector_detect(struct rockchip_connector *conn, 1214 struct display_state *state) 1215 { 1216 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1217 int ret; 1218 1219 if (analogix_dp_detect(dp)) { 1220 /* Initialize by reading RX's DPCD */ 1221 ret = analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 1222 if (ret) { 1223 dev_err(dp->dev, "failed to read max link rate\n"); 1224 return 0; 1225 } 1226 1227 ret = analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 1228 if (ret) { 1229 dev_err(dp->dev, "failed to read max lane count\n"); 1230 return 0; 1231 } 1232 1233 return 1; 1234 } else { 1235 return 0; 1236 } 1237 } 1238 1239 static int analogix_dp_connector_mode_valid(struct rockchip_connector *conn, 1240 struct display_state *state) 1241 { 1242 struct connector_state *conn_state = &state->conn_state; 1243 struct videomode vm; 1244 1245 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1246 1247 if (!vm.hfront_porch || !vm.hback_porch || !vm.vfront_porch || !vm.vback_porch) { 1248 dev_err(dp->dev, "front porch or back porch can not be 0\n"); 1249 return MODE_BAD; 1250 } 1251 1252 return MODE_OK; 1253 } 1254 1255 static int analogix_dp_mode_valid(struct analogix_dp_device *dp, struct hdmi_edid_data *edid_data) 1256 { 1257 struct drm_display_info *di = &edid_data->display_info; 1258 u32 max_link_rate, max_lane_count; 1259 u32 min_bpp; 1260 int i; 1261 1262 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1263 min_bpp = 16; 1264 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1265 min_bpp = 18; 1266 else 1267 min_bpp = 24; 1268 1269 max_link_rate = min_t(u32, dp->video_info.max_link_rate, dp->link_train.link_rate); 1270 max_lane_count = min_t(u32, dp->video_info.max_lane_count, dp->link_train.lane_count); 1271 for (i = 0; i < edid_data->modes; i++) { 1272 if (!analogix_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, 1273 drm_dp_bw_code_to_link_rate(max_link_rate), 1274 max_lane_count)) 1275 edid_data->mode_buf[i].invalid = true; 1276 } 1277 1278 return 0; 1279 } 1280 1281 static int analogix_dp_connector_get_timing(struct rockchip_connector *conn, 1282 struct display_state *state) 1283 { 1284 struct connector_state *conn_state = &state->conn_state; 1285 const struct rockchip_dp_chip_data *pdata = 1286 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1287 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1288 struct drm_display_mode *mode = &conn_state->mode; 1289 struct hdmi_edid_data edid_data; 1290 struct drm_display_mode *mode_buf; 1291 struct vop_rect rect; 1292 u32 yuv_fmts_mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422; 1293 u32 fmt_id; 1294 int ret, i; 1295 1296 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1297 if (!mode_buf) 1298 return -ENOMEM; 1299 1300 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1301 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1302 edid_data.mode_buf = mode_buf; 1303 1304 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1305 if (!ret) 1306 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1307 1308 if (ret < 0) { 1309 printf("failed to get edid\n"); 1310 goto err; 1311 } 1312 1313 if (!pdata->format_yuv) { 1314 if (edid_data.display_info.color_formats & yuv_fmts_mask) { 1315 printf("Swapping display color format from YUV to RGB\n"); 1316 edid_data.display_info.color_formats &= ~yuv_fmts_mask; 1317 edid_data.display_info.color_formats |= DRM_COLOR_FORMAT_RGB444; 1318 } 1319 } 1320 1321 if (state->conn_state.secondary) { 1322 rect.width = state->crtc_state.max_output.width / 2; 1323 rect.height = state->crtc_state.max_output.height / 2; 1324 } else { 1325 rect.width = state->crtc_state.max_output.width; 1326 rect.height = state->crtc_state.max_output.height; 1327 } 1328 1329 drm_mode_max_resolution_filter(&edid_data, &rect); 1330 analogix_dp_mode_valid(dp, &edid_data); 1331 1332 if (!drm_mode_prune_invalid(&edid_data)) { 1333 printf("can't find valid dp mode\n"); 1334 ret = -EINVAL; 1335 goto err; 1336 } 1337 1338 for (i = 0; i < edid_data.modes; i++) 1339 edid_data.mode_buf[i].vrefresh = drm_mode_vrefresh(&edid_data.mode_buf[i]); 1340 1341 drm_mode_sort(&edid_data); 1342 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1343 1344 fmt_id = analogix_dp_get_output_format_by_edid(dp, &edid_data); 1345 dp->output_fmt = &possible_output_fmts[fmt_id]; 1346 1347 switch (dp->output_fmt->color_format) { 1348 case DRM_COLOR_FORMAT_YCRCB422: 1349 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422; 1350 break; 1351 case DRM_COLOR_FORMAT_RGB444: 1352 case DRM_COLOR_FORMAT_YCRCB444: 1353 default: 1354 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1355 break; 1356 } 1357 1358 conn_state->bus_format = dp->output_fmt->bus_format; 1359 conn_state->bpc = dp->output_fmt->bpc; 1360 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 1361 if (dp->output_fmt->color_format == DRM_COLOR_FORMAT_RGB444) 1362 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 1363 else 1364 conn_state->color_range = DRM_COLOR_YCBCR_LIMITED_RANGE; 1365 1366 err: 1367 free(mode_buf); 1368 1369 return 0; 1370 } 1371 1372 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 1373 .init = analogix_dp_connector_init, 1374 .get_edid = analogix_dp_connector_get_edid, 1375 .enable = analogix_dp_connector_enable, 1376 .disable = analogix_dp_connector_disable, 1377 .detect = analogix_dp_connector_detect, 1378 .mode_valid = analogix_dp_connector_mode_valid, 1379 .get_timing = analogix_dp_connector_get_timing, 1380 }; 1381 1382 static u32 analogix_dp_parse_link_frequencies(struct analogix_dp_device *dp) 1383 { 1384 struct udevice *dev = dp->dev; 1385 const struct device_node *endpoint; 1386 u64 frequency = 0; 1387 1388 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 1389 if (!endpoint) 1390 return 0; 1391 1392 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 1393 return 0; 1394 1395 if (!frequency) 1396 return 0; 1397 1398 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 1399 1400 switch (frequency) { 1401 case 162000: 1402 case 270000: 1403 case 540000: 1404 break; 1405 default: 1406 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 1407 return 0; 1408 } 1409 1410 return frequency; 1411 } 1412 1413 static int analogix_dp_parse_dt(struct analogix_dp_device *dp) 1414 { 1415 struct udevice *dev = dp->dev; 1416 int len; 1417 u32 num_lanes; 1418 u32 max_link_rate; 1419 int ret; 1420 1421 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1422 dp->video_bist_enable = dev_read_bool(dev, "analogix,video-bist-enable"); 1423 dp->video_info.force_stream_valid = 1424 dev_read_bool(dev, "analogix,force-stream-valid"); 1425 1426 max_link_rate = analogix_dp_parse_link_frequencies(dp); 1427 if (max_link_rate && max_link_rate < drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate)) 1428 dp->video_info.max_link_rate = drm_dp_link_rate_to_bw_code(max_link_rate); 1429 1430 if (dev_read_prop(dev, "data-lanes", &len)) { 1431 num_lanes = len / sizeof(u32); 1432 if (num_lanes < 1 || num_lanes > 4 || num_lanes == 3) { 1433 dev_err(dev, "bad number of data lanes\n"); 1434 return -EINVAL; 1435 } 1436 1437 ret = dev_read_u32_array(dev, "data-lanes", dp->lane_map, 1438 num_lanes); 1439 if (ret) 1440 return ret; 1441 1442 dp->video_info.max_lane_count = num_lanes; 1443 } else { 1444 dp->lane_map[0] = 0; 1445 dp->lane_map[1] = 1; 1446 dp->lane_map[2] = 2; 1447 dp->lane_map[3] = 3; 1448 } 1449 1450 return 0; 1451 } 1452 1453 static int analogix_dp_ddc_init(struct analogix_dp_device *dp) 1454 { 1455 dp->aux.name = "analogix-dp"; 1456 dp->aux.dev = dp->dev; 1457 dp->aux.transfer = analogix_dp_aux_transfer; 1458 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1459 1460 return 0; 1461 } 1462 1463 static int analogix_dp_probe(struct udevice *dev) 1464 { 1465 struct analogix_dp_device *dp = dev_get_priv(dev); 1466 const struct rockchip_dp_chip_data *pdata = 1467 (const struct rockchip_dp_chip_data *)dev_get_driver_data(dev); 1468 struct udevice *syscon; 1469 int ret; 1470 1471 dp->reg_base = dev_read_addr_ptr(dev); 1472 1473 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 1474 if (dp->id < 0) 1475 dp->id = 0; 1476 1477 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1478 &syscon); 1479 if (!ret) { 1480 dp->grf = syscon_get_regmap(syscon); 1481 if (!dp->grf) 1482 return -ENODEV; 1483 } 1484 1485 ret = reset_get_bulk(dev, &dp->resets); 1486 if (ret) { 1487 dev_err(dev, "failed to get reset control: %d\n", ret); 1488 return ret; 1489 } 1490 1491 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1492 GPIOD_IS_IN); 1493 if (ret && ret != -ENOENT) { 1494 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1495 return ret; 1496 } 1497 1498 generic_phy_get_by_name(dev, "dp", &dp->phy); 1499 1500 dp->plat_data.dev_type = ROCKCHIP_DP; 1501 dp->plat_data.subdev_type = pdata->chip_type; 1502 dp->plat_data.ssc = pdata->ssc; 1503 dp->plat_data.max_bpc = pdata->max_bpc ? pdata->max_bpc : 8; 1504 1505 dp->video_info.max_link_rate = pdata->max_link_rate; 1506 dp->video_info.max_lane_count = pdata->max_lane_count; 1507 1508 dp->dev = dev; 1509 1510 ret = analogix_dp_parse_dt(dp); 1511 if (ret) { 1512 dev_err(dev, "failed to parse DT: %d\n", ret); 1513 return ret; 1514 } 1515 1516 analogix_dp_ddc_init(dp); 1517 1518 rockchip_connector_bind(&dp->connector, dev, dp->id, &analogix_dp_connector_funcs, 1519 NULL, DRM_MODE_CONNECTOR_eDP); 1520 1521 return 0; 1522 } 1523 1524 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 1525 .lcdsel_grf_reg = 0x025c, 1526 .lcdsel_big = 0 | BIT(21), 1527 .lcdsel_lit = BIT(5) | BIT(21), 1528 .chip_type = RK3288_DP, 1529 1530 .max_link_rate = DP_LINK_BW_2_7, 1531 .max_lane_count = 4, 1532 }; 1533 1534 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 1535 .chip_type = RK3368_EDP, 1536 1537 .max_link_rate = DP_LINK_BW_2_7, 1538 .max_lane_count = 4, 1539 }; 1540 1541 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 1542 .lcdsel_grf_reg = 0x6250, 1543 .lcdsel_big = 0 | BIT(21), 1544 .lcdsel_lit = BIT(5) | BIT(21), 1545 .chip_type = RK3399_EDP, 1546 .ssc = true, 1547 1548 .max_link_rate = DP_LINK_BW_5_4, 1549 .max_lane_count = 4, 1550 }; 1551 1552 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 1553 .chip_type = RK3568_EDP, 1554 .ssc = true, 1555 1556 .max_link_rate = DP_LINK_BW_2_7, 1557 .max_lane_count = 4, 1558 }; 1559 1560 static const struct rockchip_dp_chip_data rk3576_edp_platform_data = { 1561 .chip_type = RK3576_EDP, 1562 .ssc = true, 1563 1564 .max_link_rate = DP_LINK_BW_5_4, 1565 .max_lane_count = 4, 1566 .format_yuv = true, 1567 .max_bpc = 10, 1568 }; 1569 1570 static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { 1571 .chip_type = RK3588_EDP, 1572 .ssc = true, 1573 1574 .max_link_rate = DP_LINK_BW_5_4, 1575 .max_lane_count = 4, 1576 .format_yuv = true, 1577 .max_bpc = 10, 1578 }; 1579 1580 static const struct udevice_id analogix_dp_ids[] = { 1581 { 1582 .compatible = "rockchip,rk3288-dp", 1583 .data = (ulong)&rk3288_edp_platform_data, 1584 }, { 1585 .compatible = "rockchip,rk3368-edp", 1586 .data = (ulong)&rk3368_edp_platform_data, 1587 }, { 1588 .compatible = "rockchip,rk3399-edp", 1589 .data = (ulong)&rk3399_edp_platform_data, 1590 }, { 1591 .compatible = "rockchip,rk3568-edp", 1592 .data = (ulong)&rk3568_edp_platform_data, 1593 }, { 1594 .compatible = "rockchip,rk3576-edp", 1595 .data = (ulong)&rk3576_edp_platform_data, 1596 }, { 1597 .compatible = "rockchip,rk3588-edp", 1598 .data = (ulong)&rk3588_edp_platform_data, 1599 }, 1600 {} 1601 }; 1602 1603 U_BOOT_DRIVER(analogix_dp) = { 1604 .name = "analogix_dp", 1605 .id = UCLASS_DISPLAY, 1606 .of_match = analogix_dp_ids, 1607 .probe = analogix_dp_probe, 1608 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1609 }; 1610