1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/read.h> 15 #include <linux/list.h> 16 #include <syscon.h> 17 #include <asm/arch-rockchip/clock.h> 18 #include <asm/gpio.h> 19 20 #include "rockchip_display.h" 21 #include "rockchip_crtc.h" 22 #include "rockchip_connector.h" 23 #include "rockchip_panel.h" 24 #include "analogix_dp.h" 25 26 /** 27 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 28 * @lcdsel_grf_reg: grf register offset of lcdc select 29 * @lcdsel_big: reg value of selecting vop big for eDP 30 * @lcdsel_lit: reg value of selecting vop little for eDP 31 */ 32 struct rockchip_dp_chip_data { 33 u32 lcdsel_grf_reg; 34 u32 lcdsel_big; 35 u32 lcdsel_lit; 36 u32 chip_type; 37 bool has_vop_sel; 38 }; 39 40 static void 41 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 42 bool enable) 43 { 44 u8 data; 45 46 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 47 48 if (enable) 49 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 50 DP_LANE_COUNT_ENHANCED_FRAME_EN | 51 DPCD_LANE_COUNT_SET(data)); 52 else 53 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 54 DPCD_LANE_COUNT_SET(data)); 55 } 56 57 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 58 { 59 u8 data; 60 int retval; 61 62 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 63 retval = DPCD_ENHANCED_FRAME_CAP(data); 64 65 return retval; 66 } 67 68 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 69 { 70 u8 data; 71 72 data = analogix_dp_is_enhanced_mode_available(dp); 73 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 74 analogix_dp_enable_enhanced_mode(dp, data); 75 } 76 77 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 78 { 79 analogix_dp_set_training_pattern(dp, DP_NONE); 80 81 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 82 DP_TRAINING_PATTERN_DISABLE); 83 } 84 85 static void 86 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp, 87 int pre_emphasis, int lane) 88 { 89 switch (lane) { 90 case 0: 91 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis); 92 break; 93 case 1: 94 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis); 95 break; 96 97 case 2: 98 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis); 99 break; 100 101 case 3: 102 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis); 103 break; 104 } 105 } 106 107 static int analogix_dp_link_start(struct analogix_dp_device *dp) 108 { 109 u8 buf[4]; 110 int lane, lane_count, pll_tries, retval; 111 112 lane_count = dp->link_train.lane_count; 113 114 dp->link_train.lt_state = CLOCK_RECOVERY; 115 dp->link_train.eq_loop = 0; 116 117 for (lane = 0; lane < lane_count; lane++) 118 dp->link_train.cr_loop[lane] = 0; 119 120 /* Set link rate and count as you want to establish*/ 121 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 122 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 123 124 /* Setup RX configuration */ 125 buf[0] = dp->link_train.link_rate; 126 buf[1] = dp->link_train.lane_count; 127 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 128 if (retval) 129 return retval; 130 131 /* Set TX pre-emphasis to minimum */ 132 for (lane = 0; lane < lane_count; lane++) 133 analogix_dp_set_lane_lane_pre_emphasis(dp, 134 PRE_EMPHASIS_LEVEL_0, lane); 135 136 /* Wait for PLL lock */ 137 pll_tries = 0; 138 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 139 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { 140 dev_err(dp->dev, "Wait for PLL lock timed out\n"); 141 return -ETIMEDOUT; 142 } 143 144 pll_tries++; 145 udelay(120); 146 } 147 148 /* Set training pattern 1 */ 149 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 150 151 /* Set RX training pattern */ 152 retval = analogix_dp_write_byte_to_dpcd(dp, 153 DP_TRAINING_PATTERN_SET, 154 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 155 if (retval) 156 return retval; 157 158 for (lane = 0; lane < lane_count; lane++) 159 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 160 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 161 162 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 163 lane_count, buf); 164 165 return retval; 166 } 167 168 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 169 { 170 int shift = (lane & 1) * 4; 171 u8 link_value = link_status[lane >> 1]; 172 173 return (link_value >> shift) & 0xf; 174 } 175 176 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 177 { 178 int lane; 179 u8 lane_status; 180 181 for (lane = 0; lane < lane_count; lane++) { 182 lane_status = analogix_dp_get_lane_status(link_status, lane); 183 if ((lane_status & DP_LANE_CR_DONE) == 0) 184 return -EINVAL; 185 } 186 return 0; 187 } 188 189 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 190 int lane_count) 191 { 192 int lane; 193 u8 lane_status; 194 195 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 196 return -EINVAL; 197 198 for (lane = 0; lane < lane_count; lane++) { 199 lane_status = analogix_dp_get_lane_status(link_status, lane); 200 lane_status &= DP_CHANNEL_EQ_BITS; 201 if (lane_status != DP_CHANNEL_EQ_BITS) 202 return -EINVAL; 203 } 204 205 return 0; 206 } 207 208 static unsigned char 209 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 210 { 211 int shift = (lane & 1) * 4; 212 u8 link_value = adjust_request[lane >> 1]; 213 214 return (link_value >> shift) & 0x3; 215 } 216 217 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 218 u8 adjust_request[2], 219 int lane) 220 { 221 int shift = (lane & 1) * 4; 222 u8 link_value = adjust_request[lane >> 1]; 223 224 return ((link_value >> shift) & 0xc) >> 2; 225 } 226 227 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp, 228 u8 training_lane_set, int lane) 229 { 230 switch (lane) { 231 case 0: 232 analogix_dp_set_lane0_link_training(dp, training_lane_set); 233 break; 234 case 1: 235 analogix_dp_set_lane1_link_training(dp, training_lane_set); 236 break; 237 238 case 2: 239 analogix_dp_set_lane2_link_training(dp, training_lane_set); 240 break; 241 242 case 3: 243 analogix_dp_set_lane3_link_training(dp, training_lane_set); 244 break; 245 } 246 } 247 248 static unsigned int 249 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, 250 int lane) 251 { 252 u32 reg; 253 254 switch (lane) { 255 case 0: 256 reg = analogix_dp_get_lane0_link_training(dp); 257 break; 258 case 1: 259 reg = analogix_dp_get_lane1_link_training(dp); 260 break; 261 case 2: 262 reg = analogix_dp_get_lane2_link_training(dp); 263 break; 264 case 3: 265 reg = analogix_dp_get_lane3_link_training(dp); 266 break; 267 default: 268 WARN_ON(1); 269 return 0; 270 } 271 272 return reg; 273 } 274 275 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 276 { 277 analogix_dp_training_pattern_dis(dp); 278 analogix_dp_set_enhanced_mode(dp); 279 280 dp->link_train.lt_state = FAILED; 281 } 282 283 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 284 u8 adjust_request[2]) 285 { 286 int lane, lane_count; 287 u8 voltage_swing, pre_emphasis, training_lane; 288 289 lane_count = dp->link_train.lane_count; 290 for (lane = 0; lane < lane_count; lane++) { 291 voltage_swing = analogix_dp_get_adjust_request_voltage( 292 adjust_request, lane); 293 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 294 adjust_request, lane); 295 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 296 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 297 298 if (voltage_swing == VOLTAGE_LEVEL_3) 299 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 300 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 301 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 302 303 dp->link_train.training_lane[lane] = training_lane; 304 } 305 } 306 307 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 308 { 309 int lane, lane_count, retval; 310 u8 voltage_swing, pre_emphasis, training_lane; 311 u8 link_status[2], adjust_request[2]; 312 313 udelay(101); 314 315 lane_count = dp->link_train.lane_count; 316 317 retval = analogix_dp_read_bytes_from_dpcd(dp, 318 DP_LANE0_1_STATUS, 2, link_status); 319 if (retval) 320 return retval; 321 322 retval = analogix_dp_read_bytes_from_dpcd(dp, 323 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 324 if (retval) 325 return retval; 326 327 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 328 /* set training pattern 2 for EQ */ 329 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 330 331 retval = analogix_dp_write_byte_to_dpcd(dp, 332 DP_TRAINING_PATTERN_SET, 333 DP_LINK_SCRAMBLING_DISABLE | 334 DP_TRAINING_PATTERN_2); 335 if (retval) 336 return retval; 337 338 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 339 dp->link_train.lt_state = EQUALIZER_TRAINING; 340 } else { 341 for (lane = 0; lane < lane_count; lane++) { 342 training_lane = analogix_dp_get_lane_link_training( 343 dp, lane); 344 voltage_swing = analogix_dp_get_adjust_request_voltage( 345 adjust_request, lane); 346 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 347 adjust_request, lane); 348 349 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 350 voltage_swing && 351 DPCD_PRE_EMPHASIS_GET(training_lane) == 352 pre_emphasis) 353 dp->link_train.cr_loop[lane]++; 354 355 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 356 voltage_swing == VOLTAGE_LEVEL_3 || 357 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 358 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 359 dp->link_train.cr_loop[lane], 360 voltage_swing, pre_emphasis); 361 analogix_dp_reduce_link_rate(dp); 362 return -EIO; 363 } 364 } 365 } 366 367 analogix_dp_get_adjust_training_lane(dp, adjust_request); 368 369 for (lane = 0; lane < lane_count; lane++) 370 analogix_dp_set_lane_link_training(dp, 371 dp->link_train.training_lane[lane], lane); 372 373 retval = analogix_dp_write_bytes_to_dpcd(dp, 374 DP_TRAINING_LANE0_SET, lane_count, 375 dp->link_train.training_lane); 376 if (retval) 377 return retval; 378 379 return retval; 380 } 381 382 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 383 { 384 int lane, lane_count, retval; 385 u32 reg; 386 u8 link_align, link_status[2], adjust_request[2]; 387 388 udelay(401); 389 390 lane_count = dp->link_train.lane_count; 391 392 retval = analogix_dp_read_bytes_from_dpcd(dp, 393 DP_LANE0_1_STATUS, 2, link_status); 394 if (retval) 395 return retval; 396 397 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 398 analogix_dp_reduce_link_rate(dp); 399 return -EIO; 400 } 401 402 retval = analogix_dp_read_bytes_from_dpcd(dp, 403 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 404 if (retval) 405 return retval; 406 407 retval = analogix_dp_read_byte_from_dpcd(dp, 408 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 409 if (retval) 410 return retval; 411 412 analogix_dp_get_adjust_training_lane(dp, adjust_request); 413 414 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 415 /* traing pattern Set to Normal */ 416 analogix_dp_training_pattern_dis(dp); 417 418 printf("Link Training success!\n"); 419 420 analogix_dp_get_link_bandwidth(dp, ®); 421 dp->link_train.link_rate = reg; 422 analogix_dp_get_lane_count(dp, ®); 423 dp->link_train.lane_count = reg; 424 425 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 426 dp->link_train.link_rate, dp->link_train.lane_count); 427 428 /* set enhanced mode if available */ 429 analogix_dp_set_enhanced_mode(dp); 430 dp->link_train.lt_state = FINISHED; 431 432 return 0; 433 } 434 435 /* not all locked */ 436 dp->link_train.eq_loop++; 437 438 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 439 dev_dbg(dp->dev, "EQ Max loop\n"); 440 analogix_dp_reduce_link_rate(dp); 441 return -EIO; 442 } 443 444 for (lane = 0; lane < lane_count; lane++) 445 analogix_dp_set_lane_link_training(dp, 446 dp->link_train.training_lane[lane], lane); 447 448 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 449 lane_count, dp->link_train.training_lane); 450 451 return retval; 452 } 453 454 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 455 u8 *bandwidth) 456 { 457 u8 data; 458 459 /* 460 * For DP rev.1.1, Maximum link rate of Main Link lanes 461 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 462 * For DP rev.1.2, Maximum link rate of Main Link lanes 463 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 464 */ 465 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 466 *bandwidth = data; 467 } 468 469 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 470 u8 *lane_count) 471 { 472 u8 data; 473 474 /* 475 * For DP rev.1.1, Maximum number of Main Link lanes 476 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 477 */ 478 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 479 *lane_count = DPCD_MAX_LANE_COUNT(data); 480 } 481 482 static int analogix_dp_init_training(struct analogix_dp_device *dp, 483 enum link_lane_count_type max_lane, 484 int max_rate) 485 { 486 /* 487 * MACRO_RST must be applied after the PLL_LOCK to avoid 488 * the DP inter pair skew issue for at least 10 us 489 */ 490 analogix_dp_reset_macro(dp); 491 492 /* Initialize by reading RX's DPCD */ 493 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 494 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 495 496 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 497 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 498 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 499 dev_err(dp->dev, "failed to get Rx Max Link Rate\n"); 500 return -ENODEV; 501 } 502 503 if (dp->link_train.lane_count == 0) { 504 dev_err(dp->dev, "failed to get Rx Max Lane Count\n"); 505 return -ENODEV; 506 } 507 508 /* Setup TX lane count & rate */ 509 if (dp->link_train.lane_count > max_lane) 510 dp->link_train.lane_count = max_lane; 511 if (dp->link_train.link_rate > max_rate) 512 dp->link_train.link_rate = max_rate; 513 514 /* All DP analog module power up */ 515 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 516 517 return 0; 518 } 519 520 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 521 { 522 int retval = 0, training_finished = 0; 523 524 dp->link_train.lt_state = START; 525 526 /* Process here */ 527 while (!retval && !training_finished) { 528 switch (dp->link_train.lt_state) { 529 case START: 530 retval = analogix_dp_link_start(dp); 531 if (retval) 532 dev_err(dp->dev, "LT link start failed!\n"); 533 break; 534 case CLOCK_RECOVERY: 535 retval = analogix_dp_process_clock_recovery(dp); 536 if (retval) 537 dev_err(dp->dev, "LT CR failed!\n"); 538 break; 539 case EQUALIZER_TRAINING: 540 retval = analogix_dp_process_equalizer_training(dp); 541 if (retval) 542 dev_err(dp->dev, "LT EQ failed!\n"); 543 break; 544 case FINISHED: 545 training_finished = 1; 546 break; 547 case FAILED: 548 return -EREMOTEIO; 549 } 550 } 551 552 return retval; 553 } 554 555 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 556 u32 count, u32 bwtype) 557 { 558 int ret; 559 560 ret = analogix_dp_init_training(dp, count, bwtype); 561 if (ret < 0) { 562 dev_err(dp->dev, "failed to init training\n"); 563 return ret; 564 } 565 566 ret = analogix_dp_sw_link_training(dp); 567 if (ret < 0) { 568 dev_err(dp->dev, "failed to do sw link training\n"); 569 return ret; 570 } 571 572 return 0; 573 } 574 575 static int analogix_dp_config_video(struct analogix_dp_device *dp) 576 { 577 int timeout_loop = 0; 578 int done_count = 0; 579 580 analogix_dp_config_video_slave_mode(dp); 581 582 analogix_dp_set_video_color_format(dp); 583 584 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 585 dev_err(dp->dev, "PLL is not locked yet.\n"); 586 return -EINVAL; 587 } 588 589 for (;;) { 590 timeout_loop++; 591 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 592 break; 593 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 594 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 595 return -ETIMEDOUT; 596 } 597 598 udelay(2); 599 } 600 601 /* Set to use the register calculated M/N video */ 602 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 603 604 /* For video bist, Video timing must be generated by register */ 605 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 606 607 /* Disable video mute */ 608 analogix_dp_enable_video_mute(dp, 0); 609 610 /* Configure video slave mode */ 611 analogix_dp_enable_video_master(dp, 0); 612 613 /* Enable video input */ 614 analogix_dp_start_video(dp); 615 616 timeout_loop = 0; 617 618 for (;;) { 619 timeout_loop++; 620 if (analogix_dp_is_video_stream_on(dp) == 0) { 621 done_count++; 622 if (done_count > 10) 623 break; 624 } else if (done_count) { 625 done_count = 0; 626 } 627 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 628 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 629 return -ETIMEDOUT; 630 } 631 632 udelay(1001); 633 } 634 635 return 0; 636 } 637 638 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 639 bool enable) 640 { 641 u8 data; 642 643 if (enable) { 644 analogix_dp_enable_scrambling(dp); 645 646 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 647 &data); 648 analogix_dp_write_byte_to_dpcd(dp, 649 DP_TRAINING_PATTERN_SET, 650 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 651 } else { 652 analogix_dp_disable_scrambling(dp); 653 654 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 655 &data); 656 analogix_dp_write_byte_to_dpcd(dp, 657 DP_TRAINING_PATTERN_SET, 658 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 659 } 660 } 661 662 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 663 { 664 analogix_dp_reset(dp); 665 666 analogix_dp_swreset(dp); 667 668 analogix_dp_init_analog_param(dp); 669 analogix_dp_init_interrupt(dp); 670 671 /* SW defined function Normal operation */ 672 analogix_dp_enable_sw_function(dp); 673 674 analogix_dp_config_interrupt(dp); 675 analogix_dp_init_analog_func(dp); 676 677 analogix_dp_init_hpd(dp); 678 analogix_dp_init_aux(dp); 679 } 680 681 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 682 { 683 int i; 684 unsigned char sum = 0; 685 686 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 687 sum = sum + edid_data[i]; 688 689 return sum; 690 } 691 692 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 693 { 694 unsigned char *edid = dp->edid; 695 unsigned int extend_block = 0; 696 unsigned char test_vector; 697 int retval; 698 699 /* 700 * EDID device address is 0x50. 701 * However, if necessary, you must have set upper address 702 * into E-EDID in I2C device, 0x30. 703 */ 704 705 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 706 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 707 EDID_EXTENSION_FLAG, 708 &extend_block); 709 if (retval) 710 return retval; 711 712 if (extend_block > 0) { 713 debug("EDID data includes a single extension!\n"); 714 715 /* Read EDID data */ 716 retval = analogix_dp_read_bytes_from_i2c(dp, 717 I2C_EDID_DEVICE_ADDR, 718 EDID_HEADER_PATTERN, 719 EDID_BLOCK_LENGTH, 720 &edid[EDID_HEADER_PATTERN]); 721 if (retval < 0) 722 return retval; 723 724 if (analogix_dp_calc_edid_check_sum(edid)) 725 return -EINVAL; 726 727 /* Read additional EDID data */ 728 retval = analogix_dp_read_bytes_from_i2c(dp, 729 I2C_EDID_DEVICE_ADDR, 730 EDID_BLOCK_LENGTH, 731 EDID_BLOCK_LENGTH, 732 &edid[EDID_BLOCK_LENGTH]); 733 if (retval < 0) 734 return retval; 735 736 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 737 return -EINVAL; 738 739 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 740 &test_vector); 741 if (test_vector & DP_TEST_LINK_EDID_READ) { 742 analogix_dp_write_byte_to_dpcd(dp, 743 DP_TEST_EDID_CHECKSUM, 744 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 745 analogix_dp_write_byte_to_dpcd(dp, 746 DP_TEST_RESPONSE, 747 DP_TEST_EDID_CHECKSUM_WRITE); 748 } 749 } else { 750 dev_info(dp->dev, 751 "EDID data does not include any extensions.\n"); 752 753 /* Read EDID data */ 754 retval = analogix_dp_read_bytes_from_i2c(dp, 755 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 756 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 757 if (retval < 0) 758 return retval; 759 760 if (analogix_dp_calc_edid_check_sum(edid)) 761 return -EINVAL; 762 763 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 764 &test_vector); 765 if (test_vector & DP_TEST_LINK_EDID_READ) { 766 analogix_dp_write_byte_to_dpcd(dp, 767 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 768 analogix_dp_write_byte_to_dpcd(dp, 769 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 770 } 771 } 772 773 return 0; 774 } 775 776 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 777 { 778 u8 buf[12]; 779 int i, try = 5; 780 int retval; 781 782 retry: 783 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 784 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 785 786 if (retval && try--) { 787 mdelay(10); 788 goto retry; 789 } 790 791 if (retval) 792 return retval; 793 794 /* Read EDID */ 795 for (i = 0; i < 3; i++) { 796 retval = analogix_dp_read_edid(dp); 797 if (!retval) 798 break; 799 } 800 801 return retval; 802 } 803 804 static int analogix_dp_connector_init(struct display_state *state) 805 { 806 struct connector_state *conn_state = &state->conn_state; 807 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 808 struct video_info *video = &dp->video_info; 809 struct rockchip_panel *panel = state_get_panel(state); 810 811 conn_state->type = DRM_MODE_CONNECTOR_eDP; 812 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 813 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 814 815 switch (panel->bpc) { 816 case 12: 817 video->color_depth = COLOR_12; 818 break; 819 case 10: 820 video->color_depth = COLOR_10; 821 break; 822 case 6: 823 video->color_depth = COLOR_6; 824 break; 825 case 8: 826 default: 827 video->color_depth = COLOR_8; 828 break; 829 } 830 831 /* eDP software reset request */ 832 reset_assert(&dp->reset); 833 udelay(1); 834 reset_deassert(&dp->reset); 835 836 analogix_dp_init_dp(dp); 837 838 return 0; 839 } 840 841 static int analogix_dp_connector_get_edid(struct display_state *state) 842 { 843 struct connector_state *conn_state = &state->conn_state; 844 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 845 int ret; 846 847 ret = analogix_dp_handle_edid(dp); 848 if (ret) { 849 dev_err(dp->dev, "failed to get edid\n"); 850 return ret; 851 } 852 853 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 854 855 return 0; 856 } 857 858 static int analogix_dp_connector_enable(struct display_state *state) 859 { 860 struct connector_state *conn_state = &state->conn_state; 861 struct crtc_state *crtc_state = &state->crtc_state; 862 const struct rockchip_connector *connector = conn_state->connector; 863 const struct rockchip_dp_chip_data *pdata = connector->data; 864 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 865 u32 val; 866 int ret; 867 868 if (pdata->has_vop_sel) { 869 if (crtc_state->crtc_id) 870 val = pdata->lcdsel_lit; 871 else 872 val = pdata->lcdsel_big; 873 874 writel(val, dp->grf + pdata->lcdsel_grf_reg); 875 } 876 877 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 878 dp->video_info.max_link_rate); 879 if (ret) { 880 dev_err(dp->dev, "unable to do link train\n"); 881 return ret; 882 } 883 884 analogix_dp_enable_scramble(dp, 1); 885 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 886 analogix_dp_enable_enhanced_mode(dp, 1); 887 888 analogix_dp_init_video(dp); 889 ret = analogix_dp_config_video(dp); 890 if (ret) { 891 dev_err(dp->dev, "unable to config video\n"); 892 return ret; 893 } 894 895 return 0; 896 } 897 898 static int analogix_dp_connector_disable(struct display_state *state) 899 { 900 /* TODO */ 901 902 return 0; 903 } 904 905 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 906 .init = analogix_dp_connector_init, 907 .get_edid = analogix_dp_connector_get_edid, 908 .enable = analogix_dp_connector_enable, 909 .disable = analogix_dp_connector_disable, 910 }; 911 912 static int analogix_dp_probe(struct udevice *dev) 913 { 914 struct analogix_dp_device *dp = dev_get_priv(dev); 915 const struct rockchip_connector *connector = 916 (const struct rockchip_connector *)dev_get_driver_data(dev); 917 const struct rockchip_dp_chip_data *pdata = connector->data; 918 int ret; 919 920 dp->reg_base = dev_read_addr_ptr(dev); 921 dp->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 922 if (IS_ERR(dp->grf)) 923 return PTR_ERR(dp->grf); 924 925 ret = reset_get_by_name(dev, "dp", &dp->reset); 926 if (ret) { 927 dev_err(dev, "failed to get reset control: %d\n", ret); 928 return ret; 929 } 930 931 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 932 GPIOD_IS_IN); 933 if (ret && ret != -ENOENT) { 934 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 935 return ret; 936 } 937 938 dp->plat_data.dev_type = ROCKCHIP_DP; 939 dp->plat_data.subdev_type = pdata->chip_type; 940 /* 941 * Like Rockchip DisplayPort TRM indicate that "Main link 942 * containing 4 physical lanes of 2.7/1.62 Gbps/lane". 943 */ 944 dp->video_info.max_link_rate = 0x0A; 945 dp->video_info.max_lane_count = 0x04; 946 947 dp->dev = dev; 948 949 return 0; 950 } 951 952 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 953 .lcdsel_grf_reg = 0x025c, 954 .lcdsel_big = 0 | BIT(21), 955 .lcdsel_lit = BIT(5) | BIT(21), 956 .chip_type = RK3288_DP, 957 .has_vop_sel = true, 958 }; 959 960 static const struct rockchip_connector rk3288_edp_driver_data = { 961 .funcs = &analogix_dp_connector_funcs, 962 .data = &rk3288_edp_platform_data, 963 }; 964 965 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 966 .chip_type = RK3368_EDP, 967 .has_vop_sel = false, 968 }; 969 970 static const struct rockchip_connector rk3368_edp_driver_data = { 971 .funcs = &analogix_dp_connector_funcs, 972 .data = &rk3368_edp_platform_data, 973 }; 974 975 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 976 .lcdsel_grf_reg = 0x6250, 977 .lcdsel_big = 0 | BIT(21), 978 .lcdsel_lit = BIT(5) | BIT(21), 979 .chip_type = RK3399_EDP, 980 .has_vop_sel = true, 981 }; 982 983 static const struct rockchip_connector rk3399_edp_driver_data = { 984 .funcs = &analogix_dp_connector_funcs, 985 .data = &rk3399_edp_platform_data, 986 }; 987 988 static const struct udevice_id analogix_dp_ids[] = { 989 { 990 .compatible = "rockchip,rk3288-dp", 991 .data = (ulong)&rk3288_edp_driver_data, 992 }, { 993 .compatible = "rockchip,rk3368-edp", 994 .data = (ulong)&rk3368_edp_driver_data, 995 }, { 996 .compatible = "rockchip,rk3399-edp", 997 .data = (ulong)&rk3399_edp_driver_data, 998 }, 999 {} 1000 }; 1001 1002 U_BOOT_DRIVER(analogix_dp) = { 1003 .name = "analogix_dp", 1004 .id = UCLASS_DISPLAY, 1005 .of_match = analogix_dp_ids, 1006 .probe = analogix_dp_probe, 1007 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1008 }; 1009