1 /* 2 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. 3 * 4 * Interrupt support is added. Now, it has been tested 5 * on ULI1575 chip and works well with USB keyboard. 6 * 7 * (C) Copyright 2007 8 * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> 9 * 10 * (C) Copyright 2003 11 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> 12 * 13 * Note: Much of this code has been derived from Linux 2.4 14 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 15 * (C) Copyright 2000-2002 David Brownell 16 * 17 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard 18 * ebenard@eukrea.com - based on s3c24x0's driver 19 * 20 * SPDX-License-Identifier: GPL-2.0+ 21 */ 22 /* 23 * IMPORTANT NOTES 24 * 1 - Read doc/README.generic_usb_ohci 25 * 2 - this driver is intended for use with USB Mass Storage Devices 26 * (BBB) and USB keyboard. There is NO support for Isochronous pipes! 27 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG 28 * to activate workaround for bug #41 or this driver will NOT work! 29 */ 30 31 #include <common.h> 32 #include <asm/byteorder.h> 33 #include <dm.h> 34 #include <errno.h> 35 36 #if defined(CONFIG_PCI_OHCI) 37 # include <pci.h> 38 #if !defined(CONFIG_PCI_OHCI_DEVNO) 39 #define CONFIG_PCI_OHCI_DEVNO 0 40 #endif 41 #endif 42 43 #include <malloc.h> 44 #include <memalign.h> 45 #include <usb.h> 46 47 #include "ohci.h" 48 49 #ifdef CONFIG_AT91RM9200 50 #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ 51 #endif 52 53 #if defined(CONFIG_CPU_ARM920T) || \ 54 defined(CONFIG_PCI_OHCI) || \ 55 defined(CONFIG_SYS_OHCI_USE_NPS) 56 # define OHCI_USE_NPS /* force NoPowerSwitching mode */ 57 #endif 58 59 #undef OHCI_VERBOSE_DEBUG /* not always helpful */ 60 #undef DEBUG 61 #undef SHOW_INFO 62 #undef OHCI_FILL_TRACE 63 64 /* For initializing controller (mask in an HCFS mode too) */ 65 #define OHCI_CONTROL_INIT \ 66 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE 67 68 #if !CONFIG_IS_ENABLED(DM_USB) 69 #ifdef CONFIG_PCI_OHCI 70 static struct pci_device_id ohci_pci_ids[] = { 71 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ 72 {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ 73 {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ 74 /* Please add supported PCI OHCI controller ids here */ 75 {0, 0} 76 }; 77 #endif 78 #endif 79 80 #ifdef CONFIG_PCI_EHCI_DEVNO 81 static struct pci_device_id ehci_pci_ids[] = { 82 {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ 83 /* Please add supported PCI EHCI controller ids here */ 84 {0, 0} 85 }; 86 #endif 87 88 #ifdef DEBUG 89 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) 90 #else 91 #define dbg(format, arg...) do {} while (0) 92 #endif /* DEBUG */ 93 #define err(format, arg...) printf("ERROR: " format "\n", ## arg) 94 #ifdef SHOW_INFO 95 #define info(format, arg...) printf("INFO: " format "\n", ## arg) 96 #else 97 #define info(format, arg...) do {} while (0) 98 #endif 99 100 #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER 101 # define m16_swap(x) cpu_to_be16(x) 102 # define m32_swap(x) cpu_to_be32(x) 103 #else 104 # define m16_swap(x) cpu_to_le16(x) 105 # define m32_swap(x) cpu_to_le32(x) 106 #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ 107 108 /* We really should do proper cache flushing everywhere */ 109 #define flush_dcache_buffer(addr, size) \ 110 flush_dcache_range((unsigned long)(addr), \ 111 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) 112 #define invalidate_dcache_buffer(addr, size) \ 113 invalidate_dcache_range((unsigned long)(addr), \ 114 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) 115 116 /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */ 117 #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16) 118 #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16) 119 #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32) 120 #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256) 121 #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16) 122 #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16) 123 #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32) 124 #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256) 125 126 #if CONFIG_IS_ENABLED(DM_USB) 127 /* 128 * The various ohci_mdelay(1) calls in the code seem unnecessary. We keep 129 * them around when building for older boards not yet converted to the dm 130 * just in case (to avoid regressions), for dm this turns them into nops. 131 */ 132 #define ohci_mdelay(x) 133 #else 134 #define ohci_mdelay(x) mdelay(x) 135 #endif 136 137 #if !CONFIG_IS_ENABLED(DM_USB) 138 /* global ohci_t */ 139 static ohci_t gohci; 140 /* this must be aligned to a 256 byte boundary */ 141 struct ohci_hcca ghcca[1]; 142 #endif 143 144 /* mapping of the OHCI CC status to error codes */ 145 static int cc_to_error[16] = { 146 /* No Error */ 0, 147 /* CRC Error */ USB_ST_CRC_ERR, 148 /* Bit Stuff */ USB_ST_BIT_ERR, 149 /* Data Togg */ USB_ST_CRC_ERR, 150 /* Stall */ USB_ST_STALLED, 151 /* DevNotResp */ -1, 152 /* PIDCheck */ USB_ST_BIT_ERR, 153 /* UnExpPID */ USB_ST_BIT_ERR, 154 /* DataOver */ USB_ST_BUF_ERR, 155 /* DataUnder */ USB_ST_BUF_ERR, 156 /* reservd */ -1, 157 /* reservd */ -1, 158 /* BufferOver */ USB_ST_BUF_ERR, 159 /* BuffUnder */ USB_ST_BUF_ERR, 160 /* Not Access */ -1, 161 /* Not Access */ -1 162 }; 163 164 static const char *cc_to_string[16] = { 165 "No Error", 166 "CRC: Last data packet from endpoint contained a CRC error.", 167 "BITSTUFFING: Last data packet from endpoint contained a bit " \ 168 "stuffing violation", 169 "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \ 170 "that did not match the expected value.", 171 "STALL: TD was moved to the Done Queue because the endpoint returned" \ 172 " a STALL PID", 173 "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \ 174 "not provide a handshake (OUT)", 175 "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\ 176 "(IN) or handshake (OUT)", 177 "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \ 178 "value is not defined.", 179 "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \ 180 "either the size of the maximum data packet allowed\n" \ 181 "from the endpoint (found in MaximumPacketSize field\n" \ 182 "of ED) or the remaining buffer size.", 183 "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \ 184 "and that amount was not sufficient to fill the\n" \ 185 "specified buffer", 186 "reserved1", 187 "reserved2", 188 "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \ 189 "than it could be written to system memory", 190 "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \ 191 "system memory fast enough to keep up with data USB " \ 192 "data rate.", 193 "NOT ACCESSED: This code is set by software before the TD is placed" \ 194 "on a list to be processed by the HC.(1)", 195 "NOT ACCESSED: This code is set by software before the TD is placed" \ 196 "on a list to be processed by the HC.(2)", 197 }; 198 199 static inline u32 roothub_a(struct ohci *hc) 200 { return ohci_readl(&hc->regs->roothub.a); } 201 static inline u32 roothub_b(struct ohci *hc) 202 { return ohci_readl(&hc->regs->roothub.b); } 203 static inline u32 roothub_status(struct ohci *hc) 204 { return ohci_readl(&hc->regs->roothub.status); } 205 static inline u32 roothub_portstatus(struct ohci *hc, int i) 206 { return ohci_readl(&hc->regs->roothub.portstatus[i]); } 207 208 /* forward declaration */ 209 static int hc_interrupt(ohci_t *ohci); 210 static void td_submit_job(ohci_t *ohci, struct usb_device *dev, 211 unsigned long pipe, void *buffer, int transfer_len, 212 struct devrequest *setup, urb_priv_t *urb, 213 int interval); 214 static int ep_link(ohci_t * ohci, ed_t * ed); 215 static int ep_unlink(ohci_t * ohci, ed_t * ed); 216 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, 217 unsigned long pipe, int interval, int load); 218 219 /*-------------------------------------------------------------------------*/ 220 221 /* TDs ... */ 222 static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev) 223 { 224 int i; 225 struct td *td; 226 227 td = NULL; 228 for (i = 0; i < NUM_TD; i++) 229 { 230 if (ohci_dev->tds[i].usb_dev == NULL) 231 { 232 td = &ohci_dev->tds[i]; 233 td->usb_dev = usb_dev; 234 break; 235 } 236 } 237 238 return td; 239 } 240 241 static inline void ed_free(struct ed *ed) 242 { 243 ed->usb_dev = NULL; 244 } 245 246 /*-------------------------------------------------------------------------* 247 * URB support functions 248 *-------------------------------------------------------------------------*/ 249 250 /* free HCD-private data associated with this URB */ 251 252 static void urb_free_priv(urb_priv_t *urb) 253 { 254 int i; 255 int last; 256 struct td *td; 257 258 last = urb->length - 1; 259 if (last >= 0) { 260 for (i = 0; i <= last; i++) { 261 td = urb->td[i]; 262 if (td) { 263 td->usb_dev = NULL; 264 urb->td[i] = NULL; 265 } 266 } 267 } 268 free(urb); 269 } 270 271 /*-------------------------------------------------------------------------*/ 272 273 #ifdef DEBUG 274 static int sohci_get_current_frame_number(ohci_t *ohci); 275 276 /* debug| print the main components of an URB 277 * small: 0) header + data packets 1) just header */ 278 279 static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev, 280 unsigned long pipe, void *buffer, int transfer_len, 281 struct devrequest *setup, char *str, int small) 282 { 283 dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", 284 str, 285 sohci_get_current_frame_number(ohci), 286 usb_pipedevice(pipe), 287 usb_pipeendpoint(pipe), 288 usb_pipeout(pipe)? 'O': 'I', 289 usb_pipetype(pipe) < 2 ? \ 290 (usb_pipeint(pipe)? "INTR": "ISOC"): \ 291 (usb_pipecontrol(pipe)? "CTRL": "BULK"), 292 (purb ? purb->actual_length : 0), 293 transfer_len, dev->status); 294 #ifdef OHCI_VERBOSE_DEBUG 295 if (!small) { 296 int i, len; 297 298 if (usb_pipecontrol(pipe)) { 299 printf(__FILE__ ": cmd(8):"); 300 for (i = 0; i < 8 ; i++) 301 printf(" %02x", ((__u8 *) setup) [i]); 302 printf("\n"); 303 } 304 if (transfer_len > 0 && buffer) { 305 printf(__FILE__ ": data(%d/%d):", 306 (purb ? purb->actual_length : 0), 307 transfer_len); 308 len = usb_pipeout(pipe)? transfer_len: 309 (purb ? purb->actual_length : 0); 310 for (i = 0; i < 16 && i < len; i++) 311 printf(" %02x", ((__u8 *) buffer) [i]); 312 printf("%s\n", i < len? "...": ""); 313 } 314 } 315 #endif 316 } 317 318 /* just for debugging; prints non-empty branches of the int ed tree 319 * inclusive iso eds */ 320 void ep_print_int_eds(ohci_t *ohci, char *str) 321 { 322 int i, j; 323 __u32 *ed_p; 324 for (i = 0; i < 32; i++) { 325 j = 5; 326 ed_p = &(ohci->hcca->int_table [i]); 327 if (*ed_p == 0) 328 continue; 329 invalidate_dcache_ed(ed_p); 330 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); 331 while (*ed_p != 0 && j--) { 332 ed_t *ed = (ed_t *)m32_swap(ed_p); 333 invalidate_dcache_ed(ed); 334 printf(" ed: %4x;", ed->hwINFO); 335 ed_p = &ed->hwNextED; 336 } 337 printf("\n"); 338 } 339 } 340 341 static void ohci_dump_intr_mask(char *label, __u32 mask) 342 { 343 dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", 344 label, 345 mask, 346 (mask & OHCI_INTR_MIE) ? " MIE" : "", 347 (mask & OHCI_INTR_OC) ? " OC" : "", 348 (mask & OHCI_INTR_RHSC) ? " RHSC" : "", 349 (mask & OHCI_INTR_FNO) ? " FNO" : "", 350 (mask & OHCI_INTR_UE) ? " UE" : "", 351 (mask & OHCI_INTR_RD) ? " RD" : "", 352 (mask & OHCI_INTR_SF) ? " SF" : "", 353 (mask & OHCI_INTR_WDH) ? " WDH" : "", 354 (mask & OHCI_INTR_SO) ? " SO" : "" 355 ); 356 } 357 358 static void maybe_print_eds(char *label, __u32 value) 359 { 360 ed_t *edp = (ed_t *)value; 361 362 if (value) { 363 dbg("%s %08x", label, value); 364 invalidate_dcache_ed(edp); 365 dbg("%08x", edp->hwINFO); 366 dbg("%08x", edp->hwTailP); 367 dbg("%08x", edp->hwHeadP); 368 dbg("%08x", edp->hwNextED); 369 } 370 } 371 372 static char *hcfs2string(int state) 373 { 374 switch (state) { 375 case OHCI_USB_RESET: return "reset"; 376 case OHCI_USB_RESUME: return "resume"; 377 case OHCI_USB_OPER: return "operational"; 378 case OHCI_USB_SUSPEND: return "suspend"; 379 } 380 return "?"; 381 } 382 383 /* dump control and status registers */ 384 static void ohci_dump_status(ohci_t *controller) 385 { 386 struct ohci_regs *regs = controller->regs; 387 __u32 temp; 388 389 temp = ohci_readl(®s->revision) & 0xff; 390 if (temp != 0x10) 391 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); 392 393 temp = ohci_readl(®s->control); 394 dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, 395 (temp & OHCI_CTRL_RWE) ? " RWE" : "", 396 (temp & OHCI_CTRL_RWC) ? " RWC" : "", 397 (temp & OHCI_CTRL_IR) ? " IR" : "", 398 hcfs2string(temp & OHCI_CTRL_HCFS), 399 (temp & OHCI_CTRL_BLE) ? " BLE" : "", 400 (temp & OHCI_CTRL_CLE) ? " CLE" : "", 401 (temp & OHCI_CTRL_IE) ? " IE" : "", 402 (temp & OHCI_CTRL_PLE) ? " PLE" : "", 403 temp & OHCI_CTRL_CBSR 404 ); 405 406 temp = ohci_readl(®s->cmdstatus); 407 dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, 408 (temp & OHCI_SOC) >> 16, 409 (temp & OHCI_OCR) ? " OCR" : "", 410 (temp & OHCI_BLF) ? " BLF" : "", 411 (temp & OHCI_CLF) ? " CLF" : "", 412 (temp & OHCI_HCR) ? " HCR" : "" 413 ); 414 415 ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus)); 416 ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable)); 417 418 maybe_print_eds("ed_periodcurrent", 419 ohci_readl(®s->ed_periodcurrent)); 420 421 maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead)); 422 maybe_print_eds("ed_controlcurrent", 423 ohci_readl(®s->ed_controlcurrent)); 424 425 maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead)); 426 maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent)); 427 428 maybe_print_eds("donehead", ohci_readl(®s->donehead)); 429 } 430 431 static void ohci_dump_roothub(ohci_t *controller, int verbose) 432 { 433 __u32 temp, ndp, i; 434 435 temp = roothub_a(controller); 436 ndp = (temp & RH_A_NDP); 437 #ifdef CONFIG_AT91C_PQFP_UHPBUG 438 ndp = (ndp == 2) ? 1:0; 439 #endif 440 if (verbose) { 441 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, 442 ((temp & RH_A_POTPGT) >> 24) & 0xff, 443 (temp & RH_A_NOCP) ? " NOCP" : "", 444 (temp & RH_A_OCPM) ? " OCPM" : "", 445 (temp & RH_A_DT) ? " DT" : "", 446 (temp & RH_A_NPS) ? " NPS" : "", 447 (temp & RH_A_PSM) ? " PSM" : "", 448 ndp 449 ); 450 temp = roothub_b(controller); 451 dbg("roothub.b: %08x PPCM=%04x DR=%04x", 452 temp, 453 (temp & RH_B_PPCM) >> 16, 454 (temp & RH_B_DR) 455 ); 456 temp = roothub_status(controller); 457 dbg("roothub.status: %08x%s%s%s%s%s%s", 458 temp, 459 (temp & RH_HS_CRWE) ? " CRWE" : "", 460 (temp & RH_HS_OCIC) ? " OCIC" : "", 461 (temp & RH_HS_LPSC) ? " LPSC" : "", 462 (temp & RH_HS_DRWE) ? " DRWE" : "", 463 (temp & RH_HS_OCI) ? " OCI" : "", 464 (temp & RH_HS_LPS) ? " LPS" : "" 465 ); 466 } 467 468 for (i = 0; i < ndp; i++) { 469 temp = roothub_portstatus(controller, i); 470 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", 471 i, 472 temp, 473 (temp & RH_PS_PRSC) ? " PRSC" : "", 474 (temp & RH_PS_OCIC) ? " OCIC" : "", 475 (temp & RH_PS_PSSC) ? " PSSC" : "", 476 (temp & RH_PS_PESC) ? " PESC" : "", 477 (temp & RH_PS_CSC) ? " CSC" : "", 478 479 (temp & RH_PS_LSDA) ? " LSDA" : "", 480 (temp & RH_PS_PPS) ? " PPS" : "", 481 (temp & RH_PS_PRS) ? " PRS" : "", 482 (temp & RH_PS_POCI) ? " POCI" : "", 483 (temp & RH_PS_PSS) ? " PSS" : "", 484 485 (temp & RH_PS_PES) ? " PES" : "", 486 (temp & RH_PS_CCS) ? " CCS" : "" 487 ); 488 } 489 } 490 491 static void ohci_dump(ohci_t *controller, int verbose) 492 { 493 dbg("OHCI controller usb-%s state", controller->slot_name); 494 495 /* dumps some of the state we know about */ 496 ohci_dump_status(controller); 497 if (verbose) 498 ep_print_int_eds(controller, "hcca"); 499 invalidate_dcache_hcca(controller->hcca); 500 dbg("hcca frame #%04x", controller->hcca->frame_no); 501 ohci_dump_roothub(controller, 1); 502 } 503 #endif /* DEBUG */ 504 505 /*-------------------------------------------------------------------------* 506 * Interface functions (URB) 507 *-------------------------------------------------------------------------*/ 508 509 /* get a transfer request */ 510 511 int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb, 512 struct devrequest *setup) 513 { 514 ed_t *ed; 515 urb_priv_t *purb_priv = urb; 516 int i, size = 0; 517 struct usb_device *dev = urb->dev; 518 unsigned long pipe = urb->pipe; 519 void *buffer = urb->transfer_buffer; 520 int transfer_len = urb->transfer_buffer_length; 521 int interval = urb->interval; 522 523 /* when controller's hung, permit only roothub cleanup attempts 524 * such as powering down ports */ 525 if (ohci->disabled) { 526 err("sohci_submit_job: EPIPE"); 527 return -1; 528 } 529 530 /* we're about to begin a new transaction here so mark the 531 * URB unfinished */ 532 urb->finished = 0; 533 534 /* every endpoint has a ed, locate and fill it */ 535 ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1); 536 if (!ed) { 537 err("sohci_submit_job: ENOMEM"); 538 return -1; 539 } 540 541 /* for the private part of the URB we need the number of TDs (size) */ 542 switch (usb_pipetype(pipe)) { 543 case PIPE_BULK: /* one TD for every 4096 Byte */ 544 size = (transfer_len - 1) / 4096 + 1; 545 break; 546 case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ 547 size = (transfer_len == 0)? 2: 548 (transfer_len - 1) / 4096 + 3; 549 break; 550 case PIPE_INTERRUPT: /* 1 TD */ 551 size = 1; 552 break; 553 } 554 555 ed->purb = urb; 556 557 if (size >= (N_URB_TD - 1)) { 558 err("need %d TDs, only have %d", size, N_URB_TD); 559 return -1; 560 } 561 purb_priv->pipe = pipe; 562 563 /* fill the private part of the URB */ 564 purb_priv->length = size; 565 purb_priv->ed = ed; 566 purb_priv->actual_length = 0; 567 568 /* allocate the TDs */ 569 /* note that td[0] was allocated in ep_add_ed */ 570 for (i = 0; i < size; i++) { 571 purb_priv->td[i] = td_alloc(ohci_dev, dev); 572 if (!purb_priv->td[i]) { 573 purb_priv->length = i; 574 urb_free_priv(purb_priv); 575 err("sohci_submit_job: ENOMEM"); 576 return -1; 577 } 578 } 579 580 if (ed->state == ED_NEW || (ed->state & ED_DEL)) { 581 urb_free_priv(purb_priv); 582 err("sohci_submit_job: EINVAL"); 583 return -1; 584 } 585 586 /* link the ed into a chain if is not already */ 587 if (ed->state != ED_OPER) 588 ep_link(ohci, ed); 589 590 /* fill the TDs and link it to the ed */ 591 td_submit_job(ohci, dev, pipe, buffer, transfer_len, 592 setup, purb_priv, interval); 593 594 return 0; 595 } 596 597 /*-------------------------------------------------------------------------*/ 598 599 #ifdef DEBUG 600 /* tell us the current USB frame number */ 601 static int sohci_get_current_frame_number(ohci_t *ohci) 602 { 603 invalidate_dcache_hcca(ohci->hcca); 604 return m16_swap(ohci->hcca->frame_no); 605 } 606 #endif 607 608 /*-------------------------------------------------------------------------* 609 * ED handling functions 610 *-------------------------------------------------------------------------*/ 611 612 /* search for the right branch to insert an interrupt ed into the int tree 613 * do some load ballancing; 614 * returns the branch and 615 * sets the interval to interval = 2^integer (ld (interval)) */ 616 617 static int ep_int_ballance(ohci_t *ohci, int interval, int load) 618 { 619 int i, branch = 0; 620 621 /* search for the least loaded interrupt endpoint 622 * branch of all 32 branches 623 */ 624 for (i = 0; i < 32; i++) 625 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) 626 branch = i; 627 628 branch = branch % interval; 629 for (i = branch; i < 32; i += interval) 630 ohci->ohci_int_load [i] += load; 631 632 return branch; 633 } 634 635 /*-------------------------------------------------------------------------*/ 636 637 /* 2^int( ld (inter)) */ 638 639 static int ep_2_n_interval(int inter) 640 { 641 int i; 642 for (i = 0; ((inter >> i) > 1) && (i < 5); i++); 643 return 1 << i; 644 } 645 646 /*-------------------------------------------------------------------------*/ 647 648 /* the int tree is a binary tree 649 * in order to process it sequentially the indexes of the branches have to 650 * be mapped the mapping reverses the bits of a word of num_bits length */ 651 static int ep_rev(int num_bits, int word) 652 { 653 int i, wout = 0; 654 655 for (i = 0; i < num_bits; i++) 656 wout |= (((word >> i) & 1) << (num_bits - i - 1)); 657 return wout; 658 } 659 660 /*-------------------------------------------------------------------------* 661 * ED handling functions 662 *-------------------------------------------------------------------------*/ 663 664 /* link an ed into one of the HC chains */ 665 666 static int ep_link(ohci_t *ohci, ed_t *edi) 667 { 668 volatile ed_t *ed = edi; 669 int int_branch; 670 int i; 671 int inter; 672 int interval; 673 int load; 674 __u32 *ed_p; 675 676 ed->state = ED_OPER; 677 ed->int_interval = 0; 678 679 switch (ed->type) { 680 case PIPE_CONTROL: 681 ed->hwNextED = 0; 682 flush_dcache_ed(ed); 683 if (ohci->ed_controltail == NULL) 684 ohci_writel((uintptr_t)ed, &ohci->regs->ed_controlhead); 685 else 686 ohci->ed_controltail->hwNextED = 687 m32_swap((unsigned long)ed); 688 689 ed->ed_prev = ohci->ed_controltail; 690 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && 691 !ohci->ed_rm_list[1] && !ohci->sleeping) { 692 ohci->hc_control |= OHCI_CTRL_CLE; 693 ohci_writel(ohci->hc_control, &ohci->regs->control); 694 } 695 ohci->ed_controltail = edi; 696 break; 697 698 case PIPE_BULK: 699 ed->hwNextED = 0; 700 flush_dcache_ed(ed); 701 if (ohci->ed_bulktail == NULL) 702 ohci_writel((uintptr_t)ed, &ohci->regs->ed_bulkhead); 703 else 704 ohci->ed_bulktail->hwNextED = 705 m32_swap((unsigned long)ed); 706 707 ed->ed_prev = ohci->ed_bulktail; 708 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && 709 !ohci->ed_rm_list[1] && !ohci->sleeping) { 710 ohci->hc_control |= OHCI_CTRL_BLE; 711 ohci_writel(ohci->hc_control, &ohci->regs->control); 712 } 713 ohci->ed_bulktail = edi; 714 break; 715 716 case PIPE_INTERRUPT: 717 load = ed->int_load; 718 interval = ep_2_n_interval(ed->int_period); 719 ed->int_interval = interval; 720 int_branch = ep_int_ballance(ohci, interval, load); 721 ed->int_branch = int_branch; 722 723 for (i = 0; i < ep_rev(6, interval); i += inter) { 724 inter = 1; 725 for (ed_p = &(ohci->hcca->int_table[\ 726 ep_rev(5, i) + int_branch]); 727 (*ed_p != 0) && 728 (((ed_t *)ed_p)->int_interval >= interval); 729 ed_p = &(((ed_t *)ed_p)->hwNextED)) 730 inter = ep_rev(6, 731 ((ed_t *)ed_p)->int_interval); 732 ed->hwNextED = *ed_p; 733 flush_dcache_ed(ed); 734 *ed_p = m32_swap((unsigned long)ed); 735 flush_dcache_hcca(ohci->hcca); 736 } 737 break; 738 } 739 return 0; 740 } 741 742 /*-------------------------------------------------------------------------*/ 743 744 /* scan the periodic table to find and unlink this ED */ 745 static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, 746 unsigned index, unsigned period) 747 { 748 __maybe_unused unsigned long aligned_ed_p; 749 750 for (; index < NUM_INTS; index += period) { 751 __u32 *ed_p = &ohci->hcca->int_table [index]; 752 753 /* ED might have been unlinked through another path */ 754 while (*ed_p != 0) { 755 if (((struct ed *)(uintptr_t) 756 m32_swap((unsigned long)ed_p)) == ed) { 757 *ed_p = ed->hwNextED; 758 aligned_ed_p = (unsigned long)ed_p; 759 aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1); 760 flush_dcache_range(aligned_ed_p, 761 aligned_ed_p + ARCH_DMA_MINALIGN); 762 break; 763 } 764 ed_p = &(((struct ed *)(uintptr_t) 765 m32_swap((unsigned long)ed_p))->hwNextED); 766 } 767 } 768 } 769 770 /* unlink an ed from one of the HC chains. 771 * just the link to the ed is unlinked. 772 * the link from the ed still points to another operational ed or 0 773 * so the HC can eventually finish the processing of the unlinked ed */ 774 775 static int ep_unlink(ohci_t *ohci, ed_t *edi) 776 { 777 volatile ed_t *ed = edi; 778 int i; 779 780 ed->hwINFO |= m32_swap(OHCI_ED_SKIP); 781 flush_dcache_ed(ed); 782 783 switch (ed->type) { 784 case PIPE_CONTROL: 785 if (ed->ed_prev == NULL) { 786 if (!ed->hwNextED) { 787 ohci->hc_control &= ~OHCI_CTRL_CLE; 788 ohci_writel(ohci->hc_control, 789 &ohci->regs->control); 790 } 791 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), 792 &ohci->regs->ed_controlhead); 793 } else { 794 ed->ed_prev->hwNextED = ed->hwNextED; 795 flush_dcache_ed(ed->ed_prev); 796 } 797 if (ohci->ed_controltail == ed) { 798 ohci->ed_controltail = ed->ed_prev; 799 } else { 800 ((ed_t *)(uintptr_t)m32_swap( 801 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; 802 } 803 break; 804 805 case PIPE_BULK: 806 if (ed->ed_prev == NULL) { 807 if (!ed->hwNextED) { 808 ohci->hc_control &= ~OHCI_CTRL_BLE; 809 ohci_writel(ohci->hc_control, 810 &ohci->regs->control); 811 } 812 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), 813 &ohci->regs->ed_bulkhead); 814 } else { 815 ed->ed_prev->hwNextED = ed->hwNextED; 816 flush_dcache_ed(ed->ed_prev); 817 } 818 if (ohci->ed_bulktail == ed) { 819 ohci->ed_bulktail = ed->ed_prev; 820 } else { 821 ((ed_t *)(uintptr_t)m32_swap( 822 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; 823 } 824 break; 825 826 case PIPE_INTERRUPT: 827 periodic_unlink(ohci, ed, 0, 1); 828 for (i = ed->int_branch; i < 32; i += ed->int_interval) 829 ohci->ohci_int_load[i] -= ed->int_load; 830 break; 831 } 832 ed->state = ED_UNLINK; 833 return 0; 834 } 835 836 /*-------------------------------------------------------------------------*/ 837 838 /* add/reinit an endpoint; this should be done once at the 839 * usb_set_configuration command, but the USB stack is a little bit 840 * stateless so we do it at every transaction if the state of the ed 841 * is ED_NEW then a dummy td is added and the state is changed to 842 * ED_UNLINK in all other cases the state is left unchanged the ed 843 * info fields are setted anyway even though most of them should not 844 * change 845 */ 846 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, 847 unsigned long pipe, int interval, int load) 848 { 849 td_t *td; 850 ed_t *ed_ret; 851 volatile ed_t *ed; 852 853 ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) | 854 (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; 855 856 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { 857 err("ep_add_ed: pending delete"); 858 /* pending delete request */ 859 return NULL; 860 } 861 862 if (ed->state == ED_NEW) { 863 /* dummy td; end of td list for ed */ 864 td = td_alloc(ohci_dev, usb_dev); 865 ed->hwTailP = m32_swap((unsigned long)td); 866 ed->hwHeadP = ed->hwTailP; 867 ed->state = ED_UNLINK; 868 ed->type = usb_pipetype(pipe); 869 ohci_dev->ed_cnt++; 870 } 871 872 ed->hwINFO = m32_swap(usb_pipedevice(pipe) 873 | usb_pipeendpoint(pipe) << 7 874 | (usb_pipeisoc(pipe)? 0x8000: 0) 875 | (usb_pipecontrol(pipe)? 0: \ 876 (usb_pipeout(pipe)? 0x800: 0x1000)) 877 | (usb_dev->speed == USB_SPEED_LOW) << 13 878 | usb_maxpacket(usb_dev, pipe) << 16); 879 880 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { 881 ed->int_period = interval; 882 ed->int_load = load; 883 } 884 885 flush_dcache_ed(ed); 886 887 return ed_ret; 888 } 889 890 /*-------------------------------------------------------------------------* 891 * TD handling functions 892 *-------------------------------------------------------------------------*/ 893 894 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ 895 896 static void td_fill(ohci_t *ohci, unsigned int info, 897 void *data, int len, 898 struct usb_device *dev, int index, urb_priv_t *urb_priv) 899 { 900 volatile td_t *td, *td_pt; 901 #ifdef OHCI_FILL_TRACE 902 int i; 903 #endif 904 905 if (index > urb_priv->length) { 906 err("index > length"); 907 return; 908 } 909 /* use this td as the next dummy */ 910 td_pt = urb_priv->td [index]; 911 td_pt->hwNextTD = 0; 912 flush_dcache_td(td_pt); 913 914 /* fill the old dummy TD */ 915 td = urb_priv->td [index] = 916 (td_t *)(uintptr_t) 917 (m32_swap(urb_priv->ed->hwTailP) & ~0xf); 918 919 td->ed = urb_priv->ed; 920 td->next_dl_td = NULL; 921 td->index = index; 922 td->data = (uintptr_t)data; 923 #ifdef OHCI_FILL_TRACE 924 if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { 925 for (i = 0; i < len; i++) 926 printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); 927 printf("\n"); 928 } 929 #endif 930 if (!len) 931 data = 0; 932 933 td->hwINFO = m32_swap(info); 934 td->hwCBP = m32_swap((unsigned long)data); 935 if (data) 936 td->hwBE = m32_swap((unsigned long)(data + len - 1)); 937 else 938 td->hwBE = 0; 939 940 td->hwNextTD = m32_swap((unsigned long)td_pt); 941 flush_dcache_td(td); 942 943 /* append to queue */ 944 td->ed->hwTailP = td->hwNextTD; 945 flush_dcache_ed(td->ed); 946 } 947 948 /*-------------------------------------------------------------------------*/ 949 950 /* prepare all TDs of a transfer */ 951 952 static void td_submit_job(ohci_t *ohci, struct usb_device *dev, 953 unsigned long pipe, void *buffer, int transfer_len, 954 struct devrequest *setup, urb_priv_t *urb, 955 int interval) 956 { 957 int data_len = transfer_len; 958 void *data; 959 int cnt = 0; 960 __u32 info = 0; 961 unsigned int toggle = 0; 962 963 flush_dcache_buffer(buffer, data_len); 964 965 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle 966 * bits for resetting */ 967 if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { 968 toggle = TD_T_TOGGLE; 969 } else { 970 toggle = TD_T_DATA0; 971 usb_settoggle(dev, usb_pipeendpoint(pipe), 972 usb_pipeout(pipe), 1); 973 } 974 urb->td_cnt = 0; 975 if (data_len) 976 data = buffer; 977 else 978 data = 0; 979 980 switch (usb_pipetype(pipe)) { 981 case PIPE_BULK: 982 info = usb_pipeout(pipe)? 983 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; 984 while (data_len > 4096) { 985 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), 986 data, 4096, dev, cnt, urb); 987 data += 4096; data_len -= 4096; cnt++; 988 } 989 info = usb_pipeout(pipe)? 990 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; 991 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 992 data_len, dev, cnt, urb); 993 cnt++; 994 995 if (!ohci->sleeping) { 996 /* start bulk list */ 997 ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus); 998 } 999 break; 1000 1001 case PIPE_CONTROL: 1002 /* Setup phase */ 1003 info = TD_CC | TD_DP_SETUP | TD_T_DATA0; 1004 flush_dcache_buffer(setup, 8); 1005 td_fill(ohci, info, setup, 8, dev, cnt++, urb); 1006 1007 /* Optional Data phase */ 1008 if (data_len > 0) { 1009 info = usb_pipeout(pipe)? 1010 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : 1011 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; 1012 /* NOTE: mishandles transfers >8K, some >4K */ 1013 td_fill(ohci, info, data, data_len, dev, cnt++, urb); 1014 } 1015 1016 /* Status phase */ 1017 info = (usb_pipeout(pipe) || data_len == 0) ? 1018 TD_CC | TD_DP_IN | TD_T_DATA1: 1019 TD_CC | TD_DP_OUT | TD_T_DATA1; 1020 td_fill(ohci, info, data, 0, dev, cnt++, urb); 1021 1022 if (!ohci->sleeping) { 1023 /* start Control list */ 1024 ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus); 1025 } 1026 break; 1027 1028 case PIPE_INTERRUPT: 1029 info = usb_pipeout(urb->pipe)? 1030 TD_CC | TD_DP_OUT | toggle: 1031 TD_CC | TD_R | TD_DP_IN | toggle; 1032 td_fill(ohci, info, data, data_len, dev, cnt++, urb); 1033 break; 1034 } 1035 if (urb->length != cnt) 1036 dbg("TD LENGTH %d != CNT %d", urb->length, cnt); 1037 } 1038 1039 /*-------------------------------------------------------------------------* 1040 * Done List handling functions 1041 *-------------------------------------------------------------------------*/ 1042 1043 /* calculate the transfer length and update the urb */ 1044 1045 static void dl_transfer_length(td_t *td) 1046 { 1047 __u32 tdBE, tdCBP; 1048 urb_priv_t *lurb_priv = td->ed->purb; 1049 1050 tdBE = m32_swap(td->hwBE); 1051 tdCBP = m32_swap(td->hwCBP); 1052 1053 if (!(usb_pipecontrol(lurb_priv->pipe) && 1054 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { 1055 if (tdBE != 0) { 1056 if (td->hwCBP == 0) 1057 lurb_priv->actual_length += tdBE - td->data + 1; 1058 else 1059 lurb_priv->actual_length += tdCBP - td->data; 1060 } 1061 } 1062 } 1063 1064 /*-------------------------------------------------------------------------*/ 1065 static void check_status(td_t *td_list) 1066 { 1067 urb_priv_t *lurb_priv = td_list->ed->purb; 1068 int urb_len = lurb_priv->length; 1069 __u32 *phwHeadP = &td_list->ed->hwHeadP; 1070 int cc; 1071 1072 cc = TD_CC_GET(m32_swap(td_list->hwINFO)); 1073 if (cc) { 1074 err(" USB-error: %s (%x)", cc_to_string[cc], cc); 1075 1076 invalidate_dcache_ed(td_list->ed); 1077 if (*phwHeadP & m32_swap(0x1)) { 1078 if (lurb_priv && 1079 ((td_list->index + 1) < urb_len)) { 1080 *phwHeadP = 1081 (lurb_priv->td[urb_len - 1]->hwNextTD &\ 1082 m32_swap(0xfffffff0)) | 1083 (*phwHeadP & m32_swap(0x2)); 1084 1085 lurb_priv->td_cnt += urb_len - 1086 td_list->index - 1; 1087 } else 1088 *phwHeadP &= m32_swap(0xfffffff2); 1089 flush_dcache_ed(td_list->ed); 1090 } 1091 } 1092 } 1093 1094 /* replies to the request have to be on a FIFO basis so 1095 * we reverse the reversed done-list */ 1096 static td_t *dl_reverse_done_list(ohci_t *ohci) 1097 { 1098 uintptr_t td_list_hc; 1099 td_t *td_rev = NULL; 1100 td_t *td_list = NULL; 1101 1102 invalidate_dcache_hcca(ohci->hcca); 1103 td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; 1104 ohci->hcca->done_head = 0; 1105 flush_dcache_hcca(ohci->hcca); 1106 1107 while (td_list_hc) { 1108 td_list = (td_t *)td_list_hc; 1109 invalidate_dcache_td(td_list); 1110 check_status(td_list); 1111 td_list->next_dl_td = td_rev; 1112 td_rev = td_list; 1113 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; 1114 } 1115 return td_list; 1116 } 1117 1118 /*-------------------------------------------------------------------------*/ 1119 /*-------------------------------------------------------------------------*/ 1120 1121 static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) 1122 { 1123 if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) 1124 urb->finished = 1; 1125 else 1126 dbg("finish_urb: strange.., ED state %x, \n", status); 1127 } 1128 1129 /* 1130 * Used to take back a TD from the host controller. This would normally be 1131 * called from within dl_done_list, however it may be called directly if the 1132 * HC no longer sees the TD and it has not appeared on the donelist (after 1133 * two frames). This bug has been observed on ZF Micro systems. 1134 */ 1135 static int takeback_td(ohci_t *ohci, td_t *td_list) 1136 { 1137 ed_t *ed; 1138 int cc; 1139 int stat = 0; 1140 /* urb_t *urb; */ 1141 urb_priv_t *lurb_priv; 1142 __u32 tdINFO, edHeadP, edTailP; 1143 1144 invalidate_dcache_td(td_list); 1145 tdINFO = m32_swap(td_list->hwINFO); 1146 1147 ed = td_list->ed; 1148 lurb_priv = ed->purb; 1149 1150 dl_transfer_length(td_list); 1151 1152 lurb_priv->td_cnt++; 1153 1154 /* error code of transfer */ 1155 cc = TD_CC_GET(tdINFO); 1156 if (cc) { 1157 err("USB-error: %s (%x)", cc_to_string[cc], cc); 1158 stat = cc_to_error[cc]; 1159 } 1160 1161 /* see if this done list makes for all TD's of current URB, 1162 * and mark the URB finished if so */ 1163 if (lurb_priv->td_cnt == lurb_priv->length) 1164 finish_urb(ohci, lurb_priv, ed->state); 1165 1166 dbg("dl_done_list: processing TD %x, len %x\n", 1167 lurb_priv->td_cnt, lurb_priv->length); 1168 1169 if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { 1170 invalidate_dcache_ed(ed); 1171 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; 1172 edTailP = m32_swap(ed->hwTailP); 1173 1174 /* unlink eds if they are not busy */ 1175 if ((edHeadP == edTailP) && (ed->state == ED_OPER)) 1176 ep_unlink(ohci, ed); 1177 } 1178 return stat; 1179 } 1180 1181 static int dl_done_list(ohci_t *ohci) 1182 { 1183 int stat = 0; 1184 td_t *td_list = dl_reverse_done_list(ohci); 1185 1186 while (td_list) { 1187 td_t *td_next = td_list->next_dl_td; 1188 stat = takeback_td(ohci, td_list); 1189 td_list = td_next; 1190 } 1191 return stat; 1192 } 1193 1194 /*-------------------------------------------------------------------------* 1195 * Virtual Root Hub 1196 *-------------------------------------------------------------------------*/ 1197 1198 #include <usbroothubdes.h> 1199 1200 /* Hub class-specific descriptor is constructed dynamically */ 1201 1202 /*-------------------------------------------------------------------------*/ 1203 1204 #define OK(x) len = (x); break 1205 #ifdef DEBUG 1206 #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \ 1207 &ohci->regs->roothub.status); } 1208 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ 1209 (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); } 1210 #else 1211 #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status) 1212 #define WR_RH_PORTSTAT(x) ohci_writel((x), \ 1213 &ohci->regs->roothub.portstatus[wIndex-1]) 1214 #endif 1215 #define RD_RH_STAT roothub_status(ohci) 1216 #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1) 1217 1218 /* request to virtual root hub */ 1219 1220 int rh_check_port_status(ohci_t *controller) 1221 { 1222 __u32 temp, ndp, i; 1223 int res; 1224 1225 res = -1; 1226 temp = roothub_a(controller); 1227 ndp = (temp & RH_A_NDP); 1228 #ifdef CONFIG_AT91C_PQFP_UHPBUG 1229 ndp = (ndp == 2) ? 1:0; 1230 #endif 1231 for (i = 0; i < ndp; i++) { 1232 temp = roothub_portstatus(controller, i); 1233 /* check for a device disconnect */ 1234 if (((temp & (RH_PS_PESC | RH_PS_CSC)) == 1235 (RH_PS_PESC | RH_PS_CSC)) && 1236 ((temp & RH_PS_CCS) == 0)) { 1237 res = i; 1238 break; 1239 } 1240 } 1241 return res; 1242 } 1243 1244 static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev, 1245 unsigned long pipe, void *buffer, int transfer_len, 1246 struct devrequest *cmd) 1247 { 1248 void *data = buffer; 1249 int leni = transfer_len; 1250 int len = 0; 1251 int stat = 0; 1252 __u16 bmRType_bReq; 1253 __u16 wValue; 1254 __u16 wIndex; 1255 __u16 wLength; 1256 ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32)); 1257 1258 #ifdef DEBUG 1259 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, 1260 cmd, "SUB(rh)", usb_pipein(pipe)); 1261 #else 1262 ohci_mdelay(1); 1263 #endif 1264 if (usb_pipeint(pipe)) { 1265 info("Root-Hub submit IRQ: NOT implemented"); 1266 return 0; 1267 } 1268 1269 bmRType_bReq = cmd->requesttype | (cmd->request << 8); 1270 wValue = le16_to_cpu(cmd->value); 1271 wIndex = le16_to_cpu(cmd->index); 1272 wLength = le16_to_cpu(cmd->length); 1273 1274 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", 1275 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); 1276 1277 switch (bmRType_bReq) { 1278 /* Request Destination: 1279 without flags: Device, 1280 RH_INTERFACE: interface, 1281 RH_ENDPOINT: endpoint, 1282 RH_CLASS means HUB here, 1283 RH_OTHER | RH_CLASS almost ever means HUB_PORT here 1284 */ 1285 1286 case RH_GET_STATUS: 1287 *(u16 *)databuf = cpu_to_le16(1); 1288 OK(2); 1289 case RH_GET_STATUS | RH_INTERFACE: 1290 *(u16 *)databuf = cpu_to_le16(0); 1291 OK(2); 1292 case RH_GET_STATUS | RH_ENDPOINT: 1293 *(u16 *)databuf = cpu_to_le16(0); 1294 OK(2); 1295 case RH_GET_STATUS | RH_CLASS: 1296 *(u32 *)databuf = cpu_to_le32( 1297 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); 1298 OK(4); 1299 case RH_GET_STATUS | RH_OTHER | RH_CLASS: 1300 *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT); 1301 OK(4); 1302 1303 case RH_CLEAR_FEATURE | RH_ENDPOINT: 1304 switch (wValue) { 1305 case (RH_ENDPOINT_STALL): 1306 OK(0); 1307 } 1308 break; 1309 1310 case RH_CLEAR_FEATURE | RH_CLASS: 1311 switch (wValue) { 1312 case RH_C_HUB_LOCAL_POWER: 1313 OK(0); 1314 case (RH_C_HUB_OVER_CURRENT): 1315 WR_RH_STAT(RH_HS_OCIC); 1316 OK(0); 1317 } 1318 break; 1319 1320 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: 1321 switch (wValue) { 1322 case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); 1323 case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); 1324 case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); 1325 case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); 1326 case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); 1327 case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); 1328 case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); 1329 case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); 1330 } 1331 break; 1332 1333 case RH_SET_FEATURE | RH_OTHER | RH_CLASS: 1334 switch (wValue) { 1335 case (RH_PORT_SUSPEND): 1336 WR_RH_PORTSTAT(RH_PS_PSS); OK(0); 1337 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ 1338 if (RD_RH_PORTSTAT & RH_PS_CCS) 1339 WR_RH_PORTSTAT(RH_PS_PRS); 1340 OK(0); 1341 case (RH_PORT_POWER): 1342 WR_RH_PORTSTAT(RH_PS_PPS); 1343 OK(0); 1344 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ 1345 if (RD_RH_PORTSTAT & RH_PS_CCS) 1346 WR_RH_PORTSTAT(RH_PS_PES); 1347 OK(0); 1348 } 1349 break; 1350 1351 case RH_SET_ADDRESS: 1352 ohci->rh.devnum = wValue; 1353 OK(0); 1354 1355 case RH_GET_DESCRIPTOR: 1356 switch ((wValue & 0xff00) >> 8) { 1357 case (0x01): /* device descriptor */ 1358 len = min_t(unsigned int, 1359 leni, 1360 min_t(unsigned int, 1361 sizeof(root_hub_dev_des), 1362 wLength)); 1363 databuf = root_hub_dev_des; OK(len); 1364 case (0x02): /* configuration descriptor */ 1365 len = min_t(unsigned int, 1366 leni, 1367 min_t(unsigned int, 1368 sizeof(root_hub_config_des), 1369 wLength)); 1370 databuf = root_hub_config_des; OK(len); 1371 case (0x03): /* string descriptors */ 1372 if (wValue == 0x0300) { 1373 len = min_t(unsigned int, 1374 leni, 1375 min_t(unsigned int, 1376 sizeof(root_hub_str_index0), 1377 wLength)); 1378 databuf = root_hub_str_index0; 1379 OK(len); 1380 } 1381 if (wValue == 0x0301) { 1382 len = min_t(unsigned int, 1383 leni, 1384 min_t(unsigned int, 1385 sizeof(root_hub_str_index1), 1386 wLength)); 1387 databuf = root_hub_str_index1; 1388 OK(len); 1389 } 1390 default: 1391 stat = USB_ST_STALLED; 1392 } 1393 break; 1394 1395 case RH_GET_DESCRIPTOR | RH_CLASS: 1396 { 1397 __u32 temp = roothub_a(ohci); 1398 1399 databuf[0] = 9; /* min length; */ 1400 databuf[1] = 0x29; 1401 databuf[2] = temp & RH_A_NDP; 1402 #ifdef CONFIG_AT91C_PQFP_UHPBUG 1403 databuf[2] = (databuf[2] == 2) ? 1 : 0; 1404 #endif 1405 databuf[3] = 0; 1406 if (temp & RH_A_PSM) /* per-port power switching? */ 1407 databuf[3] |= 0x1; 1408 if (temp & RH_A_NOCP) /* no overcurrent reporting? */ 1409 databuf[3] |= 0x10; 1410 else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */ 1411 databuf[3] |= 0x8; 1412 1413 databuf[4] = 0; 1414 databuf[5] = (temp & RH_A_POTPGT) >> 24; 1415 databuf[6] = 0; 1416 temp = roothub_b(ohci); 1417 databuf[7] = temp & RH_B_DR; 1418 if (databuf[2] < 7) { 1419 databuf[8] = 0xff; 1420 } else { 1421 databuf[0] += 2; 1422 databuf[8] = (temp & RH_B_DR) >> 8; 1423 databuf[10] = databuf[9] = 0xff; 1424 } 1425 1426 len = min_t(unsigned int, leni, 1427 min_t(unsigned int, databuf[0], wLength)); 1428 OK(len); 1429 } 1430 1431 case RH_GET_CONFIGURATION: 1432 databuf[0] = 0x01; 1433 OK(1); 1434 1435 case RH_SET_CONFIGURATION: 1436 WR_RH_STAT(0x10000); 1437 OK(0); 1438 1439 default: 1440 dbg("unsupported root hub command"); 1441 stat = USB_ST_STALLED; 1442 } 1443 1444 #ifdef DEBUG 1445 ohci_dump_roothub(ohci, 1); 1446 #else 1447 ohci_mdelay(1); 1448 #endif 1449 1450 len = min_t(int, len, leni); 1451 if (data != databuf) 1452 memcpy(data, databuf, len); 1453 dev->act_len = len; 1454 dev->status = stat; 1455 1456 #ifdef DEBUG 1457 pkt_print(ohci, NULL, dev, pipe, buffer, 1458 transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); 1459 #else 1460 ohci_mdelay(1); 1461 #endif 1462 1463 return stat; 1464 } 1465 1466 /*-------------------------------------------------------------------------*/ 1467 1468 static ohci_dev_t *ohci_get_ohci_dev(ohci_t *ohci, int devnum, int intr) 1469 { 1470 int i; 1471 1472 if (!intr) 1473 return &ohci->ohci_dev; 1474 1475 /* First see if we already have an ohci_dev for this dev. */ 1476 for (i = 0; i < NUM_INT_DEVS; i++) { 1477 if (ohci->int_dev[i].devnum == devnum) 1478 return &ohci->int_dev[i]; 1479 } 1480 1481 /* If not then find a free one. */ 1482 for (i = 0; i < NUM_INT_DEVS; i++) { 1483 if (ohci->int_dev[i].devnum == -1) { 1484 ohci->int_dev[i].devnum = devnum; 1485 return &ohci->int_dev[i]; 1486 } 1487 } 1488 1489 printf("ohci: Error out of ohci_devs for interrupt endpoints\n"); 1490 return NULL; 1491 } 1492 1493 /* common code for handling submit messages - used for all but root hub */ 1494 /* accesses. */ 1495 static urb_priv_t *ohci_alloc_urb(struct usb_device *dev, unsigned long pipe, 1496 void *buffer, int transfer_len, int interval) 1497 { 1498 urb_priv_t *urb; 1499 1500 urb = calloc(1, sizeof(urb_priv_t)); 1501 if (!urb) { 1502 printf("ohci: Error out of memory allocating urb\n"); 1503 return NULL; 1504 } 1505 1506 urb->dev = dev; 1507 urb->pipe = pipe; 1508 urb->transfer_buffer = buffer; 1509 urb->transfer_buffer_length = transfer_len; 1510 urb->interval = interval; 1511 1512 return urb; 1513 } 1514 1515 static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, 1516 unsigned long pipe, void *buffer, int transfer_len, 1517 struct devrequest *setup, int interval) 1518 { 1519 int stat = 0; 1520 int maxsize = usb_maxpacket(dev, pipe); 1521 int timeout; 1522 urb_priv_t *urb; 1523 ohci_dev_t *ohci_dev; 1524 1525 urb = ohci_alloc_urb(dev, pipe, buffer, transfer_len, interval); 1526 if (!urb) 1527 return -ENOMEM; 1528 1529 #ifdef DEBUG 1530 urb->actual_length = 0; 1531 pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, 1532 setup, "SUB", usb_pipein(pipe)); 1533 #else 1534 ohci_mdelay(1); 1535 #endif 1536 if (!maxsize) { 1537 err("submit_common_message: pipesize for pipe %lx is zero", 1538 pipe); 1539 return -1; 1540 } 1541 1542 ohci_dev = ohci_get_ohci_dev(ohci, dev->devnum, usb_pipeint(pipe)); 1543 if (!ohci_dev) 1544 return -ENOMEM; 1545 1546 if (sohci_submit_job(ohci, ohci_dev, urb, setup) < 0) { 1547 err("sohci_submit_job failed"); 1548 return -1; 1549 } 1550 1551 mdelay(10); 1552 /* ohci_dump_status(ohci); */ 1553 1554 timeout = USB_TIMEOUT_MS(pipe); 1555 1556 /* wait for it to complete */ 1557 for (;;) { 1558 /* check whether the controller is done */ 1559 stat = hc_interrupt(ohci); 1560 if (stat < 0) { 1561 stat = USB_ST_CRC_ERR; 1562 break; 1563 } 1564 1565 /* NOTE: since we are not interrupt driven in U-Boot and always 1566 * handle only one URB at a time, we cannot assume the 1567 * transaction finished on the first successful return from 1568 * hc_interrupt().. unless the flag for current URB is set, 1569 * meaning that all TD's to/from device got actually 1570 * transferred and processed. If the current URB is not 1571 * finished we need to re-iterate this loop so as 1572 * hc_interrupt() gets called again as there needs to be some 1573 * more TD's to process still */ 1574 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { 1575 /* 0xff is returned for an SF-interrupt */ 1576 break; 1577 } 1578 1579 if (--timeout) { 1580 mdelay(1); 1581 if (!urb->finished) 1582 dbg("*"); 1583 1584 } else { 1585 if (!usb_pipeint(pipe)) 1586 err("CTL:TIMEOUT "); 1587 dbg("submit_common_msg: TO status %x\n", stat); 1588 urb->finished = 1; 1589 stat = USB_ST_CRC_ERR; 1590 break; 1591 } 1592 } 1593 1594 dev->status = stat; 1595 dev->act_len = urb->actual_length; 1596 1597 if (usb_pipein(pipe) && dev->status == 0 && dev->act_len) 1598 invalidate_dcache_buffer(buffer, dev->act_len); 1599 1600 #ifdef DEBUG 1601 pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, 1602 setup, "RET(ctlr)", usb_pipein(pipe)); 1603 #else 1604 ohci_mdelay(1); 1605 #endif 1606 urb_free_priv(urb); 1607 return 0; 1608 } 1609 1610 #define MAX_INT_QUEUESIZE 8 1611 1612 struct int_queue { 1613 int queuesize; 1614 int curr_urb; 1615 urb_priv_t *urb[MAX_INT_QUEUESIZE]; 1616 }; 1617 1618 static struct int_queue *_ohci_create_int_queue(ohci_t *ohci, 1619 struct usb_device *udev, unsigned long pipe, int queuesize, 1620 int elementsize, void *buffer, int interval) 1621 { 1622 struct int_queue *queue; 1623 ohci_dev_t *ohci_dev; 1624 int i; 1625 1626 if (queuesize > MAX_INT_QUEUESIZE) 1627 return NULL; 1628 1629 ohci_dev = ohci_get_ohci_dev(ohci, udev->devnum, 1); 1630 if (!ohci_dev) 1631 return NULL; 1632 1633 queue = malloc(sizeof(*queue)); 1634 if (!queue) { 1635 printf("ohci: Error out of memory allocating int queue\n"); 1636 return NULL; 1637 } 1638 1639 for (i = 0; i < queuesize; i++) { 1640 queue->urb[i] = ohci_alloc_urb(udev, pipe, 1641 buffer + i * elementsize, 1642 elementsize, interval); 1643 if (!queue->urb[i]) 1644 break; 1645 1646 if (sohci_submit_job(ohci, ohci_dev, queue->urb[i], NULL)) { 1647 printf("ohci: Error submitting int queue job\n"); 1648 urb_free_priv(queue->urb[i]); 1649 break; 1650 } 1651 } 1652 if (i == 0) { 1653 /* We did not succeed in submitting even 1 urb */ 1654 free(queue); 1655 return NULL; 1656 } 1657 1658 queue->queuesize = i; 1659 queue->curr_urb = 0; 1660 1661 return queue; 1662 } 1663 1664 static void *_ohci_poll_int_queue(ohci_t *ohci, struct usb_device *udev, 1665 struct int_queue *queue) 1666 { 1667 if (queue->curr_urb == queue->queuesize) 1668 return NULL; /* Queue depleted */ 1669 1670 if (hc_interrupt(ohci) < 0) 1671 return NULL; 1672 1673 if (queue->urb[queue->curr_urb]->finished) { 1674 void *ret = queue->urb[queue->curr_urb]->transfer_buffer; 1675 queue->curr_urb++; 1676 return ret; 1677 } 1678 1679 return NULL; 1680 } 1681 1682 static int _ohci_destroy_int_queue(ohci_t *ohci, struct usb_device *dev, 1683 struct int_queue *queue) 1684 { 1685 int i; 1686 1687 for (i = 0; i < queue->queuesize; i++) 1688 urb_free_priv(queue->urb[i]); 1689 1690 free(queue); 1691 1692 return 0; 1693 } 1694 1695 #if !CONFIG_IS_ENABLED(DM_USB) 1696 /* submit routines called from usb.c */ 1697 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1698 int transfer_len) 1699 { 1700 info("submit_bulk_msg"); 1701 return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, 1702 NULL, 0); 1703 } 1704 1705 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1706 int transfer_len, int interval) 1707 { 1708 info("submit_int_msg"); 1709 return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL, 1710 interval); 1711 } 1712 1713 struct int_queue *create_int_queue(struct usb_device *dev, 1714 unsigned long pipe, int queuesize, int elementsize, 1715 void *buffer, int interval) 1716 { 1717 return _ohci_create_int_queue(&gohci, dev, pipe, queuesize, 1718 elementsize, buffer, interval); 1719 } 1720 1721 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) 1722 { 1723 return _ohci_poll_int_queue(&gohci, dev, queue); 1724 } 1725 1726 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) 1727 { 1728 return _ohci_destroy_int_queue(&gohci, dev, queue); 1729 } 1730 #endif 1731 1732 static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev, 1733 unsigned long pipe, void *buffer, int transfer_len, 1734 struct devrequest *setup) 1735 { 1736 int maxsize = usb_maxpacket(dev, pipe); 1737 1738 info("submit_control_msg"); 1739 #ifdef DEBUG 1740 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, 1741 setup, "SUB", usb_pipein(pipe)); 1742 #else 1743 ohci_mdelay(1); 1744 #endif 1745 if (!maxsize) { 1746 err("submit_control_message: pipesize for pipe %lx is zero", 1747 pipe); 1748 return -1; 1749 } 1750 if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) { 1751 ohci->rh.dev = dev; 1752 /* root hub - redirect */ 1753 return ohci_submit_rh_msg(ohci, dev, pipe, buffer, 1754 transfer_len, setup); 1755 } 1756 1757 return submit_common_msg(ohci, dev, pipe, buffer, transfer_len, 1758 setup, 0); 1759 } 1760 1761 /*-------------------------------------------------------------------------* 1762 * HC functions 1763 *-------------------------------------------------------------------------*/ 1764 1765 /* reset the HC and BUS */ 1766 1767 static int hc_reset(ohci_t *ohci) 1768 { 1769 #ifdef CONFIG_PCI_EHCI_DEVNO 1770 pci_dev_t pdev; 1771 #endif 1772 int timeout = 30; 1773 int smm_timeout = 50; /* 0,5 sec */ 1774 1775 dbg("%s\n", __FUNCTION__); 1776 1777 #ifdef CONFIG_PCI_EHCI_DEVNO 1778 /* 1779 * Some multi-function controllers (e.g. ISP1562) allow root hub 1780 * resetting via EHCI registers only. 1781 */ 1782 pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO); 1783 if (pdev != -1) { 1784 u32 base; 1785 int timeout = 1000; 1786 1787 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); 1788 base += EHCI_USBCMD_OFF; 1789 ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base); 1790 1791 while (ohci_readl(base) & EHCI_USBCMD_HCRESET) { 1792 if (timeout-- <= 0) { 1793 printf("USB RootHub reset timed out!"); 1794 break; 1795 } 1796 udelay(1); 1797 } 1798 } else 1799 printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO); 1800 #endif 1801 if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { 1802 /* SMM owns the HC, request ownership */ 1803 ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus); 1804 info("USB HC TakeOver from SMM"); 1805 while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { 1806 mdelay(10); 1807 if (--smm_timeout == 0) { 1808 err("USB HC TakeOver failed!"); 1809 return -1; 1810 } 1811 } 1812 } 1813 1814 /* Disable HC interrupts */ 1815 ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); 1816 1817 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", 1818 ohci->slot_name, 1819 ohci_readl(&ohci->regs->control)); 1820 1821 /* Reset USB (needed by some controllers) */ 1822 ohci->hc_control = 0; 1823 ohci_writel(ohci->hc_control, &ohci->regs->control); 1824 1825 /* HC Reset requires max 10 us delay */ 1826 ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus); 1827 while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { 1828 if (--timeout == 0) { 1829 err("USB HC reset timed out!"); 1830 return -1; 1831 } 1832 udelay(1); 1833 } 1834 return 0; 1835 } 1836 1837 /*-------------------------------------------------------------------------*/ 1838 1839 /* Start an OHCI controller, set the BUS operational 1840 * enable interrupts 1841 * connect the virtual root hub */ 1842 1843 static int hc_start(ohci_t *ohci) 1844 { 1845 __u32 mask; 1846 unsigned int fminterval; 1847 int i; 1848 1849 ohci->disabled = 1; 1850 for (i = 0; i < NUM_INT_DEVS; i++) 1851 ohci->int_dev[i].devnum = -1; 1852 1853 /* Tell the controller where the control and bulk lists are 1854 * The lists are empty now. */ 1855 1856 ohci_writel(0, &ohci->regs->ed_controlhead); 1857 ohci_writel(0, &ohci->regs->ed_bulkhead); 1858 1859 ohci_writel((uintptr_t)ohci->hcca, 1860 &ohci->regs->hcca); /* reset clears this */ 1861 1862 fminterval = 0x2edf; 1863 ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart); 1864 fminterval |= ((((fminterval - 210) * 6) / 7) << 16); 1865 ohci_writel(fminterval, &ohci->regs->fminterval); 1866 ohci_writel(0x628, &ohci->regs->lsthresh); 1867 1868 /* start controller operations */ 1869 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; 1870 ohci->disabled = 0; 1871 ohci_writel(ohci->hc_control, &ohci->regs->control); 1872 1873 /* disable all interrupts */ 1874 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | 1875 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | 1876 OHCI_INTR_OC | OHCI_INTR_MIE); 1877 ohci_writel(mask, &ohci->regs->intrdisable); 1878 /* clear all interrupts */ 1879 mask &= ~OHCI_INTR_MIE; 1880 ohci_writel(mask, &ohci->regs->intrstatus); 1881 /* Choose the interrupts we care about now - but w/o MIE */ 1882 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; 1883 ohci_writel(mask, &ohci->regs->intrenable); 1884 1885 #ifdef OHCI_USE_NPS 1886 /* required for AMD-756 and some Mac platforms */ 1887 ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, 1888 &ohci->regs->roothub.a); 1889 ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status); 1890 #endif /* OHCI_USE_NPS */ 1891 1892 /* connect the virtual root hub */ 1893 ohci->rh.devnum = 0; 1894 1895 return 0; 1896 } 1897 1898 /*-------------------------------------------------------------------------*/ 1899 1900 /* an interrupt happens */ 1901 1902 static int hc_interrupt(ohci_t *ohci) 1903 { 1904 struct ohci_regs *regs = ohci->regs; 1905 int ints; 1906 int stat = -1; 1907 1908 invalidate_dcache_hcca(ohci->hcca); 1909 1910 if ((ohci->hcca->done_head != 0) && 1911 !(m32_swap(ohci->hcca->done_head) & 0x01)) { 1912 ints = OHCI_INTR_WDH; 1913 } else { 1914 ints = ohci_readl(®s->intrstatus); 1915 if (ints == ~(u32)0) { 1916 ohci->disabled++; 1917 err("%s device removed!", ohci->slot_name); 1918 return -1; 1919 } else { 1920 ints &= ohci_readl(®s->intrenable); 1921 if (ints == 0) { 1922 dbg("hc_interrupt: returning..\n"); 1923 return 0xff; 1924 } 1925 } 1926 } 1927 1928 /* dbg("Interrupt: %x frame: %x", ints, 1929 le16_to_cpu(ohci->hcca->frame_no)); */ 1930 1931 if (ints & OHCI_INTR_RHSC) 1932 stat = 0xff; 1933 1934 if (ints & OHCI_INTR_UE) { 1935 ohci->disabled++; 1936 err("OHCI Unrecoverable Error, controller usb-%s disabled", 1937 ohci->slot_name); 1938 /* e.g. due to PCI Master/Target Abort */ 1939 1940 #ifdef DEBUG 1941 ohci_dump(ohci, 1); 1942 #else 1943 ohci_mdelay(1); 1944 #endif 1945 /* FIXME: be optimistic, hope that bug won't repeat often. */ 1946 /* Make some non-interrupt context restart the controller. */ 1947 /* Count and limit the retries though; either hardware or */ 1948 /* software errors can go forever... */ 1949 hc_reset(ohci); 1950 return -1; 1951 } 1952 1953 if (ints & OHCI_INTR_WDH) { 1954 ohci_mdelay(1); 1955 ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); 1956 (void)ohci_readl(®s->intrdisable); /* flush */ 1957 stat = dl_done_list(ohci); 1958 ohci_writel(OHCI_INTR_WDH, ®s->intrenable); 1959 (void)ohci_readl(®s->intrdisable); /* flush */ 1960 } 1961 1962 if (ints & OHCI_INTR_SO) { 1963 dbg("USB Schedule overrun\n"); 1964 ohci_writel(OHCI_INTR_SO, ®s->intrenable); 1965 stat = -1; 1966 } 1967 1968 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ 1969 if (ints & OHCI_INTR_SF) { 1970 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; 1971 mdelay(1); 1972 ohci_writel(OHCI_INTR_SF, ®s->intrdisable); 1973 if (ohci->ed_rm_list[frame] != NULL) 1974 ohci_writel(OHCI_INTR_SF, ®s->intrenable); 1975 stat = 0xff; 1976 } 1977 1978 ohci_writel(ints, ®s->intrstatus); 1979 return stat; 1980 } 1981 1982 /*-------------------------------------------------------------------------*/ 1983 1984 #if !CONFIG_IS_ENABLED(DM_USB) 1985 1986 /*-------------------------------------------------------------------------*/ 1987 1988 /* De-allocate all resources.. */ 1989 1990 static void hc_release_ohci(ohci_t *ohci) 1991 { 1992 dbg("USB HC release ohci usb-%s", ohci->slot_name); 1993 1994 if (!ohci->disabled) 1995 hc_reset(ohci); 1996 } 1997 1998 /*-------------------------------------------------------------------------*/ 1999 2000 /* 2001 * low level initalisation routine, called from usb.c 2002 */ 2003 static char ohci_inited = 0; 2004 2005 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 2006 { 2007 #ifdef CONFIG_PCI_OHCI 2008 pci_dev_t pdev; 2009 #endif 2010 2011 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 2012 /* cpu dependant init */ 2013 if (usb_cpu_init()) 2014 return -1; 2015 #endif 2016 2017 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 2018 /* board dependant init */ 2019 if (board_usb_init(index, USB_INIT_HOST)) 2020 return -1; 2021 #endif 2022 memset(&gohci, 0, sizeof(ohci_t)); 2023 2024 /* align the storage */ 2025 if ((__u32)&ghcca[0] & 0xff) { 2026 err("HCCA not aligned!!"); 2027 return -1; 2028 } 2029 gohci.hcca = &ghcca[0]; 2030 info("aligned ghcca %p", gohci.hcca); 2031 memset(gohci.hcca, 0, sizeof(struct ohci_hcca)); 2032 2033 gohci.disabled = 1; 2034 gohci.sleeping = 0; 2035 gohci.irq = -1; 2036 #ifdef CONFIG_PCI_OHCI 2037 pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); 2038 2039 if (pdev != -1) { 2040 u16 vid, did; 2041 u32 base; 2042 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); 2043 pci_read_config_word(pdev, PCI_DEVICE_ID, &did); 2044 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", 2045 vid, did, (pdev >> 16) & 0xff, 2046 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); 2047 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); 2048 printf("OHCI regs address 0x%08x\n", base); 2049 gohci.regs = (struct ohci_regs *)base; 2050 } else 2051 return -1; 2052 #else 2053 gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; 2054 #endif 2055 2056 gohci.flags = 0; 2057 gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; 2058 2059 if (hc_reset (&gohci) < 0) { 2060 hc_release_ohci (&gohci); 2061 err ("can't reset usb-%s", gohci.slot_name); 2062 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 2063 /* board dependant cleanup */ 2064 board_usb_cleanup(index, USB_INIT_HOST); 2065 #endif 2066 2067 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 2068 /* cpu dependant cleanup */ 2069 usb_cpu_init_fail(); 2070 #endif 2071 return -1; 2072 } 2073 2074 if (hc_start(&gohci) < 0) { 2075 err("can't start usb-%s", gohci.slot_name); 2076 hc_release_ohci(&gohci); 2077 /* Initialization failed */ 2078 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 2079 /* board dependant cleanup */ 2080 usb_board_stop(); 2081 #endif 2082 2083 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 2084 /* cpu dependant cleanup */ 2085 usb_cpu_stop(); 2086 #endif 2087 return -1; 2088 } 2089 2090 #ifdef DEBUG 2091 ohci_dump(&gohci, 1); 2092 #else 2093 ohci_mdelay(1); 2094 #endif 2095 ohci_inited = 1; 2096 return 0; 2097 } 2098 2099 int usb_lowlevel_stop(int index) 2100 { 2101 /* this gets called really early - before the controller has */ 2102 /* even been initialized! */ 2103 if (!ohci_inited) 2104 return 0; 2105 /* TODO release any interrupts, etc. */ 2106 /* call hc_release_ohci() here ? */ 2107 hc_reset(&gohci); 2108 2109 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 2110 /* board dependant cleanup */ 2111 if (usb_board_stop()) 2112 return -1; 2113 #endif 2114 2115 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 2116 /* cpu dependant cleanup */ 2117 if (usb_cpu_stop()) 2118 return -1; 2119 #endif 2120 /* This driver is no longer initialised. It needs a new low-level 2121 * init (board/cpu) before it can be used again. */ 2122 ohci_inited = 0; 2123 return 0; 2124 } 2125 2126 int submit_control_msg(struct usb_device *dev, unsigned long pipe, 2127 void *buffer, int transfer_len, struct devrequest *setup) 2128 { 2129 return _ohci_submit_control_msg(&gohci, dev, pipe, buffer, 2130 transfer_len, setup); 2131 } 2132 #endif 2133 2134 #if CONFIG_IS_ENABLED(DM_USB) 2135 static int ohci_submit_control_msg(struct udevice *dev, struct usb_device *udev, 2136 unsigned long pipe, void *buffer, int length, 2137 struct devrequest *setup) 2138 { 2139 ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); 2140 2141 return _ohci_submit_control_msg(ohci, udev, pipe, buffer, 2142 length, setup); 2143 } 2144 2145 static int ohci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 2146 unsigned long pipe, void *buffer, int length) 2147 { 2148 ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); 2149 2150 return submit_common_msg(ohci, udev, pipe, buffer, length, NULL, 0); 2151 } 2152 2153 static int ohci_submit_int_msg(struct udevice *dev, struct usb_device *udev, 2154 unsigned long pipe, void *buffer, int length, 2155 int interval) 2156 { 2157 ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); 2158 2159 return submit_common_msg(ohci, udev, pipe, buffer, length, 2160 NULL, interval); 2161 } 2162 2163 static struct int_queue *ohci_create_int_queue(struct udevice *dev, 2164 struct usb_device *udev, unsigned long pipe, int queuesize, 2165 int elementsize, void *buffer, int interval) 2166 { 2167 ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); 2168 2169 return _ohci_create_int_queue(ohci, udev, pipe, queuesize, elementsize, 2170 buffer, interval); 2171 } 2172 2173 static void *ohci_poll_int_queue(struct udevice *dev, struct usb_device *udev, 2174 struct int_queue *queue) 2175 { 2176 ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); 2177 2178 return _ohci_poll_int_queue(ohci, udev, queue); 2179 } 2180 2181 static int ohci_destroy_int_queue(struct udevice *dev, struct usb_device *udev, 2182 struct int_queue *queue) 2183 { 2184 ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); 2185 2186 return _ohci_destroy_int_queue(ohci, udev, queue); 2187 } 2188 2189 int ohci_register(struct udevice *dev, struct ohci_regs *regs) 2190 { 2191 struct usb_bus_priv *priv = dev_get_uclass_priv(dev); 2192 ohci_t *ohci = dev_get_priv(dev); 2193 u32 reg; 2194 2195 priv->desc_before_addr = true; 2196 2197 ohci->regs = regs; 2198 ohci->hcca = memalign(256, sizeof(struct ohci_hcca)); 2199 if (!ohci->hcca) 2200 return -ENOMEM; 2201 memset(ohci->hcca, 0, sizeof(struct ohci_hcca)); 2202 flush_dcache_hcca(ohci->hcca); 2203 2204 if (hc_reset(ohci) < 0) 2205 return -EIO; 2206 2207 if (hc_start(ohci) < 0) 2208 return -EIO; 2209 2210 reg = ohci_readl(®s->revision); 2211 printf("USB OHCI %x.%x\n", (reg >> 4) & 0xf, reg & 0xf); 2212 2213 return 0; 2214 } 2215 2216 int ohci_deregister(struct udevice *dev) 2217 { 2218 ohci_t *ohci = dev_get_priv(dev); 2219 2220 if (hc_reset(ohci) < 0) 2221 return -EIO; 2222 2223 free(ohci->hcca); 2224 2225 return 0; 2226 } 2227 2228 struct dm_usb_ops ohci_usb_ops = { 2229 .control = ohci_submit_control_msg, 2230 .bulk = ohci_submit_bulk_msg, 2231 .interrupt = ohci_submit_int_msg, 2232 .create_int_queue = ohci_create_int_queue, 2233 .poll_int_queue = ohci_poll_int_queue, 2234 .destroy_int_queue = ohci_destroy_int_queue, 2235 }; 2236 2237 #endif 2238