1 /* 2 * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c 3 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers 4 * 5 * Copyright (C) 2009 for Samsung Electronics 6 * 7 * BSP Support for Samsung's UDC driver 8 * available at: 9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git 10 * 11 * State machine bugfixes: 12 * Marek Szyprowski <m.szyprowski@samsung.com> 13 * 14 * Ported to u-boot: 15 * Marek Szyprowski <m.szyprowski@samsung.com> 16 * Lukasz Majewski <l.majewski@samsumg.com> 17 * 18 * SPDX-License-Identifier: GPL-2.0+ 19 */ 20 21 static u8 clear_feature_num; 22 int clear_feature_flag; 23 24 /* Bulk-Only Mass Storage Reset (class-specific request) */ 25 #define GET_MAX_LUN_REQUEST 0xFE 26 #define BOT_RESET_REQUEST 0xFF 27 28 static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev) 29 { 30 u32 ep_ctrl; 31 32 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); 33 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz); 34 35 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl); 36 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, 37 ®->in_endp[EP0_CON].diepctl); 38 39 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n", 40 __func__, readl(®->in_endp[EP0_CON].diepctl)); 41 dev->ep0state = WAIT_FOR_IN_COMPLETE; 42 } 43 44 static void dwc2_udc_pre_setup(void) 45 { 46 u32 ep_ctrl; 47 48 debug_cond(DEBUG_IN_EP, 49 "%s : Prepare Setup packets.\n", __func__); 50 51 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), 52 ®->out_endp[EP0_CON].doeptsiz); 53 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); 54 55 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl); 56 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl); 57 58 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n", 59 __func__, readl(®->in_endp[EP0_CON].diepctl)); 60 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n", 61 __func__, readl(®->out_endp[EP0_CON].doepctl)); 62 63 } 64 65 static inline void dwc2_ep0_complete_out(void) 66 { 67 u32 ep_ctrl; 68 69 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n", 70 __func__, readl(®->in_endp[EP0_CON].diepctl)); 71 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n", 72 __func__, readl(®->out_endp[EP0_CON].doepctl)); 73 74 debug_cond(DEBUG_IN_EP, 75 "%s : Prepare Complete Out packet.\n", __func__); 76 77 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), 78 ®->out_endp[EP0_CON].doeptsiz); 79 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); 80 81 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl); 82 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, 83 ®->out_endp[EP0_CON].doepctl); 84 85 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n", 86 __func__, readl(®->in_endp[EP0_CON].diepctl)); 87 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n", 88 __func__, readl(®->out_endp[EP0_CON].doepctl)); 89 90 } 91 92 93 static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req) 94 { 95 u32 *buf, ctrl; 96 u32 length, pktcnt; 97 u32 ep_num = ep_index(ep); 98 99 buf = req->req.buf + req->req.actual; 100 length = min_t(u32, req->req.length - req->req.actual, 101 ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket); 102 103 ep->len = length; 104 ep->dma_buf = buf; 105 106 if (ep_num == EP0_CON || length == 0) 107 pktcnt = 1; 108 else 109 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1; 110 111 ctrl = readl(®->out_endp[ep_num].doepctl); 112 113 invalidate_dcache_range((unsigned long) ep->dma_buf, 114 (unsigned long) ep->dma_buf + 115 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE)); 116 117 writel((unsigned int)(unsigned long)ep->dma_buf, 118 ®->out_endp[ep_num].doepdma); 119 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), 120 ®->out_endp[ep_num].doeptsiz); 121 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl); 122 123 debug_cond(DEBUG_OUT_EP != 0, 124 "%s: EP%d RX DMA start : DOEPDMA = 0x%x," 125 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n" 126 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n", 127 __func__, ep_num, 128 readl(®->out_endp[ep_num].doepdma), 129 readl(®->out_endp[ep_num].doeptsiz), 130 readl(®->out_endp[ep_num].doepctl), 131 buf, pktcnt, length); 132 return 0; 133 134 } 135 136 static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req) 137 { 138 u32 *buf, ctrl = 0; 139 u32 length, pktcnt; 140 u32 ep_num = ep_index(ep); 141 142 buf = req->req.buf + req->req.actual; 143 length = req->req.length - req->req.actual; 144 145 if (ep_num == EP0_CON) 146 length = min(length, (u32)ep_maxpacket(ep)); 147 148 ep->len = length; 149 ep->dma_buf = buf; 150 151 flush_dcache_range((unsigned long) ep->dma_buf, 152 (unsigned long) ep->dma_buf + 153 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE)); 154 155 if (length == 0) 156 pktcnt = 1; 157 else 158 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1; 159 160 /* Flush the endpoint's Tx FIFO */ 161 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl); 162 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl); 163 while (readl(®->grstctl) & TX_FIFO_FLUSH) 164 ; 165 166 writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma); 167 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length), 168 ®->in_endp[ep_num].dieptsiz); 169 170 ctrl = readl(®->in_endp[ep_num].diepctl); 171 172 /* Write the FIFO number to be used for this endpoint */ 173 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK; 174 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num); 175 176 /* Clear reserved (Next EP) bits */ 177 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT)); 178 179 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl); 180 181 debug_cond(DEBUG_IN_EP, 182 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x," 183 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n" 184 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n", 185 __func__, ep_num, 186 readl(®->in_endp[ep_num].diepdma), 187 readl(®->in_endp[ep_num].dieptsiz), 188 readl(®->in_endp[ep_num].diepctl), 189 buf, pktcnt, length); 190 191 return length; 192 } 193 194 static void complete_rx(struct dwc2_udc *dev, u8 ep_num) 195 { 196 struct dwc2_ep *ep = &dev->ep[ep_num]; 197 struct dwc2_request *req = NULL; 198 u32 ep_tsr = 0, xfer_size = 0, is_short = 0; 199 200 if (list_empty(&ep->queue)) { 201 debug_cond(DEBUG_OUT_EP != 0, 202 "%s: RX DMA done : NULL REQ on OUT EP-%d\n", 203 __func__, ep_num); 204 return; 205 206 } 207 208 req = list_entry(ep->queue.next, struct dwc2_request, queue); 209 ep_tsr = readl(®->out_endp[ep_num].doeptsiz); 210 211 if (ep_num == EP0_CON) 212 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0); 213 else 214 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP); 215 216 xfer_size = ep->len - xfer_size; 217 218 /* 219 * NOTE: 220 * 221 * Please be careful with proper buffer allocation for USB request, 222 * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only 223 * with starting address, but also its size shall be a cache line 224 * multiplication. 225 * 226 * This will prevent from corruption of data allocated immediatelly 227 * before or after the buffer. 228 * 229 * For armv7, the cache_v7.c provides proper code to emit "ERROR" 230 * message to warn users. 231 */ 232 invalidate_dcache_range((unsigned long) ep->dma_buf, 233 (unsigned long) ep->dma_buf + 234 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE)); 235 236 req->req.actual += min(xfer_size, req->req.length - req->req.actual); 237 is_short = !!(xfer_size % ep->ep.maxpacket); 238 239 debug_cond(DEBUG_OUT_EP != 0, 240 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, " 241 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n", 242 __func__, ep_num, req->req.actual, req->req.length, 243 is_short, ep_tsr, req->req.length - req->req.actual); 244 245 if (is_short || req->req.actual == req->req.length) { 246 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) { 247 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n"); 248 dwc2_udc_ep0_zlp(dev); 249 /* packet will be completed in complete_tx() */ 250 dev->ep0state = WAIT_FOR_IN_COMPLETE; 251 } else { 252 done(ep, req, 0); 253 254 if (!list_empty(&ep->queue)) { 255 req = list_entry(ep->queue.next, 256 struct dwc2_request, queue); 257 debug_cond(DEBUG_OUT_EP != 0, 258 "%s: Next Rx request start...\n", 259 __func__); 260 setdma_rx(ep, req); 261 } 262 } 263 } else 264 setdma_rx(ep, req); 265 } 266 267 static void complete_tx(struct dwc2_udc *dev, u8 ep_num) 268 { 269 struct dwc2_ep *ep = &dev->ep[ep_num]; 270 struct dwc2_request *req; 271 u32 ep_tsr = 0, xfer_size = 0, is_short = 0; 272 u32 last; 273 274 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) { 275 dev->ep0state = WAIT_FOR_OUT_COMPLETE; 276 dwc2_ep0_complete_out(); 277 return; 278 } 279 280 if (list_empty(&ep->queue)) { 281 debug_cond(DEBUG_IN_EP, 282 "%s: TX DMA done : NULL REQ on IN EP-%d\n", 283 __func__, ep_num); 284 return; 285 286 } 287 288 req = list_entry(ep->queue.next, struct dwc2_request, queue); 289 290 ep_tsr = readl(®->in_endp[ep_num].dieptsiz); 291 292 xfer_size = ep->len; 293 is_short = (xfer_size < ep->ep.maxpacket); 294 req->req.actual += min(xfer_size, req->req.length - req->req.actual); 295 296 debug_cond(DEBUG_IN_EP, 297 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, " 298 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n", 299 __func__, ep_num, req->req.actual, req->req.length, 300 is_short, ep_tsr, req->req.length - req->req.actual); 301 302 if (ep_num == 0) { 303 if (dev->ep0state == DATA_STATE_XMIT) { 304 debug_cond(DEBUG_IN_EP, 305 "%s: ep_num = %d, ep0stat ==" 306 "DATA_STATE_XMIT\n", 307 __func__, ep_num); 308 last = write_fifo_ep0(ep, req); 309 if (last) 310 dev->ep0state = WAIT_FOR_COMPLETE; 311 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) { 312 debug_cond(DEBUG_IN_EP, 313 "%s: ep_num = %d, completing request\n", 314 __func__, ep_num); 315 done(ep, req, 0); 316 dev->ep0state = WAIT_FOR_SETUP; 317 } else if (dev->ep0state == WAIT_FOR_COMPLETE) { 318 debug_cond(DEBUG_IN_EP, 319 "%s: ep_num = %d, completing request\n", 320 __func__, ep_num); 321 done(ep, req, 0); 322 dev->ep0state = WAIT_FOR_OUT_COMPLETE; 323 dwc2_ep0_complete_out(); 324 } else { 325 debug_cond(DEBUG_IN_EP, 326 "%s: ep_num = %d, invalid ep state\n", 327 __func__, ep_num); 328 } 329 return; 330 } 331 332 if (req->req.actual == req->req.length) 333 done(ep, req, 0); 334 335 if (!list_empty(&ep->queue)) { 336 req = list_entry(ep->queue.next, struct dwc2_request, queue); 337 debug_cond(DEBUG_IN_EP, 338 "%s: Next Tx request start...\n", __func__); 339 setdma_tx(ep, req); 340 } 341 } 342 343 static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num) 344 { 345 struct dwc2_ep *ep = &dev->ep[ep_num]; 346 struct dwc2_request *req; 347 348 debug_cond(DEBUG_IN_EP, 349 "%s: Check queue, ep_num = %d\n", __func__, ep_num); 350 351 if (!list_empty(&ep->queue)) { 352 req = list_entry(ep->queue.next, struct dwc2_request, queue); 353 debug_cond(DEBUG_IN_EP, 354 "%s: Next Tx request(0x%p) start...\n", 355 __func__, req); 356 357 if (ep_is_in(ep)) 358 setdma_tx(ep, req); 359 else 360 setdma_rx(ep, req); 361 } else { 362 debug_cond(DEBUG_IN_EP, 363 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num); 364 365 return; 366 } 367 368 } 369 370 static void process_ep_in_intr(struct dwc2_udc *dev) 371 { 372 u32 ep_intr, ep_intr_status; 373 u8 ep_num = 0; 374 375 ep_intr = readl(®->daint); 376 debug_cond(DEBUG_IN_EP, 377 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr); 378 379 ep_intr &= DAINT_MASK; 380 381 while (ep_intr) { 382 if (ep_intr & DAINT_IN_EP_INT(1)) { 383 ep_intr_status = readl(®->in_endp[ep_num].diepint); 384 debug_cond(DEBUG_IN_EP, 385 "\tEP%d-IN : DIEPINT = 0x%x\n", 386 ep_num, ep_intr_status); 387 388 /* Interrupt Clear */ 389 writel(ep_intr_status, ®->in_endp[ep_num].diepint); 390 391 if (ep_intr_status & TRANSFER_DONE) { 392 complete_tx(dev, ep_num); 393 394 if (ep_num == 0) { 395 if (dev->ep0state == 396 WAIT_FOR_IN_COMPLETE) 397 dev->ep0state = WAIT_FOR_SETUP; 398 399 if (dev->ep0state == WAIT_FOR_SETUP) 400 dwc2_udc_pre_setup(); 401 402 /* continue transfer after 403 set_clear_halt for DMA mode */ 404 if (clear_feature_flag == 1) { 405 dwc2_udc_check_tx_queue(dev, 406 clear_feature_num); 407 clear_feature_flag = 0; 408 } 409 } 410 } 411 } 412 ep_num++; 413 ep_intr >>= 1; 414 } 415 } 416 417 static void process_ep_out_intr(struct dwc2_udc *dev) 418 { 419 u32 ep_intr, ep_intr_status; 420 u8 ep_num = 0; 421 422 ep_intr = readl(®->daint); 423 debug_cond(DEBUG_OUT_EP != 0, 424 "*** %s: EP OUT interrupt : DAINT = 0x%x\n", 425 __func__, ep_intr); 426 427 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK; 428 429 while (ep_intr) { 430 if (ep_intr & 0x1) { 431 ep_intr_status = readl(®->out_endp[ep_num].doepint); 432 debug_cond(DEBUG_OUT_EP != 0, 433 "\tEP%d-OUT : DOEPINT = 0x%x\n", 434 ep_num, ep_intr_status); 435 436 /* Interrupt Clear */ 437 writel(ep_intr_status, ®->out_endp[ep_num].doepint); 438 439 if (ep_num == 0) { 440 if (ep_intr_status & TRANSFER_DONE) { 441 if (dev->ep0state != 442 WAIT_FOR_OUT_COMPLETE) 443 complete_rx(dev, ep_num); 444 else { 445 dev->ep0state = WAIT_FOR_SETUP; 446 dwc2_udc_pre_setup(); 447 } 448 } 449 450 if (ep_intr_status & 451 CTRL_OUT_EP_SETUP_PHASE_DONE) { 452 debug_cond(DEBUG_OUT_EP != 0, 453 "SETUP packet arrived\n"); 454 dwc2_handle_ep0(dev); 455 } 456 } else { 457 if (ep_intr_status & TRANSFER_DONE) 458 complete_rx(dev, ep_num); 459 } 460 } 461 ep_num++; 462 ep_intr >>= 1; 463 } 464 } 465 466 /* 467 * usb client interrupt handler. 468 */ 469 static int dwc2_udc_irq(int irq, void *_dev) 470 { 471 struct dwc2_udc *dev = _dev; 472 u32 intr_status; 473 u32 usb_status, gintmsk; 474 unsigned long flags = 0; 475 476 spin_lock_irqsave(&dev->lock, flags); 477 478 intr_status = readl(®->gintsts); 479 gintmsk = readl(®->gintmsk); 480 481 debug_cond(DEBUG_ISR, 482 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x," 483 "DAINT : 0x%x, DAINTMSK : 0x%x\n", 484 __func__, intr_status, state_names[dev->ep0state], gintmsk, 485 readl(®->daint), readl(®->daintmsk)); 486 487 if (!intr_status) { 488 spin_unlock_irqrestore(&dev->lock, flags); 489 return IRQ_HANDLED; 490 } 491 492 if (intr_status & INT_ENUMDONE) { 493 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n"); 494 495 writel(INT_ENUMDONE, ®->gintsts); 496 usb_status = (readl(®->dsts) & 0x6); 497 498 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) { 499 debug_cond(DEBUG_ISR, 500 "\t\tFull Speed Detection\n"); 501 set_max_pktsize(dev, USB_SPEED_FULL); 502 503 } else { 504 debug_cond(DEBUG_ISR, 505 "\t\tHigh Speed Detection : 0x%x\n", 506 usb_status); 507 set_max_pktsize(dev, USB_SPEED_HIGH); 508 } 509 } 510 511 if (intr_status & INT_EARLY_SUSPEND) { 512 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n"); 513 writel(INT_EARLY_SUSPEND, ®->gintsts); 514 } 515 516 if (intr_status & INT_SUSPEND) { 517 usb_status = readl(®->dsts); 518 debug_cond(DEBUG_ISR, 519 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status); 520 writel(INT_SUSPEND, ®->gintsts); 521 522 if (dev->gadget.speed != USB_SPEED_UNKNOWN 523 && dev->driver) { 524 if (dev->driver->suspend) 525 dev->driver->suspend(&dev->gadget); 526 527 /* HACK to let gadget detect disconnected state */ 528 if (dev->driver->disconnect) { 529 spin_unlock_irqrestore(&dev->lock, flags); 530 dev->driver->disconnect(&dev->gadget); 531 spin_lock_irqsave(&dev->lock, flags); 532 } 533 } 534 } 535 536 if (intr_status & INT_RESUME) { 537 debug_cond(DEBUG_ISR, "\tResume interrupt\n"); 538 writel(INT_RESUME, ®->gintsts); 539 540 if (dev->gadget.speed != USB_SPEED_UNKNOWN 541 && dev->driver 542 && dev->driver->resume) { 543 544 dev->driver->resume(&dev->gadget); 545 } 546 } 547 548 if (intr_status & INT_RESET) { 549 u32 temp; 550 u32 connected = dev->connected; 551 552 usb_status = readl(®->gotgctl); 553 debug_cond(DEBUG_ISR, 554 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status); 555 writel(INT_RESET, ®->gintsts); 556 557 if ((usb_status & 0xc0000) == (0x3 << 18)) { 558 if (reset_available) { 559 debug_cond(DEBUG_ISR, 560 "\t\tOTG core got reset (%d)!!\n", 561 reset_available); 562 /* Reset device address to zero */ 563 temp = readl(®->dcfg); 564 temp &= ~DCFG_DEVADDR_MASK; 565 writel(temp, ®->dcfg); 566 567 /* Soft reset the core if connected */ 568 if (connected) 569 reconfig_usbd(dev); 570 571 dev->ep0state = WAIT_FOR_SETUP; 572 reset_available = 0; 573 dwc2_udc_pre_setup(); 574 } else 575 reset_available = 1; 576 577 } else { 578 reset_available = 1; 579 debug_cond(DEBUG_ISR, 580 "\t\tRESET handling skipped\n"); 581 } 582 } 583 584 if (intr_status & INT_IN_EP) 585 process_ep_in_intr(dev); 586 587 if (intr_status & INT_OUT_EP) 588 process_ep_out_intr(dev); 589 590 spin_unlock_irqrestore(&dev->lock, flags); 591 592 return IRQ_HANDLED; 593 } 594 595 /** Queue one request 596 * Kickstart transfer if needed 597 */ 598 static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req, 599 gfp_t gfp_flags) 600 { 601 struct dwc2_request *req; 602 struct dwc2_ep *ep; 603 struct dwc2_udc *dev; 604 unsigned long flags = 0; 605 u32 ep_num, gintsts; 606 607 req = container_of(_req, struct dwc2_request, req); 608 if (unlikely(!_req || !_req->complete || !_req->buf 609 || !list_empty(&req->queue))) { 610 611 debug("%s: bad params\n", __func__); 612 return -EINVAL; 613 } 614 615 ep = container_of(_ep, struct dwc2_ep, ep); 616 617 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { 618 619 debug("%s: bad ep: %s, %d, %p\n", __func__, 620 ep->ep.name, !ep->desc, _ep); 621 return -EINVAL; 622 } 623 624 ep_num = ep_index(ep); 625 dev = ep->dev; 626 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { 627 628 debug("%s: bogus device state %p\n", __func__, dev->driver); 629 return -ESHUTDOWN; 630 } 631 632 spin_lock_irqsave(&dev->lock, flags); 633 634 _req->status = -EINPROGRESS; 635 _req->actual = 0; 636 637 /* kickstart this i/o queue? */ 638 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p" 639 "Q empty = %d, stopped = %d\n", 640 __func__, _ep->name, ep_is_in(ep) ? "in" : "out", 641 _req, _req->length, _req->buf, 642 list_empty(&ep->queue), ep->stopped); 643 644 #ifdef DEBUG 645 { 646 int i, len = _req->length; 647 648 printf("pkt = "); 649 if (len > 64) 650 len = 64; 651 for (i = 0; i < len; i++) { 652 printf("%02x", ((u8 *)_req->buf)[i]); 653 if ((i & 7) == 7) 654 printf(" "); 655 } 656 printf("\n"); 657 } 658 #endif 659 660 if (list_empty(&ep->queue) && !ep->stopped) { 661 662 if (ep_num == 0) { 663 /* EP0 */ 664 list_add_tail(&req->queue, &ep->queue); 665 dwc2_ep0_kick(dev, ep); 666 req = 0; 667 668 } else if (ep_is_in(ep)) { 669 gintsts = readl(®->gintsts); 670 debug_cond(DEBUG_IN_EP, 671 "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n", 672 __func__, gintsts); 673 674 setdma_tx(ep, req); 675 } else { 676 gintsts = readl(®->gintsts); 677 debug_cond(DEBUG_OUT_EP != 0, 678 "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n", 679 __func__, gintsts); 680 681 setdma_rx(ep, req); 682 } 683 } 684 685 /* pio or dma irq handler advances the queue. */ 686 if (likely(req != 0)) 687 list_add_tail(&req->queue, &ep->queue); 688 689 spin_unlock_irqrestore(&dev->lock, flags); 690 691 return 0; 692 } 693 694 /****************************************************************/ 695 /* End Point 0 related functions */ 696 /****************************************************************/ 697 698 /* return: 0 = still running, 1 = completed, negative = errno */ 699 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req) 700 { 701 u32 max; 702 unsigned count; 703 int is_last; 704 705 max = ep_maxpacket(ep); 706 707 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max); 708 709 count = setdma_tx(ep, req); 710 711 /* last packet is usually short (or a zlp) */ 712 if (likely(count != max)) 713 is_last = 1; 714 else { 715 if (likely(req->req.length != req->req.actual + count) 716 || req->req.zero) 717 is_last = 0; 718 else 719 is_last = 1; 720 } 721 722 debug_cond(DEBUG_EP0 != 0, 723 "%s: wrote %s %d bytes%s %d left %p\n", __func__, 724 ep->ep.name, count, 725 is_last ? "/L" : "", 726 req->req.length - req->req.actual - count, req); 727 728 /* requests complete when all IN data is in the FIFO */ 729 if (is_last) { 730 ep->dev->ep0state = WAIT_FOR_SETUP; 731 return 1; 732 } 733 734 return 0; 735 } 736 737 static int dwc2_fifo_read(struct dwc2_ep *ep, u32 *cp, int max) 738 { 739 invalidate_dcache_range((unsigned long)cp, (unsigned long)cp + 740 ROUND(max, CONFIG_SYS_CACHELINE_SIZE)); 741 742 debug_cond(DEBUG_EP0 != 0, 743 "%s: bytes=%d, ep_index=%d 0x%p\n", __func__, 744 max, ep_index(ep), cp); 745 746 return max; 747 } 748 749 /** 750 * udc_set_address - set the USB address for this device 751 * @address: 752 * 753 * Called from control endpoint function 754 * after it decodes a set address setup packet. 755 */ 756 static void udc_set_address(struct dwc2_udc *dev, unsigned char address) 757 { 758 u32 ctrl = readl(®->dcfg); 759 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg); 760 761 dwc2_udc_ep0_zlp(dev); 762 763 debug_cond(DEBUG_EP0 != 0, 764 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n", 765 __func__, address, readl(®->dcfg)); 766 767 dev->usb_address = address; 768 } 769 770 static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep) 771 { 772 struct dwc2_udc *dev; 773 u32 ep_ctrl = 0; 774 775 dev = ep->dev; 776 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl); 777 778 /* set the disable and stall bits */ 779 if (ep_ctrl & DEPCTL_EPENA) 780 ep_ctrl |= DEPCTL_EPDIS; 781 782 ep_ctrl |= DEPCTL_STALL; 783 784 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl); 785 786 debug_cond(DEBUG_EP0 != 0, 787 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n", 788 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl); 789 /* 790 * The application can only set this bit, and the core clears it, 791 * when a SETUP token is received for this endpoint 792 */ 793 dev->ep0state = WAIT_FOR_SETUP; 794 795 dwc2_udc_pre_setup(); 796 } 797 798 static void dwc2_ep0_read(struct dwc2_udc *dev) 799 { 800 struct dwc2_request *req; 801 struct dwc2_ep *ep = &dev->ep[0]; 802 803 if (!list_empty(&ep->queue)) { 804 req = list_entry(ep->queue.next, struct dwc2_request, queue); 805 806 } else { 807 debug("%s: ---> BUG\n", __func__); 808 BUG(); 809 return; 810 } 811 812 debug_cond(DEBUG_EP0 != 0, 813 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n", 814 __func__, req, req->req.length, req->req.actual); 815 816 if (req->req.length == 0) { 817 /* zlp for Set_configuration, Set_interface, 818 * or Bulk-Only mass storge reset */ 819 820 ep->len = 0; 821 dwc2_udc_ep0_zlp(dev); 822 823 debug_cond(DEBUG_EP0 != 0, 824 "%s: req.length = 0, bRequest = %d\n", 825 __func__, usb_ctrl->bRequest); 826 return; 827 } 828 829 setdma_rx(ep, req); 830 } 831 832 /* 833 * DATA_STATE_XMIT 834 */ 835 static int dwc2_ep0_write(struct dwc2_udc *dev) 836 { 837 struct dwc2_request *req; 838 struct dwc2_ep *ep = &dev->ep[0]; 839 int ret, need_zlp = 0; 840 841 if (list_empty(&ep->queue)) 842 req = 0; 843 else 844 req = list_entry(ep->queue.next, struct dwc2_request, queue); 845 846 if (!req) { 847 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__); 848 return 0; 849 } 850 851 debug_cond(DEBUG_EP0 != 0, 852 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n", 853 __func__, req, req->req.length, req->req.actual); 854 855 if (req->req.length - req->req.actual == ep0_fifo_size) { 856 /* Next write will end with the packet size, */ 857 /* so we need Zero-length-packet */ 858 need_zlp = 1; 859 } 860 861 ret = write_fifo_ep0(ep, req); 862 863 if ((ret == 1) && !need_zlp) { 864 /* Last packet */ 865 dev->ep0state = WAIT_FOR_COMPLETE; 866 debug_cond(DEBUG_EP0 != 0, 867 "%s: finished, waiting for status\n", __func__); 868 869 } else { 870 dev->ep0state = DATA_STATE_XMIT; 871 debug_cond(DEBUG_EP0 != 0, 872 "%s: not finished\n", __func__); 873 } 874 875 return 1; 876 } 877 878 static int dwc2_udc_get_status(struct dwc2_udc *dev, 879 struct usb_ctrlrequest *crq) 880 { 881 u8 ep_num = crq->wIndex & 0x7F; 882 u16 g_status = 0; 883 u32 ep_ctrl; 884 885 debug_cond(DEBUG_SETUP != 0, 886 "%s: *** USB_REQ_GET_STATUS\n", __func__); 887 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK); 888 switch (crq->bRequestType & USB_RECIP_MASK) { 889 case USB_RECIP_INTERFACE: 890 g_status = 0; 891 debug_cond(DEBUG_SETUP != 0, 892 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n", 893 g_status); 894 break; 895 896 case USB_RECIP_DEVICE: 897 g_status = 0x1; /* Self powered */ 898 debug_cond(DEBUG_SETUP != 0, 899 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n", 900 g_status); 901 break; 902 903 case USB_RECIP_ENDPOINT: 904 if (crq->wLength > 2) { 905 debug_cond(DEBUG_SETUP != 0, 906 "\tGET_STATUS:Not support EP or wLength\n"); 907 return 1; 908 } 909 910 g_status = dev->ep[ep_num].stopped; 911 debug_cond(DEBUG_SETUP != 0, 912 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n", 913 g_status); 914 915 break; 916 917 default: 918 return 1; 919 } 920 921 memcpy(usb_ctrl, &g_status, sizeof(g_status)); 922 923 flush_dcache_range((unsigned long) usb_ctrl, 924 (unsigned long) usb_ctrl + 925 ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE)); 926 927 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); 928 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2), 929 ®->in_endp[EP0_CON].dieptsiz); 930 931 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl); 932 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, 933 ®->in_endp[EP0_CON].diepctl); 934 dev->ep0state = WAIT_FOR_NULL_COMPLETE; 935 936 return 0; 937 } 938 939 static void dwc2_udc_set_nak(struct dwc2_ep *ep) 940 { 941 u8 ep_num; 942 u32 ep_ctrl = 0; 943 944 ep_num = ep_index(ep); 945 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type); 946 947 if (ep_is_in(ep)) { 948 ep_ctrl = readl(®->in_endp[ep_num].diepctl); 949 ep_ctrl |= DEPCTL_SNAK; 950 writel(ep_ctrl, ®->in_endp[ep_num].diepctl); 951 debug("%s: set NAK, DIEPCTL%d = 0x%x\n", 952 __func__, ep_num, readl(®->in_endp[ep_num].diepctl)); 953 } else { 954 ep_ctrl = readl(®->out_endp[ep_num].doepctl); 955 ep_ctrl |= DEPCTL_SNAK; 956 writel(ep_ctrl, ®->out_endp[ep_num].doepctl); 957 debug("%s: set NAK, DOEPCTL%d = 0x%x\n", 958 __func__, ep_num, readl(®->out_endp[ep_num].doepctl)); 959 } 960 961 return; 962 } 963 964 965 static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep) 966 { 967 u8 ep_num; 968 u32 ep_ctrl = 0; 969 970 ep_num = ep_index(ep); 971 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type); 972 973 if (ep_is_in(ep)) { 974 ep_ctrl = readl(®->in_endp[ep_num].diepctl); 975 976 /* set the disable and stall bits */ 977 if (ep_ctrl & DEPCTL_EPENA) 978 ep_ctrl |= DEPCTL_EPDIS; 979 980 ep_ctrl |= DEPCTL_STALL; 981 982 writel(ep_ctrl, ®->in_endp[ep_num].diepctl); 983 debug("%s: set stall, DIEPCTL%d = 0x%x\n", 984 __func__, ep_num, readl(®->in_endp[ep_num].diepctl)); 985 986 } else { 987 ep_ctrl = readl(®->out_endp[ep_num].doepctl); 988 989 /* set the stall bit */ 990 ep_ctrl |= DEPCTL_STALL; 991 992 writel(ep_ctrl, ®->out_endp[ep_num].doepctl); 993 debug("%s: set stall, DOEPCTL%d = 0x%x\n", 994 __func__, ep_num, readl(®->out_endp[ep_num].doepctl)); 995 } 996 997 return; 998 } 999 1000 static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep) 1001 { 1002 u8 ep_num; 1003 u32 ep_ctrl = 0; 1004 1005 ep_num = ep_index(ep); 1006 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type); 1007 1008 if (ep_is_in(ep)) { 1009 ep_ctrl = readl(®->in_endp[ep_num].diepctl); 1010 1011 /* clear stall bit */ 1012 ep_ctrl &= ~DEPCTL_STALL; 1013 1014 /* 1015 * USB Spec 9.4.5: For endpoints using data toggle, regardless 1016 * of whether an endpoint has the Halt feature set, a 1017 * ClearFeature(ENDPOINT_HALT) request always results in the 1018 * data toggle being reinitialized to DATA0. 1019 */ 1020 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT 1021 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) { 1022 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */ 1023 } 1024 1025 writel(ep_ctrl, ®->in_endp[ep_num].diepctl); 1026 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n", 1027 __func__, ep_num, readl(®->in_endp[ep_num].diepctl)); 1028 1029 } else { 1030 ep_ctrl = readl(®->out_endp[ep_num].doepctl); 1031 1032 /* clear stall bit */ 1033 ep_ctrl &= ~DEPCTL_STALL; 1034 1035 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT 1036 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) { 1037 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */ 1038 } 1039 1040 writel(ep_ctrl, ®->out_endp[ep_num].doepctl); 1041 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n", 1042 __func__, ep_num, readl(®->out_endp[ep_num].doepctl)); 1043 } 1044 1045 return; 1046 } 1047 1048 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value) 1049 { 1050 struct dwc2_ep *ep; 1051 struct dwc2_udc *dev; 1052 unsigned long flags = 0; 1053 u8 ep_num; 1054 1055 ep = container_of(_ep, struct dwc2_ep, ep); 1056 ep_num = ep_index(ep); 1057 1058 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON || 1059 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) { 1060 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name); 1061 return -EINVAL; 1062 } 1063 1064 /* Attempt to halt IN ep will fail if any transfer requests 1065 * are still queue */ 1066 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) { 1067 debug("%s: %s queue not empty, req = %p\n", 1068 __func__, ep->ep.name, 1069 list_entry(ep->queue.next, struct dwc2_request, queue)); 1070 1071 return -EAGAIN; 1072 } 1073 1074 dev = ep->dev; 1075 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value); 1076 1077 spin_lock_irqsave(&dev->lock, flags); 1078 1079 if (value == 0) { 1080 ep->stopped = 0; 1081 dwc2_udc_ep_clear_stall(ep); 1082 } else { 1083 if (ep_num == 0) 1084 dev->ep0state = WAIT_FOR_SETUP; 1085 1086 ep->stopped = 1; 1087 dwc2_udc_ep_set_stall(ep); 1088 } 1089 1090 spin_unlock_irqrestore(&dev->lock, flags); 1091 1092 return 0; 1093 } 1094 1095 static void dwc2_udc_ep_activate(struct dwc2_ep *ep) 1096 { 1097 u8 ep_num; 1098 u32 ep_ctrl = 0, daintmsk = 0; 1099 1100 ep_num = ep_index(ep); 1101 1102 /* Read DEPCTLn register */ 1103 if (ep_is_in(ep)) { 1104 ep_ctrl = readl(®->in_endp[ep_num].diepctl); 1105 daintmsk = 1 << ep_num; 1106 } else { 1107 ep_ctrl = readl(®->out_endp[ep_num].doepctl); 1108 daintmsk = (1 << ep_num) << DAINT_OUT_BIT; 1109 } 1110 1111 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n", 1112 __func__, ep_num, ep_ctrl, ep_is_in(ep)); 1113 1114 /* If the EP is already active don't change the EP Control 1115 * register. */ 1116 if (!(ep_ctrl & DEPCTL_USBACTEP)) { 1117 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) | 1118 (ep->bmAttributes << DEPCTL_TYPE_BIT); 1119 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) | 1120 (ep->ep.maxpacket << DEPCTL_MPS_BIT); 1121 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK); 1122 1123 if (ep_is_in(ep)) { 1124 writel(ep_ctrl, ®->in_endp[ep_num].diepctl); 1125 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n", 1126 __func__, ep_num, ep_num, 1127 readl(®->in_endp[ep_num].diepctl)); 1128 } else { 1129 writel(ep_ctrl, ®->out_endp[ep_num].doepctl); 1130 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n", 1131 __func__, ep_num, ep_num, 1132 readl(®->out_endp[ep_num].doepctl)); 1133 } 1134 } 1135 1136 /* Unmask EP Interrtupt */ 1137 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk); 1138 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk)); 1139 1140 } 1141 1142 static int dwc2_udc_clear_feature(struct usb_ep *_ep) 1143 { 1144 struct dwc2_udc *dev; 1145 struct dwc2_ep *ep; 1146 u8 ep_num; 1147 1148 ep = container_of(_ep, struct dwc2_ep, ep); 1149 ep_num = ep_index(ep); 1150 1151 dev = ep->dev; 1152 debug_cond(DEBUG_SETUP != 0, 1153 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n", 1154 __func__, ep_num, ep_is_in(ep), clear_feature_flag); 1155 1156 if (usb_ctrl->wLength != 0) { 1157 debug_cond(DEBUG_SETUP != 0, 1158 "\tCLEAR_FEATURE: wLength is not zero.....\n"); 1159 return 1; 1160 } 1161 1162 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) { 1163 case USB_RECIP_DEVICE: 1164 switch (usb_ctrl->wValue) { 1165 case USB_DEVICE_REMOTE_WAKEUP: 1166 debug_cond(DEBUG_SETUP != 0, 1167 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n"); 1168 break; 1169 1170 case USB_DEVICE_TEST_MODE: 1171 debug_cond(DEBUG_SETUP != 0, 1172 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n"); 1173 /** @todo Add CLEAR_FEATURE for TEST modes. */ 1174 break; 1175 } 1176 1177 dwc2_udc_ep0_zlp(dev); 1178 break; 1179 1180 case USB_RECIP_ENDPOINT: 1181 debug_cond(DEBUG_SETUP != 0, 1182 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n", 1183 usb_ctrl->wValue); 1184 1185 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) { 1186 if (ep_num == 0) { 1187 dwc2_udc_ep0_set_stall(ep); 1188 return 0; 1189 } 1190 1191 dwc2_udc_ep0_zlp(dev); 1192 1193 dwc2_udc_ep_clear_stall(ep); 1194 dwc2_udc_ep_activate(ep); 1195 ep->stopped = 0; 1196 1197 clear_feature_num = ep_num; 1198 clear_feature_flag = 1; 1199 } 1200 break; 1201 } 1202 1203 return 0; 1204 } 1205 1206 static int dwc2_udc_set_feature(struct usb_ep *_ep) 1207 { 1208 struct dwc2_udc *dev; 1209 struct dwc2_ep *ep; 1210 u8 ep_num; 1211 1212 ep = container_of(_ep, struct dwc2_ep, ep); 1213 ep_num = ep_index(ep); 1214 dev = ep->dev; 1215 1216 debug_cond(DEBUG_SETUP != 0, 1217 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n", 1218 __func__, ep_num); 1219 1220 if (usb_ctrl->wLength != 0) { 1221 debug_cond(DEBUG_SETUP != 0, 1222 "\tSET_FEATURE: wLength is not zero.....\n"); 1223 return 1; 1224 } 1225 1226 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) { 1227 case USB_RECIP_DEVICE: 1228 switch (usb_ctrl->wValue) { 1229 case USB_DEVICE_REMOTE_WAKEUP: 1230 debug_cond(DEBUG_SETUP != 0, 1231 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n"); 1232 break; 1233 case USB_DEVICE_B_HNP_ENABLE: 1234 debug_cond(DEBUG_SETUP != 0, 1235 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n"); 1236 break; 1237 1238 case USB_DEVICE_A_HNP_SUPPORT: 1239 /* RH port supports HNP */ 1240 debug_cond(DEBUG_SETUP != 0, 1241 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n"); 1242 break; 1243 1244 case USB_DEVICE_A_ALT_HNP_SUPPORT: 1245 /* other RH port does */ 1246 debug_cond(DEBUG_SETUP != 0, 1247 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n"); 1248 break; 1249 } 1250 1251 dwc2_udc_ep0_zlp(dev); 1252 return 0; 1253 1254 case USB_RECIP_INTERFACE: 1255 debug_cond(DEBUG_SETUP != 0, 1256 "\tSET_FEATURE: USB_RECIP_INTERFACE\n"); 1257 break; 1258 1259 case USB_RECIP_ENDPOINT: 1260 debug_cond(DEBUG_SETUP != 0, 1261 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n"); 1262 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) { 1263 if (ep_num == 0) { 1264 dwc2_udc_ep0_set_stall(ep); 1265 return 0; 1266 } 1267 ep->stopped = 1; 1268 dwc2_udc_ep_set_stall(ep); 1269 } 1270 1271 dwc2_udc_ep0_zlp(dev); 1272 return 0; 1273 } 1274 1275 return 1; 1276 } 1277 1278 /* 1279 * WAIT_FOR_SETUP (OUT_PKT_RDY) 1280 */ 1281 static void dwc2_ep0_setup(struct dwc2_udc *dev) 1282 { 1283 struct dwc2_ep *ep = &dev->ep[0]; 1284 int i; 1285 u8 ep_num; 1286 1287 /* Nuke all previous transfers */ 1288 nuke(ep, -EPROTO); 1289 1290 /* read control req from fifo (8 bytes) */ 1291 dwc2_fifo_read(ep, (u32 *)usb_ctrl, 8); 1292 1293 debug_cond(DEBUG_SETUP != 0, 1294 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x" 1295 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n", 1296 __func__, usb_ctrl->bRequestType, 1297 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT", 1298 usb_ctrl->bRequest, 1299 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex); 1300 1301 #ifdef DEBUG 1302 { 1303 int i, len = sizeof(*usb_ctrl); 1304 char *p = (char *)usb_ctrl; 1305 1306 printf("pkt = "); 1307 for (i = 0; i < len; i++) { 1308 printf("%02x", ((u8 *)p)[i]); 1309 if ((i & 7) == 7) 1310 printf(" "); 1311 } 1312 printf("\n"); 1313 } 1314 #endif 1315 1316 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST && 1317 usb_ctrl->wLength != 1) { 1318 debug_cond(DEBUG_SETUP != 0, 1319 "\t%s:GET_MAX_LUN_REQUEST:invalid", 1320 __func__); 1321 debug_cond(DEBUG_SETUP != 0, 1322 "wLength = %d, setup returned\n", 1323 usb_ctrl->wLength); 1324 1325 dwc2_udc_ep0_set_stall(ep); 1326 dev->ep0state = WAIT_FOR_SETUP; 1327 1328 return; 1329 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST && 1330 usb_ctrl->wLength != 0) { 1331 /* Bulk-Only *mass storge reset of class-specific request */ 1332 debug_cond(DEBUG_SETUP != 0, 1333 "%s:BOT Rest:invalid wLength =%d, setup returned\n", 1334 __func__, usb_ctrl->wLength); 1335 1336 dwc2_udc_ep0_set_stall(ep); 1337 dev->ep0state = WAIT_FOR_SETUP; 1338 1339 return; 1340 } 1341 1342 /* Set direction of EP0 */ 1343 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) { 1344 ep->bEndpointAddress |= USB_DIR_IN; 1345 } else { 1346 ep->bEndpointAddress &= ~USB_DIR_IN; 1347 } 1348 /* cope with automagic for some standard requests. */ 1349 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK) 1350 == USB_TYPE_STANDARD; 1351 1352 dev->req_pending = 1; 1353 1354 /* Handle some SETUP packets ourselves */ 1355 if (dev->req_std) { 1356 switch (usb_ctrl->bRequest) { 1357 case USB_REQ_SET_ADDRESS: 1358 debug_cond(DEBUG_SETUP != 0, 1359 "%s: *** USB_REQ_SET_ADDRESS (%d)\n", 1360 __func__, usb_ctrl->wValue); 1361 if (usb_ctrl->bRequestType 1362 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) 1363 break; 1364 dev->connected = 1; 1365 udc_set_address(dev, usb_ctrl->wValue); 1366 return; 1367 1368 case USB_REQ_SET_CONFIGURATION: 1369 debug_cond(DEBUG_SETUP != 0, 1370 "=====================================\n"); 1371 debug_cond(DEBUG_SETUP != 0, 1372 "%s: USB_REQ_SET_CONFIGURATION (%d)\n", 1373 __func__, usb_ctrl->wValue); 1374 1375 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE) 1376 reset_available = 1; 1377 1378 break; 1379 1380 case USB_REQ_GET_DESCRIPTOR: 1381 debug_cond(DEBUG_SETUP != 0, 1382 "%s: *** USB_REQ_GET_DESCRIPTOR\n", 1383 __func__); 1384 break; 1385 1386 case USB_REQ_SET_INTERFACE: 1387 debug_cond(DEBUG_SETUP != 0, 1388 "%s: *** USB_REQ_SET_INTERFACE (%d)\n", 1389 __func__, usb_ctrl->wValue); 1390 1391 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE) 1392 reset_available = 1; 1393 1394 break; 1395 1396 case USB_REQ_GET_CONFIGURATION: 1397 debug_cond(DEBUG_SETUP != 0, 1398 "%s: *** USB_REQ_GET_CONFIGURATION\n", 1399 __func__); 1400 break; 1401 1402 case USB_REQ_GET_STATUS: 1403 if (!dwc2_udc_get_status(dev, usb_ctrl)) 1404 return; 1405 1406 break; 1407 1408 case USB_REQ_CLEAR_FEATURE: 1409 ep_num = usb_ctrl->wIndex & 0x7f; 1410 1411 if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep)) 1412 return; 1413 1414 break; 1415 1416 case USB_REQ_SET_FEATURE: 1417 ep_num = usb_ctrl->wIndex & 0x7f; 1418 1419 if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep)) 1420 return; 1421 1422 break; 1423 1424 default: 1425 debug_cond(DEBUG_SETUP != 0, 1426 "%s: *** Default of usb_ctrl->bRequest=0x%x" 1427 "happened.\n", __func__, usb_ctrl->bRequest); 1428 break; 1429 } 1430 } 1431 1432 1433 if (likely(dev->driver)) { 1434 /* device-2-host (IN) or no data setup command, 1435 * process immediately */ 1436 debug_cond(DEBUG_SETUP != 0, 1437 "%s:usb_ctrlreq will be passed to fsg_setup()\n", 1438 __func__); 1439 1440 spin_unlock(&dev->lock); 1441 i = dev->driver->setup(&dev->gadget, usb_ctrl); 1442 spin_lock(&dev->lock); 1443 1444 if (i < 0) { 1445 /* setup processing failed, force stall */ 1446 dwc2_udc_ep0_set_stall(ep); 1447 dev->ep0state = WAIT_FOR_SETUP; 1448 1449 debug_cond(DEBUG_SETUP != 0, 1450 "\tdev->driver->setup failed (%d)," 1451 " bRequest = %d\n", 1452 i, usb_ctrl->bRequest); 1453 1454 1455 } else if (dev->req_pending) { 1456 dev->req_pending = 0; 1457 debug_cond(DEBUG_SETUP != 0, 1458 "\tdev->req_pending...\n"); 1459 } 1460 1461 debug_cond(DEBUG_SETUP != 0, 1462 "\tep0state = %s\n", state_names[dev->ep0state]); 1463 1464 } 1465 } 1466 1467 /* 1468 * handle ep0 interrupt 1469 */ 1470 static void dwc2_handle_ep0(struct dwc2_udc *dev) 1471 { 1472 if (dev->ep0state == WAIT_FOR_SETUP) { 1473 debug_cond(DEBUG_OUT_EP != 0, 1474 "%s: WAIT_FOR_SETUP\n", __func__); 1475 dwc2_ep0_setup(dev); 1476 1477 } else { 1478 debug_cond(DEBUG_OUT_EP != 0, 1479 "%s: strange state!!(state = %s)\n", 1480 __func__, state_names[dev->ep0state]); 1481 } 1482 } 1483 1484 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep) 1485 { 1486 debug_cond(DEBUG_EP0 != 0, 1487 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep)); 1488 if (ep_is_in(ep)) { 1489 dev->ep0state = DATA_STATE_XMIT; 1490 dwc2_ep0_write(dev); 1491 1492 } else { 1493 dev->ep0state = DATA_STATE_RECV; 1494 dwc2_ep0_read(dev); 1495 } 1496 } 1497