1 /* 2 * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c 3 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers 4 * 5 * Copyright (C) 2009 for Samsung Electronics 6 * 7 * BSP Support for Samsung's UDC driver 8 * available at: 9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git 10 * 11 * State machine bugfixes: 12 * Marek Szyprowski <m.szyprowski@samsung.com> 13 * 14 * Ported to u-boot: 15 * Marek Szyprowski <m.szyprowski@samsung.com> 16 * Lukasz Majewski <l.majewski@samsumg.com> 17 * 18 * SPDX-License-Identifier: GPL-2.0+ 19 */ 20 21 static u8 clear_feature_num; 22 int clear_feature_flag; 23 24 /* Bulk-Only Mass Storage Reset (class-specific request) */ 25 #define GET_MAX_LUN_REQUEST 0xFE 26 #define BOT_RESET_REQUEST 0xFF 27 28 static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev) 29 { 30 u32 ep_ctrl; 31 32 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); 33 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz); 34 35 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl); 36 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, 37 ®->in_endp[EP0_CON].diepctl); 38 39 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n", 40 __func__, readl(®->in_endp[EP0_CON].diepctl)); 41 dev->ep0state = WAIT_FOR_IN_COMPLETE; 42 } 43 44 static void dwc2_udc_pre_setup(void) 45 { 46 u32 ep_ctrl; 47 48 debug_cond(DEBUG_IN_EP, 49 "%s : Prepare Setup packets.\n", __func__); 50 51 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), 52 ®->out_endp[EP0_CON].doeptsiz); 53 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); 54 55 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl); 56 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl); 57 58 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n", 59 __func__, readl(®->in_endp[EP0_CON].diepctl)); 60 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n", 61 __func__, readl(®->out_endp[EP0_CON].doepctl)); 62 63 } 64 65 static inline void dwc2_ep0_complete_out(void) 66 { 67 u32 ep_ctrl; 68 69 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n", 70 __func__, readl(®->in_endp[EP0_CON].diepctl)); 71 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n", 72 __func__, readl(®->out_endp[EP0_CON].doepctl)); 73 74 debug_cond(DEBUG_IN_EP, 75 "%s : Prepare Complete Out packet.\n", __func__); 76 77 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), 78 ®->out_endp[EP0_CON].doeptsiz); 79 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); 80 81 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl); 82 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, 83 ®->out_endp[EP0_CON].doepctl); 84 85 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n", 86 __func__, readl(®->in_endp[EP0_CON].diepctl)); 87 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n", 88 __func__, readl(®->out_endp[EP0_CON].doepctl)); 89 90 } 91 92 93 static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req) 94 { 95 u32 *buf, ctrl; 96 u32 length, pktcnt; 97 u32 ep_num = ep_index(ep); 98 99 buf = req->req.buf + req->req.actual; 100 length = min_t(u32, req->req.length - req->req.actual, 101 ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket); 102 103 ep->len = length; 104 ep->dma_buf = buf; 105 106 if (ep_num == EP0_CON || length == 0) 107 pktcnt = 1; 108 else 109 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1; 110 111 ctrl = readl(®->out_endp[ep_num].doepctl); 112 113 invalidate_dcache_range((unsigned long) ep->dma_buf, 114 (unsigned long) ep->dma_buf + 115 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE)); 116 117 writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma); 118 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), 119 ®->out_endp[ep_num].doeptsiz); 120 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl); 121 122 debug_cond(DEBUG_OUT_EP != 0, 123 "%s: EP%d RX DMA start : DOEPDMA = 0x%x," 124 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n" 125 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n", 126 __func__, ep_num, 127 readl(®->out_endp[ep_num].doepdma), 128 readl(®->out_endp[ep_num].doeptsiz), 129 readl(®->out_endp[ep_num].doepctl), 130 buf, pktcnt, length); 131 return 0; 132 133 } 134 135 static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req) 136 { 137 u32 *buf, ctrl = 0; 138 u32 length, pktcnt; 139 u32 ep_num = ep_index(ep); 140 141 buf = req->req.buf + req->req.actual; 142 length = req->req.length - req->req.actual; 143 144 if (ep_num == EP0_CON) 145 length = min(length, (u32)ep_maxpacket(ep)); 146 147 ep->len = length; 148 ep->dma_buf = buf; 149 150 flush_dcache_range((unsigned long) ep->dma_buf, 151 (unsigned long) ep->dma_buf + 152 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE)); 153 154 if (length == 0) 155 pktcnt = 1; 156 else 157 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1; 158 159 /* Flush the endpoint's Tx FIFO */ 160 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl); 161 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl); 162 while (readl(®->grstctl) & TX_FIFO_FLUSH) 163 ; 164 165 writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma); 166 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length), 167 ®->in_endp[ep_num].dieptsiz); 168 169 ctrl = readl(®->in_endp[ep_num].diepctl); 170 171 /* Write the FIFO number to be used for this endpoint */ 172 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK; 173 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num); 174 175 /* Clear reserved (Next EP) bits */ 176 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT)); 177 178 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl); 179 180 debug_cond(DEBUG_IN_EP, 181 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x," 182 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n" 183 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n", 184 __func__, ep_num, 185 readl(®->in_endp[ep_num].diepdma), 186 readl(®->in_endp[ep_num].dieptsiz), 187 readl(®->in_endp[ep_num].diepctl), 188 buf, pktcnt, length); 189 190 return length; 191 } 192 193 static void complete_rx(struct dwc2_udc *dev, u8 ep_num) 194 { 195 struct dwc2_ep *ep = &dev->ep[ep_num]; 196 struct dwc2_request *req = NULL; 197 u32 ep_tsr = 0, xfer_size = 0, is_short = 0; 198 199 if (list_empty(&ep->queue)) { 200 debug_cond(DEBUG_OUT_EP != 0, 201 "%s: RX DMA done : NULL REQ on OUT EP-%d\n", 202 __func__, ep_num); 203 return; 204 205 } 206 207 req = list_entry(ep->queue.next, struct dwc2_request, queue); 208 ep_tsr = readl(®->out_endp[ep_num].doeptsiz); 209 210 if (ep_num == EP0_CON) 211 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0); 212 else 213 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP); 214 215 xfer_size = ep->len - xfer_size; 216 217 /* 218 * NOTE: 219 * 220 * Please be careful with proper buffer allocation for USB request, 221 * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only 222 * with starting address, but also its size shall be a cache line 223 * multiplication. 224 * 225 * This will prevent from corruption of data allocated immediatelly 226 * before or after the buffer. 227 * 228 * For armv7, the cache_v7.c provides proper code to emit "ERROR" 229 * message to warn users. 230 */ 231 invalidate_dcache_range((unsigned long) ep->dma_buf, 232 (unsigned long) ep->dma_buf + 233 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE)); 234 235 req->req.actual += min(xfer_size, req->req.length - req->req.actual); 236 is_short = !!(xfer_size % ep->ep.maxpacket); 237 238 debug_cond(DEBUG_OUT_EP != 0, 239 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, " 240 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n", 241 __func__, ep_num, req->req.actual, req->req.length, 242 is_short, ep_tsr, req->req.length - req->req.actual); 243 244 if (is_short || req->req.actual == req->req.length) { 245 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) { 246 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n"); 247 dwc2_udc_ep0_zlp(dev); 248 /* packet will be completed in complete_tx() */ 249 dev->ep0state = WAIT_FOR_IN_COMPLETE; 250 } else { 251 done(ep, req, 0); 252 253 if (!list_empty(&ep->queue)) { 254 req = list_entry(ep->queue.next, 255 struct dwc2_request, queue); 256 debug_cond(DEBUG_OUT_EP != 0, 257 "%s: Next Rx request start...\n", 258 __func__); 259 setdma_rx(ep, req); 260 } 261 } 262 } else 263 setdma_rx(ep, req); 264 } 265 266 static void complete_tx(struct dwc2_udc *dev, u8 ep_num) 267 { 268 struct dwc2_ep *ep = &dev->ep[ep_num]; 269 struct dwc2_request *req; 270 u32 ep_tsr = 0, xfer_size = 0, is_short = 0; 271 u32 last; 272 273 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) { 274 dev->ep0state = WAIT_FOR_OUT_COMPLETE; 275 dwc2_ep0_complete_out(); 276 return; 277 } 278 279 if (list_empty(&ep->queue)) { 280 debug_cond(DEBUG_IN_EP, 281 "%s: TX DMA done : NULL REQ on IN EP-%d\n", 282 __func__, ep_num); 283 return; 284 285 } 286 287 req = list_entry(ep->queue.next, struct dwc2_request, queue); 288 289 ep_tsr = readl(®->in_endp[ep_num].dieptsiz); 290 291 xfer_size = ep->len; 292 is_short = (xfer_size < ep->ep.maxpacket); 293 req->req.actual += min(xfer_size, req->req.length - req->req.actual); 294 295 debug_cond(DEBUG_IN_EP, 296 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, " 297 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n", 298 __func__, ep_num, req->req.actual, req->req.length, 299 is_short, ep_tsr, req->req.length - req->req.actual); 300 301 if (ep_num == 0) { 302 if (dev->ep0state == DATA_STATE_XMIT) { 303 debug_cond(DEBUG_IN_EP, 304 "%s: ep_num = %d, ep0stat ==" 305 "DATA_STATE_XMIT\n", 306 __func__, ep_num); 307 last = write_fifo_ep0(ep, req); 308 if (last) 309 dev->ep0state = WAIT_FOR_COMPLETE; 310 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) { 311 debug_cond(DEBUG_IN_EP, 312 "%s: ep_num = %d, completing request\n", 313 __func__, ep_num); 314 done(ep, req, 0); 315 dev->ep0state = WAIT_FOR_SETUP; 316 } else if (dev->ep0state == WAIT_FOR_COMPLETE) { 317 debug_cond(DEBUG_IN_EP, 318 "%s: ep_num = %d, completing request\n", 319 __func__, ep_num); 320 done(ep, req, 0); 321 dev->ep0state = WAIT_FOR_OUT_COMPLETE; 322 dwc2_ep0_complete_out(); 323 } else { 324 debug_cond(DEBUG_IN_EP, 325 "%s: ep_num = %d, invalid ep state\n", 326 __func__, ep_num); 327 } 328 return; 329 } 330 331 if (req->req.actual == req->req.length) 332 done(ep, req, 0); 333 334 if (!list_empty(&ep->queue)) { 335 req = list_entry(ep->queue.next, struct dwc2_request, queue); 336 debug_cond(DEBUG_IN_EP, 337 "%s: Next Tx request start...\n", __func__); 338 setdma_tx(ep, req); 339 } 340 } 341 342 static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num) 343 { 344 struct dwc2_ep *ep = &dev->ep[ep_num]; 345 struct dwc2_request *req; 346 347 debug_cond(DEBUG_IN_EP, 348 "%s: Check queue, ep_num = %d\n", __func__, ep_num); 349 350 if (!list_empty(&ep->queue)) { 351 req = list_entry(ep->queue.next, struct dwc2_request, queue); 352 debug_cond(DEBUG_IN_EP, 353 "%s: Next Tx request(0x%p) start...\n", 354 __func__, req); 355 356 if (ep_is_in(ep)) 357 setdma_tx(ep, req); 358 else 359 setdma_rx(ep, req); 360 } else { 361 debug_cond(DEBUG_IN_EP, 362 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num); 363 364 return; 365 } 366 367 } 368 369 static void process_ep_in_intr(struct dwc2_udc *dev) 370 { 371 u32 ep_intr, ep_intr_status; 372 u8 ep_num = 0; 373 374 ep_intr = readl(®->daint); 375 debug_cond(DEBUG_IN_EP, 376 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr); 377 378 ep_intr &= DAINT_MASK; 379 380 while (ep_intr) { 381 if (ep_intr & DAINT_IN_EP_INT(1)) { 382 ep_intr_status = readl(®->in_endp[ep_num].diepint); 383 debug_cond(DEBUG_IN_EP, 384 "\tEP%d-IN : DIEPINT = 0x%x\n", 385 ep_num, ep_intr_status); 386 387 /* Interrupt Clear */ 388 writel(ep_intr_status, ®->in_endp[ep_num].diepint); 389 390 if (ep_intr_status & TRANSFER_DONE) { 391 complete_tx(dev, ep_num); 392 393 if (ep_num == 0) { 394 if (dev->ep0state == 395 WAIT_FOR_IN_COMPLETE) 396 dev->ep0state = WAIT_FOR_SETUP; 397 398 if (dev->ep0state == WAIT_FOR_SETUP) 399 dwc2_udc_pre_setup(); 400 401 /* continue transfer after 402 set_clear_halt for DMA mode */ 403 if (clear_feature_flag == 1) { 404 dwc2_udc_check_tx_queue(dev, 405 clear_feature_num); 406 clear_feature_flag = 0; 407 } 408 } 409 } 410 } 411 ep_num++; 412 ep_intr >>= 1; 413 } 414 } 415 416 static void process_ep_out_intr(struct dwc2_udc *dev) 417 { 418 u32 ep_intr, ep_intr_status; 419 u8 ep_num = 0; 420 421 ep_intr = readl(®->daint); 422 debug_cond(DEBUG_OUT_EP != 0, 423 "*** %s: EP OUT interrupt : DAINT = 0x%x\n", 424 __func__, ep_intr); 425 426 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK; 427 428 while (ep_intr) { 429 if (ep_intr & 0x1) { 430 ep_intr_status = readl(®->out_endp[ep_num].doepint); 431 debug_cond(DEBUG_OUT_EP != 0, 432 "\tEP%d-OUT : DOEPINT = 0x%x\n", 433 ep_num, ep_intr_status); 434 435 /* Interrupt Clear */ 436 writel(ep_intr_status, ®->out_endp[ep_num].doepint); 437 438 if (ep_num == 0) { 439 if (ep_intr_status & TRANSFER_DONE) { 440 if (dev->ep0state != 441 WAIT_FOR_OUT_COMPLETE) 442 complete_rx(dev, ep_num); 443 else { 444 dev->ep0state = WAIT_FOR_SETUP; 445 dwc2_udc_pre_setup(); 446 } 447 } 448 449 if (ep_intr_status & 450 CTRL_OUT_EP_SETUP_PHASE_DONE) { 451 debug_cond(DEBUG_OUT_EP != 0, 452 "SETUP packet arrived\n"); 453 dwc2_handle_ep0(dev); 454 } 455 } else { 456 if (ep_intr_status & TRANSFER_DONE) 457 complete_rx(dev, ep_num); 458 } 459 } 460 ep_num++; 461 ep_intr >>= 1; 462 } 463 } 464 465 /* 466 * usb client interrupt handler. 467 */ 468 static int dwc2_udc_irq(int irq, void *_dev) 469 { 470 struct dwc2_udc *dev = _dev; 471 u32 intr_status; 472 u32 usb_status, gintmsk; 473 unsigned long flags = 0; 474 475 spin_lock_irqsave(&dev->lock, flags); 476 477 intr_status = readl(®->gintsts); 478 gintmsk = readl(®->gintmsk); 479 480 debug_cond(DEBUG_ISR, 481 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x," 482 "DAINT : 0x%x, DAINTMSK : 0x%x\n", 483 __func__, intr_status, state_names[dev->ep0state], gintmsk, 484 readl(®->daint), readl(®->daintmsk)); 485 486 if (!intr_status) { 487 spin_unlock_irqrestore(&dev->lock, flags); 488 return IRQ_HANDLED; 489 } 490 491 if (intr_status & INT_ENUMDONE) { 492 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n"); 493 494 writel(INT_ENUMDONE, ®->gintsts); 495 usb_status = (readl(®->dsts) & 0x6); 496 497 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) { 498 debug_cond(DEBUG_ISR, 499 "\t\tFull Speed Detection\n"); 500 set_max_pktsize(dev, USB_SPEED_FULL); 501 502 } else { 503 debug_cond(DEBUG_ISR, 504 "\t\tHigh Speed Detection : 0x%x\n", 505 usb_status); 506 set_max_pktsize(dev, USB_SPEED_HIGH); 507 } 508 } 509 510 if (intr_status & INT_EARLY_SUSPEND) { 511 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n"); 512 writel(INT_EARLY_SUSPEND, ®->gintsts); 513 } 514 515 if (intr_status & INT_SUSPEND) { 516 usb_status = readl(®->dsts); 517 debug_cond(DEBUG_ISR, 518 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status); 519 writel(INT_SUSPEND, ®->gintsts); 520 521 if (dev->gadget.speed != USB_SPEED_UNKNOWN 522 && dev->driver) { 523 if (dev->driver->suspend) 524 dev->driver->suspend(&dev->gadget); 525 526 /* HACK to let gadget detect disconnected state */ 527 if (dev->driver->disconnect) { 528 spin_unlock_irqrestore(&dev->lock, flags); 529 dev->driver->disconnect(&dev->gadget); 530 spin_lock_irqsave(&dev->lock, flags); 531 } 532 } 533 } 534 535 if (intr_status & INT_RESUME) { 536 debug_cond(DEBUG_ISR, "\tResume interrupt\n"); 537 writel(INT_RESUME, ®->gintsts); 538 539 if (dev->gadget.speed != USB_SPEED_UNKNOWN 540 && dev->driver 541 && dev->driver->resume) { 542 543 dev->driver->resume(&dev->gadget); 544 } 545 } 546 547 if (intr_status & INT_RESET) { 548 u32 temp; 549 u32 connected = dev->connected; 550 551 usb_status = readl(®->gotgctl); 552 debug_cond(DEBUG_ISR, 553 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status); 554 writel(INT_RESET, ®->gintsts); 555 556 if ((usb_status & 0xc0000) == (0x3 << 18)) { 557 if (reset_available) { 558 debug_cond(DEBUG_ISR, 559 "\t\tOTG core got reset (%d)!!\n", 560 reset_available); 561 /* Reset device address to zero */ 562 temp = readl(®->dcfg); 563 temp &= ~DCFG_DEVADDR_MASK; 564 writel(temp, ®->dcfg); 565 566 /* Soft reset the core if connected */ 567 if (connected) 568 reconfig_usbd(dev); 569 570 dev->ep0state = WAIT_FOR_SETUP; 571 reset_available = 0; 572 dwc2_udc_pre_setup(); 573 } else 574 reset_available = 1; 575 576 } else { 577 reset_available = 1; 578 debug_cond(DEBUG_ISR, 579 "\t\tRESET handling skipped\n"); 580 } 581 } 582 583 if (intr_status & INT_IN_EP) 584 process_ep_in_intr(dev); 585 586 if (intr_status & INT_OUT_EP) 587 process_ep_out_intr(dev); 588 589 spin_unlock_irqrestore(&dev->lock, flags); 590 591 return IRQ_HANDLED; 592 } 593 594 /** Queue one request 595 * Kickstart transfer if needed 596 */ 597 static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req, 598 gfp_t gfp_flags) 599 { 600 struct dwc2_request *req; 601 struct dwc2_ep *ep; 602 struct dwc2_udc *dev; 603 unsigned long flags = 0; 604 u32 ep_num, gintsts; 605 606 req = container_of(_req, struct dwc2_request, req); 607 if (unlikely(!_req || !_req->complete || !_req->buf 608 || !list_empty(&req->queue))) { 609 610 debug("%s: bad params\n", __func__); 611 return -EINVAL; 612 } 613 614 ep = container_of(_ep, struct dwc2_ep, ep); 615 616 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { 617 618 debug("%s: bad ep: %s, %d, %p\n", __func__, 619 ep->ep.name, !ep->desc, _ep); 620 return -EINVAL; 621 } 622 623 ep_num = ep_index(ep); 624 dev = ep->dev; 625 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { 626 627 debug("%s: bogus device state %p\n", __func__, dev->driver); 628 return -ESHUTDOWN; 629 } 630 631 spin_lock_irqsave(&dev->lock, flags); 632 633 _req->status = -EINPROGRESS; 634 _req->actual = 0; 635 636 /* kickstart this i/o queue? */ 637 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p" 638 "Q empty = %d, stopped = %d\n", 639 __func__, _ep->name, ep_is_in(ep) ? "in" : "out", 640 _req, _req->length, _req->buf, 641 list_empty(&ep->queue), ep->stopped); 642 643 #ifdef DEBUG 644 { 645 int i, len = _req->length; 646 647 printf("pkt = "); 648 if (len > 64) 649 len = 64; 650 for (i = 0; i < len; i++) { 651 printf("%02x", ((u8 *)_req->buf)[i]); 652 if ((i & 7) == 7) 653 printf(" "); 654 } 655 printf("\n"); 656 } 657 #endif 658 659 if (list_empty(&ep->queue) && !ep->stopped) { 660 661 if (ep_num == 0) { 662 /* EP0 */ 663 list_add_tail(&req->queue, &ep->queue); 664 dwc2_ep0_kick(dev, ep); 665 req = 0; 666 667 } else if (ep_is_in(ep)) { 668 gintsts = readl(®->gintsts); 669 debug_cond(DEBUG_IN_EP, 670 "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n", 671 __func__, gintsts); 672 673 setdma_tx(ep, req); 674 } else { 675 gintsts = readl(®->gintsts); 676 debug_cond(DEBUG_OUT_EP != 0, 677 "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n", 678 __func__, gintsts); 679 680 setdma_rx(ep, req); 681 } 682 } 683 684 /* pio or dma irq handler advances the queue. */ 685 if (likely(req != 0)) 686 list_add_tail(&req->queue, &ep->queue); 687 688 spin_unlock_irqrestore(&dev->lock, flags); 689 690 return 0; 691 } 692 693 /****************************************************************/ 694 /* End Point 0 related functions */ 695 /****************************************************************/ 696 697 /* return: 0 = still running, 1 = completed, negative = errno */ 698 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req) 699 { 700 u32 max; 701 unsigned count; 702 int is_last; 703 704 max = ep_maxpacket(ep); 705 706 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max); 707 708 count = setdma_tx(ep, req); 709 710 /* last packet is usually short (or a zlp) */ 711 if (likely(count != max)) 712 is_last = 1; 713 else { 714 if (likely(req->req.length != req->req.actual + count) 715 || req->req.zero) 716 is_last = 0; 717 else 718 is_last = 1; 719 } 720 721 debug_cond(DEBUG_EP0 != 0, 722 "%s: wrote %s %d bytes%s %d left %p\n", __func__, 723 ep->ep.name, count, 724 is_last ? "/L" : "", 725 req->req.length - req->req.actual - count, req); 726 727 /* requests complete when all IN data is in the FIFO */ 728 if (is_last) { 729 ep->dev->ep0state = WAIT_FOR_SETUP; 730 return 1; 731 } 732 733 return 0; 734 } 735 736 static int dwc2_fifo_read(struct dwc2_ep *ep, u32 *cp, int max) 737 { 738 invalidate_dcache_range((unsigned long)cp, (unsigned long)cp + 739 ROUND(max, CONFIG_SYS_CACHELINE_SIZE)); 740 741 debug_cond(DEBUG_EP0 != 0, 742 "%s: bytes=%d, ep_index=%d 0x%p\n", __func__, 743 max, ep_index(ep), cp); 744 745 return max; 746 } 747 748 /** 749 * udc_set_address - set the USB address for this device 750 * @address: 751 * 752 * Called from control endpoint function 753 * after it decodes a set address setup packet. 754 */ 755 static void udc_set_address(struct dwc2_udc *dev, unsigned char address) 756 { 757 u32 ctrl = readl(®->dcfg); 758 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg); 759 760 dwc2_udc_ep0_zlp(dev); 761 762 debug_cond(DEBUG_EP0 != 0, 763 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n", 764 __func__, address, readl(®->dcfg)); 765 766 dev->usb_address = address; 767 } 768 769 static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep) 770 { 771 struct dwc2_udc *dev; 772 u32 ep_ctrl = 0; 773 774 dev = ep->dev; 775 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl); 776 777 /* set the disable and stall bits */ 778 if (ep_ctrl & DEPCTL_EPENA) 779 ep_ctrl |= DEPCTL_EPDIS; 780 781 ep_ctrl |= DEPCTL_STALL; 782 783 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl); 784 785 debug_cond(DEBUG_EP0 != 0, 786 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n", 787 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl); 788 /* 789 * The application can only set this bit, and the core clears it, 790 * when a SETUP token is received for this endpoint 791 */ 792 dev->ep0state = WAIT_FOR_SETUP; 793 794 dwc2_udc_pre_setup(); 795 } 796 797 static void dwc2_ep0_read(struct dwc2_udc *dev) 798 { 799 struct dwc2_request *req; 800 struct dwc2_ep *ep = &dev->ep[0]; 801 802 if (!list_empty(&ep->queue)) { 803 req = list_entry(ep->queue.next, struct dwc2_request, queue); 804 805 } else { 806 debug("%s: ---> BUG\n", __func__); 807 BUG(); 808 return; 809 } 810 811 debug_cond(DEBUG_EP0 != 0, 812 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n", 813 __func__, req, req->req.length, req->req.actual); 814 815 if (req->req.length == 0) { 816 /* zlp for Set_configuration, Set_interface, 817 * or Bulk-Only mass storge reset */ 818 819 ep->len = 0; 820 dwc2_udc_ep0_zlp(dev); 821 822 debug_cond(DEBUG_EP0 != 0, 823 "%s: req.length = 0, bRequest = %d\n", 824 __func__, usb_ctrl->bRequest); 825 return; 826 } 827 828 setdma_rx(ep, req); 829 } 830 831 /* 832 * DATA_STATE_XMIT 833 */ 834 static int dwc2_ep0_write(struct dwc2_udc *dev) 835 { 836 struct dwc2_request *req; 837 struct dwc2_ep *ep = &dev->ep[0]; 838 int ret, need_zlp = 0; 839 840 if (list_empty(&ep->queue)) 841 req = 0; 842 else 843 req = list_entry(ep->queue.next, struct dwc2_request, queue); 844 845 if (!req) { 846 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__); 847 return 0; 848 } 849 850 debug_cond(DEBUG_EP0 != 0, 851 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n", 852 __func__, req, req->req.length, req->req.actual); 853 854 if (req->req.length - req->req.actual == ep0_fifo_size) { 855 /* Next write will end with the packet size, */ 856 /* so we need Zero-length-packet */ 857 need_zlp = 1; 858 } 859 860 ret = write_fifo_ep0(ep, req); 861 862 if ((ret == 1) && !need_zlp) { 863 /* Last packet */ 864 dev->ep0state = WAIT_FOR_COMPLETE; 865 debug_cond(DEBUG_EP0 != 0, 866 "%s: finished, waiting for status\n", __func__); 867 868 } else { 869 dev->ep0state = DATA_STATE_XMIT; 870 debug_cond(DEBUG_EP0 != 0, 871 "%s: not finished\n", __func__); 872 } 873 874 return 1; 875 } 876 877 static int dwc2_udc_get_status(struct dwc2_udc *dev, 878 struct usb_ctrlrequest *crq) 879 { 880 u8 ep_num = crq->wIndex & 0x7F; 881 u16 g_status = 0; 882 u32 ep_ctrl; 883 884 debug_cond(DEBUG_SETUP != 0, 885 "%s: *** USB_REQ_GET_STATUS\n", __func__); 886 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK); 887 switch (crq->bRequestType & USB_RECIP_MASK) { 888 case USB_RECIP_INTERFACE: 889 g_status = 0; 890 debug_cond(DEBUG_SETUP != 0, 891 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n", 892 g_status); 893 break; 894 895 case USB_RECIP_DEVICE: 896 g_status = 0x1; /* Self powered */ 897 debug_cond(DEBUG_SETUP != 0, 898 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n", 899 g_status); 900 break; 901 902 case USB_RECIP_ENDPOINT: 903 if (crq->wLength > 2) { 904 debug_cond(DEBUG_SETUP != 0, 905 "\tGET_STATUS:Not support EP or wLength\n"); 906 return 1; 907 } 908 909 g_status = dev->ep[ep_num].stopped; 910 debug_cond(DEBUG_SETUP != 0, 911 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n", 912 g_status); 913 914 break; 915 916 default: 917 return 1; 918 } 919 920 memcpy(usb_ctrl, &g_status, sizeof(g_status)); 921 922 flush_dcache_range((unsigned long) usb_ctrl, 923 (unsigned long) usb_ctrl + 924 ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE)); 925 926 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); 927 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2), 928 ®->in_endp[EP0_CON].dieptsiz); 929 930 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl); 931 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, 932 ®->in_endp[EP0_CON].diepctl); 933 dev->ep0state = WAIT_FOR_NULL_COMPLETE; 934 935 return 0; 936 } 937 938 static void dwc2_udc_set_nak(struct dwc2_ep *ep) 939 { 940 u8 ep_num; 941 u32 ep_ctrl = 0; 942 943 ep_num = ep_index(ep); 944 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type); 945 946 if (ep_is_in(ep)) { 947 ep_ctrl = readl(®->in_endp[ep_num].diepctl); 948 ep_ctrl |= DEPCTL_SNAK; 949 writel(ep_ctrl, ®->in_endp[ep_num].diepctl); 950 debug("%s: set NAK, DIEPCTL%d = 0x%x\n", 951 __func__, ep_num, readl(®->in_endp[ep_num].diepctl)); 952 } else { 953 ep_ctrl = readl(®->out_endp[ep_num].doepctl); 954 ep_ctrl |= DEPCTL_SNAK; 955 writel(ep_ctrl, ®->out_endp[ep_num].doepctl); 956 debug("%s: set NAK, DOEPCTL%d = 0x%x\n", 957 __func__, ep_num, readl(®->out_endp[ep_num].doepctl)); 958 } 959 960 return; 961 } 962 963 964 static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep) 965 { 966 u8 ep_num; 967 u32 ep_ctrl = 0; 968 969 ep_num = ep_index(ep); 970 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type); 971 972 if (ep_is_in(ep)) { 973 ep_ctrl = readl(®->in_endp[ep_num].diepctl); 974 975 /* set the disable and stall bits */ 976 if (ep_ctrl & DEPCTL_EPENA) 977 ep_ctrl |= DEPCTL_EPDIS; 978 979 ep_ctrl |= DEPCTL_STALL; 980 981 writel(ep_ctrl, ®->in_endp[ep_num].diepctl); 982 debug("%s: set stall, DIEPCTL%d = 0x%x\n", 983 __func__, ep_num, readl(®->in_endp[ep_num].diepctl)); 984 985 } else { 986 ep_ctrl = readl(®->out_endp[ep_num].doepctl); 987 988 /* set the stall bit */ 989 ep_ctrl |= DEPCTL_STALL; 990 991 writel(ep_ctrl, ®->out_endp[ep_num].doepctl); 992 debug("%s: set stall, DOEPCTL%d = 0x%x\n", 993 __func__, ep_num, readl(®->out_endp[ep_num].doepctl)); 994 } 995 996 return; 997 } 998 999 static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep) 1000 { 1001 u8 ep_num; 1002 u32 ep_ctrl = 0; 1003 1004 ep_num = ep_index(ep); 1005 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type); 1006 1007 if (ep_is_in(ep)) { 1008 ep_ctrl = readl(®->in_endp[ep_num].diepctl); 1009 1010 /* clear stall bit */ 1011 ep_ctrl &= ~DEPCTL_STALL; 1012 1013 /* 1014 * USB Spec 9.4.5: For endpoints using data toggle, regardless 1015 * of whether an endpoint has the Halt feature set, a 1016 * ClearFeature(ENDPOINT_HALT) request always results in the 1017 * data toggle being reinitialized to DATA0. 1018 */ 1019 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT 1020 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) { 1021 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */ 1022 } 1023 1024 writel(ep_ctrl, ®->in_endp[ep_num].diepctl); 1025 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n", 1026 __func__, ep_num, readl(®->in_endp[ep_num].diepctl)); 1027 1028 } else { 1029 ep_ctrl = readl(®->out_endp[ep_num].doepctl); 1030 1031 /* clear stall bit */ 1032 ep_ctrl &= ~DEPCTL_STALL; 1033 1034 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT 1035 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) { 1036 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */ 1037 } 1038 1039 writel(ep_ctrl, ®->out_endp[ep_num].doepctl); 1040 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n", 1041 __func__, ep_num, readl(®->out_endp[ep_num].doepctl)); 1042 } 1043 1044 return; 1045 } 1046 1047 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value) 1048 { 1049 struct dwc2_ep *ep; 1050 struct dwc2_udc *dev; 1051 unsigned long flags = 0; 1052 u8 ep_num; 1053 1054 ep = container_of(_ep, struct dwc2_ep, ep); 1055 ep_num = ep_index(ep); 1056 1057 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON || 1058 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) { 1059 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name); 1060 return -EINVAL; 1061 } 1062 1063 /* Attempt to halt IN ep will fail if any transfer requests 1064 * are still queue */ 1065 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) { 1066 debug("%s: %s queue not empty, req = %p\n", 1067 __func__, ep->ep.name, 1068 list_entry(ep->queue.next, struct dwc2_request, queue)); 1069 1070 return -EAGAIN; 1071 } 1072 1073 dev = ep->dev; 1074 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value); 1075 1076 spin_lock_irqsave(&dev->lock, flags); 1077 1078 if (value == 0) { 1079 ep->stopped = 0; 1080 dwc2_udc_ep_clear_stall(ep); 1081 } else { 1082 if (ep_num == 0) 1083 dev->ep0state = WAIT_FOR_SETUP; 1084 1085 ep->stopped = 1; 1086 dwc2_udc_ep_set_stall(ep); 1087 } 1088 1089 spin_unlock_irqrestore(&dev->lock, flags); 1090 1091 return 0; 1092 } 1093 1094 static void dwc2_udc_ep_activate(struct dwc2_ep *ep) 1095 { 1096 u8 ep_num; 1097 u32 ep_ctrl = 0, daintmsk = 0; 1098 1099 ep_num = ep_index(ep); 1100 1101 /* Read DEPCTLn register */ 1102 if (ep_is_in(ep)) { 1103 ep_ctrl = readl(®->in_endp[ep_num].diepctl); 1104 daintmsk = 1 << ep_num; 1105 } else { 1106 ep_ctrl = readl(®->out_endp[ep_num].doepctl); 1107 daintmsk = (1 << ep_num) << DAINT_OUT_BIT; 1108 } 1109 1110 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n", 1111 __func__, ep_num, ep_ctrl, ep_is_in(ep)); 1112 1113 /* If the EP is already active don't change the EP Control 1114 * register. */ 1115 if (!(ep_ctrl & DEPCTL_USBACTEP)) { 1116 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) | 1117 (ep->bmAttributes << DEPCTL_TYPE_BIT); 1118 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) | 1119 (ep->ep.maxpacket << DEPCTL_MPS_BIT); 1120 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK); 1121 1122 if (ep_is_in(ep)) { 1123 writel(ep_ctrl, ®->in_endp[ep_num].diepctl); 1124 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n", 1125 __func__, ep_num, ep_num, 1126 readl(®->in_endp[ep_num].diepctl)); 1127 } else { 1128 writel(ep_ctrl, ®->out_endp[ep_num].doepctl); 1129 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n", 1130 __func__, ep_num, ep_num, 1131 readl(®->out_endp[ep_num].doepctl)); 1132 } 1133 } 1134 1135 /* Unmask EP Interrtupt */ 1136 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk); 1137 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk)); 1138 1139 } 1140 1141 static int dwc2_udc_clear_feature(struct usb_ep *_ep) 1142 { 1143 struct dwc2_udc *dev; 1144 struct dwc2_ep *ep; 1145 u8 ep_num; 1146 1147 ep = container_of(_ep, struct dwc2_ep, ep); 1148 ep_num = ep_index(ep); 1149 1150 dev = ep->dev; 1151 debug_cond(DEBUG_SETUP != 0, 1152 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n", 1153 __func__, ep_num, ep_is_in(ep), clear_feature_flag); 1154 1155 if (usb_ctrl->wLength != 0) { 1156 debug_cond(DEBUG_SETUP != 0, 1157 "\tCLEAR_FEATURE: wLength is not zero.....\n"); 1158 return 1; 1159 } 1160 1161 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) { 1162 case USB_RECIP_DEVICE: 1163 switch (usb_ctrl->wValue) { 1164 case USB_DEVICE_REMOTE_WAKEUP: 1165 debug_cond(DEBUG_SETUP != 0, 1166 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n"); 1167 break; 1168 1169 case USB_DEVICE_TEST_MODE: 1170 debug_cond(DEBUG_SETUP != 0, 1171 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n"); 1172 /** @todo Add CLEAR_FEATURE for TEST modes. */ 1173 break; 1174 } 1175 1176 dwc2_udc_ep0_zlp(dev); 1177 break; 1178 1179 case USB_RECIP_ENDPOINT: 1180 debug_cond(DEBUG_SETUP != 0, 1181 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n", 1182 usb_ctrl->wValue); 1183 1184 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) { 1185 if (ep_num == 0) { 1186 dwc2_udc_ep0_set_stall(ep); 1187 return 0; 1188 } 1189 1190 dwc2_udc_ep0_zlp(dev); 1191 1192 dwc2_udc_ep_clear_stall(ep); 1193 dwc2_udc_ep_activate(ep); 1194 ep->stopped = 0; 1195 1196 clear_feature_num = ep_num; 1197 clear_feature_flag = 1; 1198 } 1199 break; 1200 } 1201 1202 return 0; 1203 } 1204 1205 static int dwc2_udc_set_feature(struct usb_ep *_ep) 1206 { 1207 struct dwc2_udc *dev; 1208 struct dwc2_ep *ep; 1209 u8 ep_num; 1210 1211 ep = container_of(_ep, struct dwc2_ep, ep); 1212 ep_num = ep_index(ep); 1213 dev = ep->dev; 1214 1215 debug_cond(DEBUG_SETUP != 0, 1216 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n", 1217 __func__, ep_num); 1218 1219 if (usb_ctrl->wLength != 0) { 1220 debug_cond(DEBUG_SETUP != 0, 1221 "\tSET_FEATURE: wLength is not zero.....\n"); 1222 return 1; 1223 } 1224 1225 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) { 1226 case USB_RECIP_DEVICE: 1227 switch (usb_ctrl->wValue) { 1228 case USB_DEVICE_REMOTE_WAKEUP: 1229 debug_cond(DEBUG_SETUP != 0, 1230 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n"); 1231 break; 1232 case USB_DEVICE_B_HNP_ENABLE: 1233 debug_cond(DEBUG_SETUP != 0, 1234 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n"); 1235 break; 1236 1237 case USB_DEVICE_A_HNP_SUPPORT: 1238 /* RH port supports HNP */ 1239 debug_cond(DEBUG_SETUP != 0, 1240 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n"); 1241 break; 1242 1243 case USB_DEVICE_A_ALT_HNP_SUPPORT: 1244 /* other RH port does */ 1245 debug_cond(DEBUG_SETUP != 0, 1246 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n"); 1247 break; 1248 } 1249 1250 dwc2_udc_ep0_zlp(dev); 1251 return 0; 1252 1253 case USB_RECIP_INTERFACE: 1254 debug_cond(DEBUG_SETUP != 0, 1255 "\tSET_FEATURE: USB_RECIP_INTERFACE\n"); 1256 break; 1257 1258 case USB_RECIP_ENDPOINT: 1259 debug_cond(DEBUG_SETUP != 0, 1260 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n"); 1261 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) { 1262 if (ep_num == 0) { 1263 dwc2_udc_ep0_set_stall(ep); 1264 return 0; 1265 } 1266 ep->stopped = 1; 1267 dwc2_udc_ep_set_stall(ep); 1268 } 1269 1270 dwc2_udc_ep0_zlp(dev); 1271 return 0; 1272 } 1273 1274 return 1; 1275 } 1276 1277 /* 1278 * WAIT_FOR_SETUP (OUT_PKT_RDY) 1279 */ 1280 static void dwc2_ep0_setup(struct dwc2_udc *dev) 1281 { 1282 struct dwc2_ep *ep = &dev->ep[0]; 1283 int i; 1284 u8 ep_num; 1285 1286 /* Nuke all previous transfers */ 1287 nuke(ep, -EPROTO); 1288 1289 /* read control req from fifo (8 bytes) */ 1290 dwc2_fifo_read(ep, (u32 *)usb_ctrl, 8); 1291 1292 debug_cond(DEBUG_SETUP != 0, 1293 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x" 1294 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n", 1295 __func__, usb_ctrl->bRequestType, 1296 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT", 1297 usb_ctrl->bRequest, 1298 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex); 1299 1300 #ifdef DEBUG 1301 { 1302 int i, len = sizeof(*usb_ctrl); 1303 char *p = (char *)usb_ctrl; 1304 1305 printf("pkt = "); 1306 for (i = 0; i < len; i++) { 1307 printf("%02x", ((u8 *)p)[i]); 1308 if ((i & 7) == 7) 1309 printf(" "); 1310 } 1311 printf("\n"); 1312 } 1313 #endif 1314 1315 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST && 1316 usb_ctrl->wLength != 1) { 1317 debug_cond(DEBUG_SETUP != 0, 1318 "\t%s:GET_MAX_LUN_REQUEST:invalid", 1319 __func__); 1320 debug_cond(DEBUG_SETUP != 0, 1321 "wLength = %d, setup returned\n", 1322 usb_ctrl->wLength); 1323 1324 dwc2_udc_ep0_set_stall(ep); 1325 dev->ep0state = WAIT_FOR_SETUP; 1326 1327 return; 1328 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST && 1329 usb_ctrl->wLength != 0) { 1330 /* Bulk-Only *mass storge reset of class-specific request */ 1331 debug_cond(DEBUG_SETUP != 0, 1332 "%s:BOT Rest:invalid wLength =%d, setup returned\n", 1333 __func__, usb_ctrl->wLength); 1334 1335 dwc2_udc_ep0_set_stall(ep); 1336 dev->ep0state = WAIT_FOR_SETUP; 1337 1338 return; 1339 } 1340 1341 /* Set direction of EP0 */ 1342 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) { 1343 ep->bEndpointAddress |= USB_DIR_IN; 1344 } else { 1345 ep->bEndpointAddress &= ~USB_DIR_IN; 1346 } 1347 /* cope with automagic for some standard requests. */ 1348 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK) 1349 == USB_TYPE_STANDARD; 1350 1351 dev->req_pending = 1; 1352 1353 /* Handle some SETUP packets ourselves */ 1354 if (dev->req_std) { 1355 switch (usb_ctrl->bRequest) { 1356 case USB_REQ_SET_ADDRESS: 1357 debug_cond(DEBUG_SETUP != 0, 1358 "%s: *** USB_REQ_SET_ADDRESS (%d)\n", 1359 __func__, usb_ctrl->wValue); 1360 if (usb_ctrl->bRequestType 1361 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) 1362 break; 1363 dev->connected = 1; 1364 udc_set_address(dev, usb_ctrl->wValue); 1365 return; 1366 1367 case USB_REQ_SET_CONFIGURATION: 1368 debug_cond(DEBUG_SETUP != 0, 1369 "=====================================\n"); 1370 debug_cond(DEBUG_SETUP != 0, 1371 "%s: USB_REQ_SET_CONFIGURATION (%d)\n", 1372 __func__, usb_ctrl->wValue); 1373 1374 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE) 1375 reset_available = 1; 1376 1377 break; 1378 1379 case USB_REQ_GET_DESCRIPTOR: 1380 debug_cond(DEBUG_SETUP != 0, 1381 "%s: *** USB_REQ_GET_DESCRIPTOR\n", 1382 __func__); 1383 break; 1384 1385 case USB_REQ_SET_INTERFACE: 1386 debug_cond(DEBUG_SETUP != 0, 1387 "%s: *** USB_REQ_SET_INTERFACE (%d)\n", 1388 __func__, usb_ctrl->wValue); 1389 1390 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE) 1391 reset_available = 1; 1392 1393 break; 1394 1395 case USB_REQ_GET_CONFIGURATION: 1396 debug_cond(DEBUG_SETUP != 0, 1397 "%s: *** USB_REQ_GET_CONFIGURATION\n", 1398 __func__); 1399 break; 1400 1401 case USB_REQ_GET_STATUS: 1402 if (!dwc2_udc_get_status(dev, usb_ctrl)) 1403 return; 1404 1405 break; 1406 1407 case USB_REQ_CLEAR_FEATURE: 1408 ep_num = usb_ctrl->wIndex & 0x7f; 1409 1410 if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep)) 1411 return; 1412 1413 break; 1414 1415 case USB_REQ_SET_FEATURE: 1416 ep_num = usb_ctrl->wIndex & 0x7f; 1417 1418 if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep)) 1419 return; 1420 1421 break; 1422 1423 default: 1424 debug_cond(DEBUG_SETUP != 0, 1425 "%s: *** Default of usb_ctrl->bRequest=0x%x" 1426 "happened.\n", __func__, usb_ctrl->bRequest); 1427 break; 1428 } 1429 } 1430 1431 1432 if (likely(dev->driver)) { 1433 /* device-2-host (IN) or no data setup command, 1434 * process immediately */ 1435 debug_cond(DEBUG_SETUP != 0, 1436 "%s:usb_ctrlreq will be passed to fsg_setup()\n", 1437 __func__); 1438 1439 spin_unlock(&dev->lock); 1440 i = dev->driver->setup(&dev->gadget, usb_ctrl); 1441 spin_lock(&dev->lock); 1442 1443 if (i < 0) { 1444 /* setup processing failed, force stall */ 1445 dwc2_udc_ep0_set_stall(ep); 1446 dev->ep0state = WAIT_FOR_SETUP; 1447 1448 debug_cond(DEBUG_SETUP != 0, 1449 "\tdev->driver->setup failed (%d)," 1450 " bRequest = %d\n", 1451 i, usb_ctrl->bRequest); 1452 1453 1454 } else if (dev->req_pending) { 1455 dev->req_pending = 0; 1456 debug_cond(DEBUG_SETUP != 0, 1457 "\tdev->req_pending...\n"); 1458 } 1459 1460 debug_cond(DEBUG_SETUP != 0, 1461 "\tep0state = %s\n", state_names[dev->ep0state]); 1462 1463 } 1464 } 1465 1466 /* 1467 * handle ep0 interrupt 1468 */ 1469 static void dwc2_handle_ep0(struct dwc2_udc *dev) 1470 { 1471 if (dev->ep0state == WAIT_FOR_SETUP) { 1472 debug_cond(DEBUG_OUT_EP != 0, 1473 "%s: WAIT_FOR_SETUP\n", __func__); 1474 dwc2_ep0_setup(dev); 1475 1476 } else { 1477 debug_cond(DEBUG_OUT_EP != 0, 1478 "%s: strange state!!(state = %s)\n", 1479 __func__, state_names[dev->ep0state]); 1480 } 1481 } 1482 1483 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep) 1484 { 1485 debug_cond(DEBUG_EP0 != 0, 1486 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep)); 1487 if (ep_is_in(ep)) { 1488 dev->ep0state = DATA_STATE_XMIT; 1489 dwc2_ep0_write(dev); 1490 1491 } else { 1492 dev->ep0state = DATA_STATE_RECV; 1493 dwc2_ep0_read(dev); 1494 } 1495 } 1496