1 /* 2 * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c 3 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers 4 * 5 * Copyright (C) 2009 for Samsung Electronics 6 * 7 * BSP Support for Samsung's UDC driver 8 * available at: 9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git 10 * 11 * State machine bugfixes: 12 * Marek Szyprowski <m.szyprowski@samsung.com> 13 * 14 * Ported to u-boot: 15 * Marek Szyprowski <m.szyprowski@samsung.com> 16 * Lukasz Majewski <l.majewski@samsumg.com> 17 * 18 * SPDX-License-Identifier: GPL-2.0+ 19 */ 20 21 static u8 clear_feature_num; 22 int clear_feature_flag; 23 24 /* Bulk-Only Mass Storage Reset (class-specific request) */ 25 #define GET_MAX_LUN_REQUEST 0xFE 26 #define BOT_RESET_REQUEST 0xFF 27 28 static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev) 29 { 30 u32 ep_ctrl; 31 32 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); 33 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz); 34 35 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl); 36 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, 37 ®->in_endp[EP0_CON].diepctl); 38 39 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n", 40 __func__, readl(®->in_endp[EP0_CON].diepctl)); 41 dev->ep0state = WAIT_FOR_IN_COMPLETE; 42 } 43 44 static void dwc2_udc_pre_setup(void) 45 { 46 u32 ep_ctrl; 47 48 debug_cond(DEBUG_IN_EP, 49 "%s : Prepare Setup packets.\n", __func__); 50 51 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), 52 ®->out_endp[EP0_CON].doeptsiz); 53 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); 54 55 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl); 56 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl); 57 58 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n", 59 __func__, readl(®->in_endp[EP0_CON].diepctl)); 60 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n", 61 __func__, readl(®->out_endp[EP0_CON].doepctl)); 62 63 } 64 65 static inline void dwc2_ep0_complete_out(void) 66 { 67 u32 ep_ctrl; 68 69 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n", 70 __func__, readl(®->in_endp[EP0_CON].diepctl)); 71 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n", 72 __func__, readl(®->out_endp[EP0_CON].doepctl)); 73 74 debug_cond(DEBUG_IN_EP, 75 "%s : Prepare Complete Out packet.\n", __func__); 76 77 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), 78 ®->out_endp[EP0_CON].doeptsiz); 79 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); 80 81 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl); 82 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, 83 ®->out_endp[EP0_CON].doepctl); 84 85 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n", 86 __func__, readl(®->in_endp[EP0_CON].diepctl)); 87 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n", 88 __func__, readl(®->out_endp[EP0_CON].doepctl)); 89 90 } 91 92 93 static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req) 94 { 95 u32 *buf, ctrl; 96 u32 length, pktcnt; 97 u32 ep_num = ep_index(ep); 98 99 buf = req->req.buf + req->req.actual; 100 length = min_t(u32, req->req.length - req->req.actual, 101 ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket); 102 103 ep->len = length; 104 ep->dma_buf = buf; 105 106 if (ep_num == EP0_CON || length == 0) 107 pktcnt = 1; 108 else 109 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1; 110 111 ctrl = readl(®->out_endp[ep_num].doepctl); 112 113 invalidate_dcache_range((unsigned long) ep->dma_buf, 114 (unsigned long) ep->dma_buf + ep->len); 115 116 writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma); 117 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), 118 ®->out_endp[ep_num].doeptsiz); 119 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl); 120 121 debug_cond(DEBUG_OUT_EP != 0, 122 "%s: EP%d RX DMA start : DOEPDMA = 0x%x," 123 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n" 124 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n", 125 __func__, ep_num, 126 readl(®->out_endp[ep_num].doepdma), 127 readl(®->out_endp[ep_num].doeptsiz), 128 readl(®->out_endp[ep_num].doepctl), 129 buf, pktcnt, length); 130 return 0; 131 132 } 133 134 static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req) 135 { 136 u32 *buf, ctrl = 0; 137 u32 length, pktcnt; 138 u32 ep_num = ep_index(ep); 139 140 buf = req->req.buf + req->req.actual; 141 length = req->req.length - req->req.actual; 142 143 if (ep_num == EP0_CON) 144 length = min(length, (u32)ep_maxpacket(ep)); 145 146 ep->len = length; 147 ep->dma_buf = buf; 148 149 flush_dcache_range((unsigned long) ep->dma_buf, 150 (unsigned long) ep->dma_buf + 151 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE)); 152 153 if (length == 0) 154 pktcnt = 1; 155 else 156 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1; 157 158 /* Flush the endpoint's Tx FIFO */ 159 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl); 160 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl); 161 while (readl(®->grstctl) & TX_FIFO_FLUSH) 162 ; 163 164 writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma); 165 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length), 166 ®->in_endp[ep_num].dieptsiz); 167 168 ctrl = readl(®->in_endp[ep_num].diepctl); 169 170 /* Write the FIFO number to be used for this endpoint */ 171 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK; 172 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num); 173 174 /* Clear reserved (Next EP) bits */ 175 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT)); 176 177 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl); 178 179 debug_cond(DEBUG_IN_EP, 180 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x," 181 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n" 182 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n", 183 __func__, ep_num, 184 readl(®->in_endp[ep_num].diepdma), 185 readl(®->in_endp[ep_num].dieptsiz), 186 readl(®->in_endp[ep_num].diepctl), 187 buf, pktcnt, length); 188 189 return length; 190 } 191 192 static void complete_rx(struct dwc2_udc *dev, u8 ep_num) 193 { 194 struct dwc2_ep *ep = &dev->ep[ep_num]; 195 struct dwc2_request *req = NULL; 196 u32 ep_tsr = 0, xfer_size = 0, is_short = 0; 197 198 if (list_empty(&ep->queue)) { 199 debug_cond(DEBUG_OUT_EP != 0, 200 "%s: RX DMA done : NULL REQ on OUT EP-%d\n", 201 __func__, ep_num); 202 return; 203 204 } 205 206 req = list_entry(ep->queue.next, struct dwc2_request, queue); 207 ep_tsr = readl(®->out_endp[ep_num].doeptsiz); 208 209 if (ep_num == EP0_CON) 210 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0); 211 else 212 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP); 213 214 xfer_size = ep->len - xfer_size; 215 216 /* 217 * NOTE: 218 * 219 * Please be careful with proper buffer allocation for USB request, 220 * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only 221 * with starting address, but also its size shall be a cache line 222 * multiplication. 223 * 224 * This will prevent from corruption of data allocated immediatelly 225 * before or after the buffer. 226 * 227 * For armv7, the cache_v7.c provides proper code to emit "ERROR" 228 * message to warn users. 229 */ 230 invalidate_dcache_range((unsigned long) ep->dma_buf, 231 (unsigned long) ep->dma_buf + 232 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE)); 233 234 req->req.actual += min(xfer_size, req->req.length - req->req.actual); 235 is_short = !!(xfer_size % ep->ep.maxpacket); 236 237 debug_cond(DEBUG_OUT_EP != 0, 238 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, " 239 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n", 240 __func__, ep_num, req->req.actual, req->req.length, 241 is_short, ep_tsr, req->req.length - req->req.actual); 242 243 if (is_short || req->req.actual == req->req.length) { 244 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) { 245 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n"); 246 dwc2_udc_ep0_zlp(dev); 247 /* packet will be completed in complete_tx() */ 248 dev->ep0state = WAIT_FOR_IN_COMPLETE; 249 } else { 250 done(ep, req, 0); 251 252 if (!list_empty(&ep->queue)) { 253 req = list_entry(ep->queue.next, 254 struct dwc2_request, queue); 255 debug_cond(DEBUG_OUT_EP != 0, 256 "%s: Next Rx request start...\n", 257 __func__); 258 setdma_rx(ep, req); 259 } 260 } 261 } else 262 setdma_rx(ep, req); 263 } 264 265 static void complete_tx(struct dwc2_udc *dev, u8 ep_num) 266 { 267 struct dwc2_ep *ep = &dev->ep[ep_num]; 268 struct dwc2_request *req; 269 u32 ep_tsr = 0, xfer_size = 0, is_short = 0; 270 u32 last; 271 272 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) { 273 dev->ep0state = WAIT_FOR_OUT_COMPLETE; 274 dwc2_ep0_complete_out(); 275 return; 276 } 277 278 if (list_empty(&ep->queue)) { 279 debug_cond(DEBUG_IN_EP, 280 "%s: TX DMA done : NULL REQ on IN EP-%d\n", 281 __func__, ep_num); 282 return; 283 284 } 285 286 req = list_entry(ep->queue.next, struct dwc2_request, queue); 287 288 ep_tsr = readl(®->in_endp[ep_num].dieptsiz); 289 290 xfer_size = ep->len; 291 is_short = (xfer_size < ep->ep.maxpacket); 292 req->req.actual += min(xfer_size, req->req.length - req->req.actual); 293 294 debug_cond(DEBUG_IN_EP, 295 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, " 296 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n", 297 __func__, ep_num, req->req.actual, req->req.length, 298 is_short, ep_tsr, req->req.length - req->req.actual); 299 300 if (ep_num == 0) { 301 if (dev->ep0state == DATA_STATE_XMIT) { 302 debug_cond(DEBUG_IN_EP, 303 "%s: ep_num = %d, ep0stat ==" 304 "DATA_STATE_XMIT\n", 305 __func__, ep_num); 306 last = write_fifo_ep0(ep, req); 307 if (last) 308 dev->ep0state = WAIT_FOR_COMPLETE; 309 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) { 310 debug_cond(DEBUG_IN_EP, 311 "%s: ep_num = %d, completing request\n", 312 __func__, ep_num); 313 done(ep, req, 0); 314 dev->ep0state = WAIT_FOR_SETUP; 315 } else if (dev->ep0state == WAIT_FOR_COMPLETE) { 316 debug_cond(DEBUG_IN_EP, 317 "%s: ep_num = %d, completing request\n", 318 __func__, ep_num); 319 done(ep, req, 0); 320 dev->ep0state = WAIT_FOR_OUT_COMPLETE; 321 dwc2_ep0_complete_out(); 322 } else { 323 debug_cond(DEBUG_IN_EP, 324 "%s: ep_num = %d, invalid ep state\n", 325 __func__, ep_num); 326 } 327 return; 328 } 329 330 if (req->req.actual == req->req.length) 331 done(ep, req, 0); 332 333 if (!list_empty(&ep->queue)) { 334 req = list_entry(ep->queue.next, struct dwc2_request, queue); 335 debug_cond(DEBUG_IN_EP, 336 "%s: Next Tx request start...\n", __func__); 337 setdma_tx(ep, req); 338 } 339 } 340 341 static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num) 342 { 343 struct dwc2_ep *ep = &dev->ep[ep_num]; 344 struct dwc2_request *req; 345 346 debug_cond(DEBUG_IN_EP, 347 "%s: Check queue, ep_num = %d\n", __func__, ep_num); 348 349 if (!list_empty(&ep->queue)) { 350 req = list_entry(ep->queue.next, struct dwc2_request, queue); 351 debug_cond(DEBUG_IN_EP, 352 "%s: Next Tx request(0x%p) start...\n", 353 __func__, req); 354 355 if (ep_is_in(ep)) 356 setdma_tx(ep, req); 357 else 358 setdma_rx(ep, req); 359 } else { 360 debug_cond(DEBUG_IN_EP, 361 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num); 362 363 return; 364 } 365 366 } 367 368 static void process_ep_in_intr(struct dwc2_udc *dev) 369 { 370 u32 ep_intr, ep_intr_status; 371 u8 ep_num = 0; 372 373 ep_intr = readl(®->daint); 374 debug_cond(DEBUG_IN_EP, 375 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr); 376 377 ep_intr &= DAINT_MASK; 378 379 while (ep_intr) { 380 if (ep_intr & DAINT_IN_EP_INT(1)) { 381 ep_intr_status = readl(®->in_endp[ep_num].diepint); 382 debug_cond(DEBUG_IN_EP, 383 "\tEP%d-IN : DIEPINT = 0x%x\n", 384 ep_num, ep_intr_status); 385 386 /* Interrupt Clear */ 387 writel(ep_intr_status, ®->in_endp[ep_num].diepint); 388 389 if (ep_intr_status & TRANSFER_DONE) { 390 complete_tx(dev, ep_num); 391 392 if (ep_num == 0) { 393 if (dev->ep0state == 394 WAIT_FOR_IN_COMPLETE) 395 dev->ep0state = WAIT_FOR_SETUP; 396 397 if (dev->ep0state == WAIT_FOR_SETUP) 398 dwc2_udc_pre_setup(); 399 400 /* continue transfer after 401 set_clear_halt for DMA mode */ 402 if (clear_feature_flag == 1) { 403 dwc2_udc_check_tx_queue(dev, 404 clear_feature_num); 405 clear_feature_flag = 0; 406 } 407 } 408 } 409 } 410 ep_num++; 411 ep_intr >>= 1; 412 } 413 } 414 415 static void process_ep_out_intr(struct dwc2_udc *dev) 416 { 417 u32 ep_intr, ep_intr_status; 418 u8 ep_num = 0; 419 420 ep_intr = readl(®->daint); 421 debug_cond(DEBUG_OUT_EP != 0, 422 "*** %s: EP OUT interrupt : DAINT = 0x%x\n", 423 __func__, ep_intr); 424 425 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK; 426 427 while (ep_intr) { 428 if (ep_intr & 0x1) { 429 ep_intr_status = readl(®->out_endp[ep_num].doepint); 430 debug_cond(DEBUG_OUT_EP != 0, 431 "\tEP%d-OUT : DOEPINT = 0x%x\n", 432 ep_num, ep_intr_status); 433 434 /* Interrupt Clear */ 435 writel(ep_intr_status, ®->out_endp[ep_num].doepint); 436 437 if (ep_num == 0) { 438 if (ep_intr_status & TRANSFER_DONE) { 439 if (dev->ep0state != 440 WAIT_FOR_OUT_COMPLETE) 441 complete_rx(dev, ep_num); 442 else { 443 dev->ep0state = WAIT_FOR_SETUP; 444 dwc2_udc_pre_setup(); 445 } 446 } 447 448 if (ep_intr_status & 449 CTRL_OUT_EP_SETUP_PHASE_DONE) { 450 debug_cond(DEBUG_OUT_EP != 0, 451 "SETUP packet arrived\n"); 452 dwc2_handle_ep0(dev); 453 } 454 } else { 455 if (ep_intr_status & TRANSFER_DONE) 456 complete_rx(dev, ep_num); 457 } 458 } 459 ep_num++; 460 ep_intr >>= 1; 461 } 462 } 463 464 /* 465 * usb client interrupt handler. 466 */ 467 static int dwc2_udc_irq(int irq, void *_dev) 468 { 469 struct dwc2_udc *dev = _dev; 470 u32 intr_status; 471 u32 usb_status, gintmsk; 472 unsigned long flags = 0; 473 474 spin_lock_irqsave(&dev->lock, flags); 475 476 intr_status = readl(®->gintsts); 477 gintmsk = readl(®->gintmsk); 478 479 debug_cond(DEBUG_ISR, 480 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x," 481 "DAINT : 0x%x, DAINTMSK : 0x%x\n", 482 __func__, intr_status, state_names[dev->ep0state], gintmsk, 483 readl(®->daint), readl(®->daintmsk)); 484 485 if (!intr_status) { 486 spin_unlock_irqrestore(&dev->lock, flags); 487 return IRQ_HANDLED; 488 } 489 490 if (intr_status & INT_ENUMDONE) { 491 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n"); 492 493 writel(INT_ENUMDONE, ®->gintsts); 494 usb_status = (readl(®->dsts) & 0x6); 495 496 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) { 497 debug_cond(DEBUG_ISR, 498 "\t\tFull Speed Detection\n"); 499 set_max_pktsize(dev, USB_SPEED_FULL); 500 501 } else { 502 debug_cond(DEBUG_ISR, 503 "\t\tHigh Speed Detection : 0x%x\n", 504 usb_status); 505 set_max_pktsize(dev, USB_SPEED_HIGH); 506 } 507 } 508 509 if (intr_status & INT_EARLY_SUSPEND) { 510 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n"); 511 writel(INT_EARLY_SUSPEND, ®->gintsts); 512 } 513 514 if (intr_status & INT_SUSPEND) { 515 usb_status = readl(®->dsts); 516 debug_cond(DEBUG_ISR, 517 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status); 518 writel(INT_SUSPEND, ®->gintsts); 519 520 if (dev->gadget.speed != USB_SPEED_UNKNOWN 521 && dev->driver) { 522 if (dev->driver->suspend) 523 dev->driver->suspend(&dev->gadget); 524 525 /* HACK to let gadget detect disconnected state */ 526 if (dev->driver->disconnect) { 527 spin_unlock_irqrestore(&dev->lock, flags); 528 dev->driver->disconnect(&dev->gadget); 529 spin_lock_irqsave(&dev->lock, flags); 530 } 531 } 532 } 533 534 if (intr_status & INT_RESUME) { 535 debug_cond(DEBUG_ISR, "\tResume interrupt\n"); 536 writel(INT_RESUME, ®->gintsts); 537 538 if (dev->gadget.speed != USB_SPEED_UNKNOWN 539 && dev->driver 540 && dev->driver->resume) { 541 542 dev->driver->resume(&dev->gadget); 543 } 544 } 545 546 if (intr_status & INT_RESET) { 547 u32 temp; 548 u32 connected = dev->connected; 549 550 usb_status = readl(®->gotgctl); 551 debug_cond(DEBUG_ISR, 552 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status); 553 writel(INT_RESET, ®->gintsts); 554 555 if ((usb_status & 0xc0000) == (0x3 << 18)) { 556 if (reset_available) { 557 debug_cond(DEBUG_ISR, 558 "\t\tOTG core got reset (%d)!!\n", 559 reset_available); 560 /* Reset device address to zero */ 561 temp = readl(®->dcfg); 562 temp &= ~DCFG_DEVADDR_MASK; 563 writel(temp, ®->dcfg); 564 565 /* Soft reset the core if connected */ 566 if (connected) 567 reconfig_usbd(dev); 568 569 dev->ep0state = WAIT_FOR_SETUP; 570 reset_available = 0; 571 dwc2_udc_pre_setup(); 572 } else 573 reset_available = 1; 574 575 } else { 576 reset_available = 1; 577 debug_cond(DEBUG_ISR, 578 "\t\tRESET handling skipped\n"); 579 } 580 } 581 582 if (intr_status & INT_IN_EP) 583 process_ep_in_intr(dev); 584 585 if (intr_status & INT_OUT_EP) 586 process_ep_out_intr(dev); 587 588 spin_unlock_irqrestore(&dev->lock, flags); 589 590 return IRQ_HANDLED; 591 } 592 593 /** Queue one request 594 * Kickstart transfer if needed 595 */ 596 static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req, 597 gfp_t gfp_flags) 598 { 599 struct dwc2_request *req; 600 struct dwc2_ep *ep; 601 struct dwc2_udc *dev; 602 unsigned long flags = 0; 603 u32 ep_num, gintsts; 604 605 req = container_of(_req, struct dwc2_request, req); 606 if (unlikely(!_req || !_req->complete || !_req->buf 607 || !list_empty(&req->queue))) { 608 609 debug("%s: bad params\n", __func__); 610 return -EINVAL; 611 } 612 613 ep = container_of(_ep, struct dwc2_ep, ep); 614 615 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { 616 617 debug("%s: bad ep: %s, %d, %p\n", __func__, 618 ep->ep.name, !ep->desc, _ep); 619 return -EINVAL; 620 } 621 622 ep_num = ep_index(ep); 623 dev = ep->dev; 624 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { 625 626 debug("%s: bogus device state %p\n", __func__, dev->driver); 627 return -ESHUTDOWN; 628 } 629 630 spin_lock_irqsave(&dev->lock, flags); 631 632 _req->status = -EINPROGRESS; 633 _req->actual = 0; 634 635 /* kickstart this i/o queue? */ 636 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p" 637 "Q empty = %d, stopped = %d\n", 638 __func__, _ep->name, ep_is_in(ep) ? "in" : "out", 639 _req, _req->length, _req->buf, 640 list_empty(&ep->queue), ep->stopped); 641 642 #ifdef DEBUG 643 { 644 int i, len = _req->length; 645 646 printf("pkt = "); 647 if (len > 64) 648 len = 64; 649 for (i = 0; i < len; i++) { 650 printf("%02x", ((u8 *)_req->buf)[i]); 651 if ((i & 7) == 7) 652 printf(" "); 653 } 654 printf("\n"); 655 } 656 #endif 657 658 if (list_empty(&ep->queue) && !ep->stopped) { 659 660 if (ep_num == 0) { 661 /* EP0 */ 662 list_add_tail(&req->queue, &ep->queue); 663 dwc2_ep0_kick(dev, ep); 664 req = 0; 665 666 } else if (ep_is_in(ep)) { 667 gintsts = readl(®->gintsts); 668 debug_cond(DEBUG_IN_EP, 669 "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n", 670 __func__, gintsts); 671 672 setdma_tx(ep, req); 673 } else { 674 gintsts = readl(®->gintsts); 675 debug_cond(DEBUG_OUT_EP != 0, 676 "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n", 677 __func__, gintsts); 678 679 setdma_rx(ep, req); 680 } 681 } 682 683 /* pio or dma irq handler advances the queue. */ 684 if (likely(req != 0)) 685 list_add_tail(&req->queue, &ep->queue); 686 687 spin_unlock_irqrestore(&dev->lock, flags); 688 689 return 0; 690 } 691 692 /****************************************************************/ 693 /* End Point 0 related functions */ 694 /****************************************************************/ 695 696 /* return: 0 = still running, 1 = completed, negative = errno */ 697 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req) 698 { 699 u32 max; 700 unsigned count; 701 int is_last; 702 703 max = ep_maxpacket(ep); 704 705 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max); 706 707 count = setdma_tx(ep, req); 708 709 /* last packet is usually short (or a zlp) */ 710 if (likely(count != max)) 711 is_last = 1; 712 else { 713 if (likely(req->req.length != req->req.actual + count) 714 || req->req.zero) 715 is_last = 0; 716 else 717 is_last = 1; 718 } 719 720 debug_cond(DEBUG_EP0 != 0, 721 "%s: wrote %s %d bytes%s %d left %p\n", __func__, 722 ep->ep.name, count, 723 is_last ? "/L" : "", 724 req->req.length - req->req.actual - count, req); 725 726 /* requests complete when all IN data is in the FIFO */ 727 if (is_last) { 728 ep->dev->ep0state = WAIT_FOR_SETUP; 729 return 1; 730 } 731 732 return 0; 733 } 734 735 static int dwc2_fifo_read(struct dwc2_ep *ep, u32 *cp, int max) 736 { 737 invalidate_dcache_range((unsigned long)cp, (unsigned long)cp + 738 ROUND(max, CONFIG_SYS_CACHELINE_SIZE)); 739 740 debug_cond(DEBUG_EP0 != 0, 741 "%s: bytes=%d, ep_index=%d 0x%p\n", __func__, 742 max, ep_index(ep), cp); 743 744 return max; 745 } 746 747 /** 748 * udc_set_address - set the USB address for this device 749 * @address: 750 * 751 * Called from control endpoint function 752 * after it decodes a set address setup packet. 753 */ 754 static void udc_set_address(struct dwc2_udc *dev, unsigned char address) 755 { 756 u32 ctrl = readl(®->dcfg); 757 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg); 758 759 dwc2_udc_ep0_zlp(dev); 760 761 debug_cond(DEBUG_EP0 != 0, 762 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n", 763 __func__, address, readl(®->dcfg)); 764 765 dev->usb_address = address; 766 } 767 768 static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep) 769 { 770 struct dwc2_udc *dev; 771 u32 ep_ctrl = 0; 772 773 dev = ep->dev; 774 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl); 775 776 /* set the disable and stall bits */ 777 if (ep_ctrl & DEPCTL_EPENA) 778 ep_ctrl |= DEPCTL_EPDIS; 779 780 ep_ctrl |= DEPCTL_STALL; 781 782 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl); 783 784 debug_cond(DEBUG_EP0 != 0, 785 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n", 786 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl); 787 /* 788 * The application can only set this bit, and the core clears it, 789 * when a SETUP token is received for this endpoint 790 */ 791 dev->ep0state = WAIT_FOR_SETUP; 792 793 dwc2_udc_pre_setup(); 794 } 795 796 static void dwc2_ep0_read(struct dwc2_udc *dev) 797 { 798 struct dwc2_request *req; 799 struct dwc2_ep *ep = &dev->ep[0]; 800 801 if (!list_empty(&ep->queue)) { 802 req = list_entry(ep->queue.next, struct dwc2_request, queue); 803 804 } else { 805 debug("%s: ---> BUG\n", __func__); 806 BUG(); 807 return; 808 } 809 810 debug_cond(DEBUG_EP0 != 0, 811 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n", 812 __func__, req, req->req.length, req->req.actual); 813 814 if (req->req.length == 0) { 815 /* zlp for Set_configuration, Set_interface, 816 * or Bulk-Only mass storge reset */ 817 818 ep->len = 0; 819 dwc2_udc_ep0_zlp(dev); 820 821 debug_cond(DEBUG_EP0 != 0, 822 "%s: req.length = 0, bRequest = %d\n", 823 __func__, usb_ctrl->bRequest); 824 return; 825 } 826 827 setdma_rx(ep, req); 828 } 829 830 /* 831 * DATA_STATE_XMIT 832 */ 833 static int dwc2_ep0_write(struct dwc2_udc *dev) 834 { 835 struct dwc2_request *req; 836 struct dwc2_ep *ep = &dev->ep[0]; 837 int ret, need_zlp = 0; 838 839 if (list_empty(&ep->queue)) 840 req = 0; 841 else 842 req = list_entry(ep->queue.next, struct dwc2_request, queue); 843 844 if (!req) { 845 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__); 846 return 0; 847 } 848 849 debug_cond(DEBUG_EP0 != 0, 850 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n", 851 __func__, req, req->req.length, req->req.actual); 852 853 if (req->req.length - req->req.actual == ep0_fifo_size) { 854 /* Next write will end with the packet size, */ 855 /* so we need Zero-length-packet */ 856 need_zlp = 1; 857 } 858 859 ret = write_fifo_ep0(ep, req); 860 861 if ((ret == 1) && !need_zlp) { 862 /* Last packet */ 863 dev->ep0state = WAIT_FOR_COMPLETE; 864 debug_cond(DEBUG_EP0 != 0, 865 "%s: finished, waiting for status\n", __func__); 866 867 } else { 868 dev->ep0state = DATA_STATE_XMIT; 869 debug_cond(DEBUG_EP0 != 0, 870 "%s: not finished\n", __func__); 871 } 872 873 return 1; 874 } 875 876 static int dwc2_udc_get_status(struct dwc2_udc *dev, 877 struct usb_ctrlrequest *crq) 878 { 879 u8 ep_num = crq->wIndex & 0x7F; 880 u16 g_status = 0; 881 u32 ep_ctrl; 882 883 debug_cond(DEBUG_SETUP != 0, 884 "%s: *** USB_REQ_GET_STATUS\n", __func__); 885 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK); 886 switch (crq->bRequestType & USB_RECIP_MASK) { 887 case USB_RECIP_INTERFACE: 888 g_status = 0; 889 debug_cond(DEBUG_SETUP != 0, 890 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n", 891 g_status); 892 break; 893 894 case USB_RECIP_DEVICE: 895 g_status = 0x1; /* Self powered */ 896 debug_cond(DEBUG_SETUP != 0, 897 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n", 898 g_status); 899 break; 900 901 case USB_RECIP_ENDPOINT: 902 if (crq->wLength > 2) { 903 debug_cond(DEBUG_SETUP != 0, 904 "\tGET_STATUS:Not support EP or wLength\n"); 905 return 1; 906 } 907 908 g_status = dev->ep[ep_num].stopped; 909 debug_cond(DEBUG_SETUP != 0, 910 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n", 911 g_status); 912 913 break; 914 915 default: 916 return 1; 917 } 918 919 memcpy(usb_ctrl, &g_status, sizeof(g_status)); 920 921 flush_dcache_range((unsigned long) usb_ctrl, 922 (unsigned long) usb_ctrl + 923 ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE)); 924 925 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); 926 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2), 927 ®->in_endp[EP0_CON].dieptsiz); 928 929 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl); 930 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, 931 ®->in_endp[EP0_CON].diepctl); 932 dev->ep0state = WAIT_FOR_NULL_COMPLETE; 933 934 return 0; 935 } 936 937 static void dwc2_udc_set_nak(struct dwc2_ep *ep) 938 { 939 u8 ep_num; 940 u32 ep_ctrl = 0; 941 942 ep_num = ep_index(ep); 943 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type); 944 945 if (ep_is_in(ep)) { 946 ep_ctrl = readl(®->in_endp[ep_num].diepctl); 947 ep_ctrl |= DEPCTL_SNAK; 948 writel(ep_ctrl, ®->in_endp[ep_num].diepctl); 949 debug("%s: set NAK, DIEPCTL%d = 0x%x\n", 950 __func__, ep_num, readl(®->in_endp[ep_num].diepctl)); 951 } else { 952 ep_ctrl = readl(®->out_endp[ep_num].doepctl); 953 ep_ctrl |= DEPCTL_SNAK; 954 writel(ep_ctrl, ®->out_endp[ep_num].doepctl); 955 debug("%s: set NAK, DOEPCTL%d = 0x%x\n", 956 __func__, ep_num, readl(®->out_endp[ep_num].doepctl)); 957 } 958 959 return; 960 } 961 962 963 static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep) 964 { 965 u8 ep_num; 966 u32 ep_ctrl = 0; 967 968 ep_num = ep_index(ep); 969 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type); 970 971 if (ep_is_in(ep)) { 972 ep_ctrl = readl(®->in_endp[ep_num].diepctl); 973 974 /* set the disable and stall bits */ 975 if (ep_ctrl & DEPCTL_EPENA) 976 ep_ctrl |= DEPCTL_EPDIS; 977 978 ep_ctrl |= DEPCTL_STALL; 979 980 writel(ep_ctrl, ®->in_endp[ep_num].diepctl); 981 debug("%s: set stall, DIEPCTL%d = 0x%x\n", 982 __func__, ep_num, readl(®->in_endp[ep_num].diepctl)); 983 984 } else { 985 ep_ctrl = readl(®->out_endp[ep_num].doepctl); 986 987 /* set the stall bit */ 988 ep_ctrl |= DEPCTL_STALL; 989 990 writel(ep_ctrl, ®->out_endp[ep_num].doepctl); 991 debug("%s: set stall, DOEPCTL%d = 0x%x\n", 992 __func__, ep_num, readl(®->out_endp[ep_num].doepctl)); 993 } 994 995 return; 996 } 997 998 static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep) 999 { 1000 u8 ep_num; 1001 u32 ep_ctrl = 0; 1002 1003 ep_num = ep_index(ep); 1004 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type); 1005 1006 if (ep_is_in(ep)) { 1007 ep_ctrl = readl(®->in_endp[ep_num].diepctl); 1008 1009 /* clear stall bit */ 1010 ep_ctrl &= ~DEPCTL_STALL; 1011 1012 /* 1013 * USB Spec 9.4.5: For endpoints using data toggle, regardless 1014 * of whether an endpoint has the Halt feature set, a 1015 * ClearFeature(ENDPOINT_HALT) request always results in the 1016 * data toggle being reinitialized to DATA0. 1017 */ 1018 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT 1019 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) { 1020 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */ 1021 } 1022 1023 writel(ep_ctrl, ®->in_endp[ep_num].diepctl); 1024 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n", 1025 __func__, ep_num, readl(®->in_endp[ep_num].diepctl)); 1026 1027 } else { 1028 ep_ctrl = readl(®->out_endp[ep_num].doepctl); 1029 1030 /* clear stall bit */ 1031 ep_ctrl &= ~DEPCTL_STALL; 1032 1033 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT 1034 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) { 1035 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */ 1036 } 1037 1038 writel(ep_ctrl, ®->out_endp[ep_num].doepctl); 1039 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n", 1040 __func__, ep_num, readl(®->out_endp[ep_num].doepctl)); 1041 } 1042 1043 return; 1044 } 1045 1046 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value) 1047 { 1048 struct dwc2_ep *ep; 1049 struct dwc2_udc *dev; 1050 unsigned long flags = 0; 1051 u8 ep_num; 1052 1053 ep = container_of(_ep, struct dwc2_ep, ep); 1054 ep_num = ep_index(ep); 1055 1056 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON || 1057 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) { 1058 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name); 1059 return -EINVAL; 1060 } 1061 1062 /* Attempt to halt IN ep will fail if any transfer requests 1063 * are still queue */ 1064 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) { 1065 debug("%s: %s queue not empty, req = %p\n", 1066 __func__, ep->ep.name, 1067 list_entry(ep->queue.next, struct dwc2_request, queue)); 1068 1069 return -EAGAIN; 1070 } 1071 1072 dev = ep->dev; 1073 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value); 1074 1075 spin_lock_irqsave(&dev->lock, flags); 1076 1077 if (value == 0) { 1078 ep->stopped = 0; 1079 dwc2_udc_ep_clear_stall(ep); 1080 } else { 1081 if (ep_num == 0) 1082 dev->ep0state = WAIT_FOR_SETUP; 1083 1084 ep->stopped = 1; 1085 dwc2_udc_ep_set_stall(ep); 1086 } 1087 1088 spin_unlock_irqrestore(&dev->lock, flags); 1089 1090 return 0; 1091 } 1092 1093 static void dwc2_udc_ep_activate(struct dwc2_ep *ep) 1094 { 1095 u8 ep_num; 1096 u32 ep_ctrl = 0, daintmsk = 0; 1097 1098 ep_num = ep_index(ep); 1099 1100 /* Read DEPCTLn register */ 1101 if (ep_is_in(ep)) { 1102 ep_ctrl = readl(®->in_endp[ep_num].diepctl); 1103 daintmsk = 1 << ep_num; 1104 } else { 1105 ep_ctrl = readl(®->out_endp[ep_num].doepctl); 1106 daintmsk = (1 << ep_num) << DAINT_OUT_BIT; 1107 } 1108 1109 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n", 1110 __func__, ep_num, ep_ctrl, ep_is_in(ep)); 1111 1112 /* If the EP is already active don't change the EP Control 1113 * register. */ 1114 if (!(ep_ctrl & DEPCTL_USBACTEP)) { 1115 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) | 1116 (ep->bmAttributes << DEPCTL_TYPE_BIT); 1117 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) | 1118 (ep->ep.maxpacket << DEPCTL_MPS_BIT); 1119 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK); 1120 1121 if (ep_is_in(ep)) { 1122 writel(ep_ctrl, ®->in_endp[ep_num].diepctl); 1123 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n", 1124 __func__, ep_num, ep_num, 1125 readl(®->in_endp[ep_num].diepctl)); 1126 } else { 1127 writel(ep_ctrl, ®->out_endp[ep_num].doepctl); 1128 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n", 1129 __func__, ep_num, ep_num, 1130 readl(®->out_endp[ep_num].doepctl)); 1131 } 1132 } 1133 1134 /* Unmask EP Interrtupt */ 1135 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk); 1136 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk)); 1137 1138 } 1139 1140 static int dwc2_udc_clear_feature(struct usb_ep *_ep) 1141 { 1142 struct dwc2_udc *dev; 1143 struct dwc2_ep *ep; 1144 u8 ep_num; 1145 1146 ep = container_of(_ep, struct dwc2_ep, ep); 1147 ep_num = ep_index(ep); 1148 1149 dev = ep->dev; 1150 debug_cond(DEBUG_SETUP != 0, 1151 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n", 1152 __func__, ep_num, ep_is_in(ep), clear_feature_flag); 1153 1154 if (usb_ctrl->wLength != 0) { 1155 debug_cond(DEBUG_SETUP != 0, 1156 "\tCLEAR_FEATURE: wLength is not zero.....\n"); 1157 return 1; 1158 } 1159 1160 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) { 1161 case USB_RECIP_DEVICE: 1162 switch (usb_ctrl->wValue) { 1163 case USB_DEVICE_REMOTE_WAKEUP: 1164 debug_cond(DEBUG_SETUP != 0, 1165 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n"); 1166 break; 1167 1168 case USB_DEVICE_TEST_MODE: 1169 debug_cond(DEBUG_SETUP != 0, 1170 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n"); 1171 /** @todo Add CLEAR_FEATURE for TEST modes. */ 1172 break; 1173 } 1174 1175 dwc2_udc_ep0_zlp(dev); 1176 break; 1177 1178 case USB_RECIP_ENDPOINT: 1179 debug_cond(DEBUG_SETUP != 0, 1180 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n", 1181 usb_ctrl->wValue); 1182 1183 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) { 1184 if (ep_num == 0) { 1185 dwc2_udc_ep0_set_stall(ep); 1186 return 0; 1187 } 1188 1189 dwc2_udc_ep0_zlp(dev); 1190 1191 dwc2_udc_ep_clear_stall(ep); 1192 dwc2_udc_ep_activate(ep); 1193 ep->stopped = 0; 1194 1195 clear_feature_num = ep_num; 1196 clear_feature_flag = 1; 1197 } 1198 break; 1199 } 1200 1201 return 0; 1202 } 1203 1204 static int dwc2_udc_set_feature(struct usb_ep *_ep) 1205 { 1206 struct dwc2_udc *dev; 1207 struct dwc2_ep *ep; 1208 u8 ep_num; 1209 1210 ep = container_of(_ep, struct dwc2_ep, ep); 1211 ep_num = ep_index(ep); 1212 dev = ep->dev; 1213 1214 debug_cond(DEBUG_SETUP != 0, 1215 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n", 1216 __func__, ep_num); 1217 1218 if (usb_ctrl->wLength != 0) { 1219 debug_cond(DEBUG_SETUP != 0, 1220 "\tSET_FEATURE: wLength is not zero.....\n"); 1221 return 1; 1222 } 1223 1224 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) { 1225 case USB_RECIP_DEVICE: 1226 switch (usb_ctrl->wValue) { 1227 case USB_DEVICE_REMOTE_WAKEUP: 1228 debug_cond(DEBUG_SETUP != 0, 1229 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n"); 1230 break; 1231 case USB_DEVICE_B_HNP_ENABLE: 1232 debug_cond(DEBUG_SETUP != 0, 1233 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n"); 1234 break; 1235 1236 case USB_DEVICE_A_HNP_SUPPORT: 1237 /* RH port supports HNP */ 1238 debug_cond(DEBUG_SETUP != 0, 1239 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n"); 1240 break; 1241 1242 case USB_DEVICE_A_ALT_HNP_SUPPORT: 1243 /* other RH port does */ 1244 debug_cond(DEBUG_SETUP != 0, 1245 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n"); 1246 break; 1247 } 1248 1249 dwc2_udc_ep0_zlp(dev); 1250 return 0; 1251 1252 case USB_RECIP_INTERFACE: 1253 debug_cond(DEBUG_SETUP != 0, 1254 "\tSET_FEATURE: USB_RECIP_INTERFACE\n"); 1255 break; 1256 1257 case USB_RECIP_ENDPOINT: 1258 debug_cond(DEBUG_SETUP != 0, 1259 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n"); 1260 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) { 1261 if (ep_num == 0) { 1262 dwc2_udc_ep0_set_stall(ep); 1263 return 0; 1264 } 1265 ep->stopped = 1; 1266 dwc2_udc_ep_set_stall(ep); 1267 } 1268 1269 dwc2_udc_ep0_zlp(dev); 1270 return 0; 1271 } 1272 1273 return 1; 1274 } 1275 1276 /* 1277 * WAIT_FOR_SETUP (OUT_PKT_RDY) 1278 */ 1279 static void dwc2_ep0_setup(struct dwc2_udc *dev) 1280 { 1281 struct dwc2_ep *ep = &dev->ep[0]; 1282 int i; 1283 u8 ep_num; 1284 1285 /* Nuke all previous transfers */ 1286 nuke(ep, -EPROTO); 1287 1288 /* read control req from fifo (8 bytes) */ 1289 dwc2_fifo_read(ep, (u32 *)usb_ctrl, 8); 1290 1291 debug_cond(DEBUG_SETUP != 0, 1292 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x" 1293 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n", 1294 __func__, usb_ctrl->bRequestType, 1295 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT", 1296 usb_ctrl->bRequest, 1297 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex); 1298 1299 #ifdef DEBUG 1300 { 1301 int i, len = sizeof(*usb_ctrl); 1302 char *p = (char *)usb_ctrl; 1303 1304 printf("pkt = "); 1305 for (i = 0; i < len; i++) { 1306 printf("%02x", ((u8 *)p)[i]); 1307 if ((i & 7) == 7) 1308 printf(" "); 1309 } 1310 printf("\n"); 1311 } 1312 #endif 1313 1314 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST && 1315 usb_ctrl->wLength != 1) { 1316 debug_cond(DEBUG_SETUP != 0, 1317 "\t%s:GET_MAX_LUN_REQUEST:invalid", 1318 __func__); 1319 debug_cond(DEBUG_SETUP != 0, 1320 "wLength = %d, setup returned\n", 1321 usb_ctrl->wLength); 1322 1323 dwc2_udc_ep0_set_stall(ep); 1324 dev->ep0state = WAIT_FOR_SETUP; 1325 1326 return; 1327 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST && 1328 usb_ctrl->wLength != 0) { 1329 /* Bulk-Only *mass storge reset of class-specific request */ 1330 debug_cond(DEBUG_SETUP != 0, 1331 "%s:BOT Rest:invalid wLength =%d, setup returned\n", 1332 __func__, usb_ctrl->wLength); 1333 1334 dwc2_udc_ep0_set_stall(ep); 1335 dev->ep0state = WAIT_FOR_SETUP; 1336 1337 return; 1338 } 1339 1340 /* Set direction of EP0 */ 1341 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) { 1342 ep->bEndpointAddress |= USB_DIR_IN; 1343 } else { 1344 ep->bEndpointAddress &= ~USB_DIR_IN; 1345 } 1346 /* cope with automagic for some standard requests. */ 1347 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK) 1348 == USB_TYPE_STANDARD; 1349 1350 dev->req_pending = 1; 1351 1352 /* Handle some SETUP packets ourselves */ 1353 if (dev->req_std) { 1354 switch (usb_ctrl->bRequest) { 1355 case USB_REQ_SET_ADDRESS: 1356 debug_cond(DEBUG_SETUP != 0, 1357 "%s: *** USB_REQ_SET_ADDRESS (%d)\n", 1358 __func__, usb_ctrl->wValue); 1359 if (usb_ctrl->bRequestType 1360 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) 1361 break; 1362 dev->connected = 1; 1363 udc_set_address(dev, usb_ctrl->wValue); 1364 return; 1365 1366 case USB_REQ_SET_CONFIGURATION: 1367 debug_cond(DEBUG_SETUP != 0, 1368 "=====================================\n"); 1369 debug_cond(DEBUG_SETUP != 0, 1370 "%s: USB_REQ_SET_CONFIGURATION (%d)\n", 1371 __func__, usb_ctrl->wValue); 1372 1373 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE) 1374 reset_available = 1; 1375 1376 break; 1377 1378 case USB_REQ_GET_DESCRIPTOR: 1379 debug_cond(DEBUG_SETUP != 0, 1380 "%s: *** USB_REQ_GET_DESCRIPTOR\n", 1381 __func__); 1382 break; 1383 1384 case USB_REQ_SET_INTERFACE: 1385 debug_cond(DEBUG_SETUP != 0, 1386 "%s: *** USB_REQ_SET_INTERFACE (%d)\n", 1387 __func__, usb_ctrl->wValue); 1388 1389 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE) 1390 reset_available = 1; 1391 1392 break; 1393 1394 case USB_REQ_GET_CONFIGURATION: 1395 debug_cond(DEBUG_SETUP != 0, 1396 "%s: *** USB_REQ_GET_CONFIGURATION\n", 1397 __func__); 1398 break; 1399 1400 case USB_REQ_GET_STATUS: 1401 if (!dwc2_udc_get_status(dev, usb_ctrl)) 1402 return; 1403 1404 break; 1405 1406 case USB_REQ_CLEAR_FEATURE: 1407 ep_num = usb_ctrl->wIndex & 0x7f; 1408 1409 if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep)) 1410 return; 1411 1412 break; 1413 1414 case USB_REQ_SET_FEATURE: 1415 ep_num = usb_ctrl->wIndex & 0x7f; 1416 1417 if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep)) 1418 return; 1419 1420 break; 1421 1422 default: 1423 debug_cond(DEBUG_SETUP != 0, 1424 "%s: *** Default of usb_ctrl->bRequest=0x%x" 1425 "happened.\n", __func__, usb_ctrl->bRequest); 1426 break; 1427 } 1428 } 1429 1430 1431 if (likely(dev->driver)) { 1432 /* device-2-host (IN) or no data setup command, 1433 * process immediately */ 1434 debug_cond(DEBUG_SETUP != 0, 1435 "%s:usb_ctrlreq will be passed to fsg_setup()\n", 1436 __func__); 1437 1438 spin_unlock(&dev->lock); 1439 i = dev->driver->setup(&dev->gadget, usb_ctrl); 1440 spin_lock(&dev->lock); 1441 1442 if (i < 0) { 1443 /* setup processing failed, force stall */ 1444 dwc2_udc_ep0_set_stall(ep); 1445 dev->ep0state = WAIT_FOR_SETUP; 1446 1447 debug_cond(DEBUG_SETUP != 0, 1448 "\tdev->driver->setup failed (%d)," 1449 " bRequest = %d\n", 1450 i, usb_ctrl->bRequest); 1451 1452 1453 } else if (dev->req_pending) { 1454 dev->req_pending = 0; 1455 debug_cond(DEBUG_SETUP != 0, 1456 "\tdev->req_pending...\n"); 1457 } 1458 1459 debug_cond(DEBUG_SETUP != 0, 1460 "\tep0state = %s\n", state_names[dev->ep0state]); 1461 1462 } 1463 } 1464 1465 /* 1466 * handle ep0 interrupt 1467 */ 1468 static void dwc2_handle_ep0(struct dwc2_udc *dev) 1469 { 1470 if (dev->ep0state == WAIT_FOR_SETUP) { 1471 debug_cond(DEBUG_OUT_EP != 0, 1472 "%s: WAIT_FOR_SETUP\n", __func__); 1473 dwc2_ep0_setup(dev); 1474 1475 } else { 1476 debug_cond(DEBUG_OUT_EP != 0, 1477 "%s: strange state!!(state = %s)\n", 1478 __func__, state_names[dev->ep0state]); 1479 } 1480 } 1481 1482 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep) 1483 { 1484 debug_cond(DEBUG_EP0 != 0, 1485 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep)); 1486 if (ep_is_in(ep)) { 1487 dev->ep0state = DATA_STATE_XMIT; 1488 dwc2_ep0_write(dev); 1489 1490 } else { 1491 dev->ep0state = DATA_STATE_RECV; 1492 dwc2_ep0_read(dev); 1493 } 1494 } 1495