1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported 10 * to uboot. 11 * 12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <common.h> 18 #include <malloc.h> 19 #include <fdtdec.h> 20 #include <dwc3-uboot.h> 21 #include <asm/dma-mapping.h> 22 #include <linux/ioport.h> 23 #include <dm.h> 24 #include <generic-phy.h> 25 #include <linux/usb/ch9.h> 26 #include <linux/usb/gadget.h> 27 28 #include "core.h" 29 #include "gadget.h" 30 #include "io.h" 31 32 #include "linux-compat.h" 33 #include "rockusb.h" 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 static LIST_HEAD(dwc3_list); 38 /* -------------------------------------------------------------------------- */ 39 40 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 41 { 42 u32 reg; 43 44 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 45 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 46 reg |= DWC3_GCTL_PRTCAPDIR(mode); 47 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 48 } 49 50 /** 51 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 52 * @dwc: pointer to our context structure 53 */ 54 static int dwc3_core_soft_reset(struct dwc3 *dwc) 55 { 56 u32 reg; 57 58 /* Before Resetting PHY, put Core in Reset */ 59 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 60 reg |= DWC3_GCTL_CORESOFTRESET; 61 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 62 63 /* Assert USB3 PHY reset */ 64 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 65 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 66 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 67 68 /* Assert USB2 PHY reset */ 69 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 70 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 71 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 72 73 mdelay(100); 74 75 /* Clear USB3 PHY reset */ 76 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 77 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 78 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 79 80 /* Clear USB2 PHY reset */ 81 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 82 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 83 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 84 85 mdelay(100); 86 87 /* After PHYs are stable we can take Core out of reset state */ 88 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 89 reg &= ~DWC3_GCTL_CORESOFTRESET; 90 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 91 92 return 0; 93 } 94 95 /** 96 * dwc3_free_one_event_buffer - Frees one event buffer 97 * @dwc: Pointer to our controller context structure 98 * @evt: Pointer to event buffer to be freed 99 */ 100 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 101 struct dwc3_event_buffer *evt) 102 { 103 dma_free_coherent(evt->buf); 104 } 105 106 /** 107 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 108 * @dwc: Pointer to our controller context structure 109 * @length: size of the event buffer 110 * 111 * Returns a pointer to the allocated event buffer structure on success 112 * otherwise ERR_PTR(errno). 113 */ 114 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 115 unsigned length) 116 { 117 struct dwc3_event_buffer *evt; 118 119 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt), 120 GFP_KERNEL); 121 if (!evt) 122 return ERR_PTR(-ENOMEM); 123 124 evt->dwc = dwc; 125 evt->length = length; 126 evt->buf = dma_alloc_coherent(length, 127 (unsigned long *)&evt->dma); 128 if (!evt->buf) 129 return ERR_PTR(-ENOMEM); 130 131 dwc3_flush_cache((uintptr_t)evt->buf, evt->length); 132 133 return evt; 134 } 135 136 /** 137 * dwc3_free_event_buffers - frees all allocated event buffers 138 * @dwc: Pointer to our controller context structure 139 */ 140 static void dwc3_free_event_buffers(struct dwc3 *dwc) 141 { 142 struct dwc3_event_buffer *evt; 143 int i; 144 145 for (i = 0; i < dwc->num_event_buffers; i++) { 146 evt = dwc->ev_buffs[i]; 147 if (evt) 148 dwc3_free_one_event_buffer(dwc, evt); 149 } 150 } 151 152 /** 153 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 154 * @dwc: pointer to our controller context structure 155 * @length: size of event buffer 156 * 157 * Returns 0 on success otherwise negative errno. In the error case, dwc 158 * may contain some buffers allocated but not all which were requested. 159 */ 160 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 161 { 162 int num; 163 int i; 164 165 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 166 dwc->num_event_buffers = num; 167 168 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE, 169 sizeof(*dwc->ev_buffs) * num); 170 if (!dwc->ev_buffs) 171 return -ENOMEM; 172 173 for (i = 0; i < num; i++) { 174 struct dwc3_event_buffer *evt; 175 176 evt = dwc3_alloc_one_event_buffer(dwc, length); 177 if (IS_ERR(evt)) { 178 dev_err(dwc->dev, "can't allocate event buffer\n"); 179 return PTR_ERR(evt); 180 } 181 dwc->ev_buffs[i] = evt; 182 } 183 184 return 0; 185 } 186 187 /** 188 * dwc3_event_buffers_setup - setup our allocated event buffers 189 * @dwc: pointer to our controller context structure 190 * 191 * Returns 0 on success otherwise negative errno. 192 */ 193 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 194 { 195 struct dwc3_event_buffer *evt; 196 int n; 197 198 for (n = 0; n < dwc->num_event_buffers; n++) { 199 evt = dwc->ev_buffs[n]; 200 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 201 evt->buf, (unsigned long long) evt->dma, 202 evt->length); 203 204 evt->lpos = 0; 205 206 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 207 lower_32_bits(evt->dma)); 208 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 209 upper_32_bits(evt->dma)); 210 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 211 DWC3_GEVNTSIZ_SIZE(evt->length)); 212 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 213 } 214 215 return 0; 216 } 217 218 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 219 { 220 struct dwc3_event_buffer *evt; 221 int n; 222 223 for (n = 0; n < dwc->num_event_buffers; n++) { 224 evt = dwc->ev_buffs[n]; 225 226 evt->lpos = 0; 227 228 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 229 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 230 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 231 | DWC3_GEVNTSIZ_SIZE(0)); 232 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 233 } 234 } 235 236 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 237 { 238 if (!dwc->has_hibernation) 239 return 0; 240 241 if (!dwc->nr_scratch) 242 return 0; 243 244 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 245 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 246 if (!dwc->scratchbuf) 247 return -ENOMEM; 248 249 return 0; 250 } 251 252 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 253 { 254 dma_addr_t scratch_addr; 255 u32 param; 256 int ret; 257 258 if (!dwc->has_hibernation) 259 return 0; 260 261 if (!dwc->nr_scratch) 262 return 0; 263 264 scratch_addr = dma_map_single(dwc->scratchbuf, 265 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 266 DMA_BIDIRECTIONAL); 267 if (dma_mapping_error(dwc->dev, scratch_addr)) { 268 dev_err(dwc->dev, "failed to map scratch buffer\n"); 269 ret = -EFAULT; 270 goto err0; 271 } 272 273 dwc->scratch_addr = scratch_addr; 274 275 param = lower_32_bits(scratch_addr); 276 277 ret = dwc3_send_gadget_generic_command(dwc, 278 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 279 if (ret < 0) 280 goto err1; 281 282 param = upper_32_bits(scratch_addr); 283 284 ret = dwc3_send_gadget_generic_command(dwc, 285 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 286 if (ret < 0) 287 goto err1; 288 289 return 0; 290 291 err1: 292 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 293 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 294 295 err0: 296 return ret; 297 } 298 299 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 300 { 301 if (!dwc->has_hibernation) 302 return; 303 304 if (!dwc->nr_scratch) 305 return; 306 307 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 308 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 309 kfree(dwc->scratchbuf); 310 } 311 312 static void dwc3_core_num_eps(struct dwc3 *dwc) 313 { 314 struct dwc3_hwparams *parms = &dwc->hwparams; 315 316 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 317 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 318 319 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", 320 dwc->num_in_eps, dwc->num_out_eps); 321 } 322 323 static void dwc3_cache_hwparams(struct dwc3 *dwc) 324 { 325 struct dwc3_hwparams *parms = &dwc->hwparams; 326 327 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 328 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 329 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 330 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 331 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 332 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 333 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 334 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 335 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 336 } 337 338 static void dwc3_hsphy_mode_setup(struct dwc3 *dwc) 339 { 340 enum usb_phy_interface hsphy_mode = dwc->hsphy_mode; 341 u32 reg; 342 343 /* Set dwc3 usb2 phy config */ 344 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 345 346 switch (hsphy_mode) { 347 case USBPHY_INTERFACE_MODE_UTMI: 348 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 349 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 350 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 351 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 352 break; 353 case USBPHY_INTERFACE_MODE_UTMIW: 354 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 355 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 356 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 357 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 358 break; 359 default: 360 break; 361 } 362 363 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 364 } 365 366 /** 367 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 368 * @dwc: Pointer to our controller context structure 369 */ 370 static void dwc3_phy_setup(struct dwc3 *dwc) 371 { 372 u32 reg; 373 374 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 375 376 /* 377 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 378 * to '0' during coreConsultant configuration. So default value 379 * will be '0' when the core is reset. Application needs to set it 380 * to '1' after the core initialization is completed. 381 */ 382 if (dwc->revision > DWC3_REVISION_194A) 383 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 384 385 if (dwc->u2ss_inp3_quirk) 386 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 387 388 if (dwc->req_p1p2p3_quirk) 389 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 390 391 if (dwc->del_p1p2p3_quirk) 392 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 393 394 if (dwc->del_phy_power_chg_quirk) 395 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 396 397 if (dwc->lfps_filter_quirk) 398 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 399 400 if (dwc->rx_detect_poll_quirk) 401 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 402 403 if (dwc->tx_de_emphasis_quirk) 404 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 405 406 /* 407 * For some Rokchip SoCs like RK3588, if the USB3 PHY is suspended 408 * in U-Boot would cause the PHY initialize abortively in Linux Kernel, 409 * so disable the DWC3_GUSB3PIPECTL_SUSPHY feature here to fix it. 410 */ 411 if (dwc->dis_u3_susphy_quirk || CONFIG_IS_ENABLED(ARCH_ROCKCHIP)) 412 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 413 414 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 415 416 dwc3_hsphy_mode_setup(dwc); 417 418 mdelay(100); 419 420 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 421 422 /* 423 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 424 * '0' during coreConsultant configuration. So default value will 425 * be '0' when the core is reset. Application needs to set it to 426 * '1' after the core initialization is completed. 427 */ 428 if (dwc->revision > DWC3_REVISION_194A) 429 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 430 431 if (dwc->dis_u2_susphy_quirk || CONFIG_IS_ENABLED(ARCH_ROCKCHIP)) 432 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 433 434 if (dwc->dis_enblslpm_quirk) 435 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 436 437 if (dwc->dis_u2_freeclk_exists_quirk) 438 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 439 440 if (dwc->usb2_phyif_utmi_width == 16) { 441 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 442 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 443 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 444 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT); 445 } 446 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 447 448 mdelay(100); 449 } 450 451 /** 452 * dwc3_core_init - Low-level initialization of DWC3 Core 453 * @dwc: Pointer to our controller context structure 454 * 455 * Returns 0 on success otherwise negative errno. 456 */ 457 static int dwc3_core_init(struct dwc3 *dwc) 458 { 459 unsigned long timeout; 460 u32 hwparams4 = dwc->hwparams.hwparams4; 461 u32 reg; 462 int ret; 463 464 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 465 /* This should read as U3 followed by revision number */ 466 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 467 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 468 ret = -ENODEV; 469 goto err0; 470 } 471 dwc->revision = reg; 472 473 /* Handle USB2.0-only core configuration */ 474 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 475 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 476 if (dwc->maximum_speed == USB_SPEED_SUPER) 477 dwc->maximum_speed = USB_SPEED_HIGH; 478 } 479 480 /* issue device SoftReset too */ 481 timeout = 5000; 482 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 483 while (timeout--) { 484 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 485 if (!(reg & DWC3_DCTL_CSFTRST)) 486 break; 487 }; 488 489 if (!timeout) { 490 dev_err(dwc->dev, "Reset Timed Out\n"); 491 ret = -ETIMEDOUT; 492 goto err0; 493 } 494 495 ret = dwc3_core_soft_reset(dwc); 496 if (ret) 497 goto err0; 498 499 if (dwc->revision >= DWC3_REVISION_250A) { 500 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 501 502 if (dwc->maximum_speed == USB_SPEED_HIGH || 503 dwc->maximum_speed == USB_SPEED_FULL) 504 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 505 506 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 507 } 508 509 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 510 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 511 512 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 513 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 514 /** 515 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 516 * issue which would cause xHCI compliance tests to fail. 517 * 518 * Because of that we cannot enable clock gating on such 519 * configurations. 520 * 521 * Refers to: 522 * 523 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 524 * SOF/ITP Mode Used 525 */ 526 if ((dwc->dr_mode == USB_DR_MODE_HOST || 527 dwc->dr_mode == USB_DR_MODE_OTG) && 528 (dwc->revision >= DWC3_REVISION_210A && 529 dwc->revision <= DWC3_REVISION_250A)) 530 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 531 else 532 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 533 break; 534 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 535 /* enable hibernation here */ 536 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 537 538 /* 539 * REVISIT Enabling this bit so that host-mode hibernation 540 * will work. Device-mode hibernation is not yet implemented. 541 */ 542 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 543 break; 544 default: 545 dev_dbg(dwc->dev, "No power optimization available\n"); 546 } 547 548 /* check if current dwc3 is on simulation board */ 549 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 550 dev_dbg(dwc->dev, "it is on FPGA board\n"); 551 dwc->is_fpga = true; 552 } 553 554 if(dwc->disable_scramble_quirk && !dwc->is_fpga) 555 WARN(true, 556 "disable_scramble cannot be used on non-FPGA builds\n"); 557 558 if (dwc->disable_scramble_quirk && dwc->is_fpga) 559 reg |= DWC3_GCTL_DISSCRAMBLE; 560 else 561 reg &= ~DWC3_GCTL_DISSCRAMBLE; 562 563 if (dwc->u2exit_lfps_quirk) 564 reg |= DWC3_GCTL_U2EXIT_LFPS; 565 566 /* 567 * WORKAROUND: DWC3 revisions <1.90a have a bug 568 * where the device can fail to connect at SuperSpeed 569 * and falls back to high-speed mode which causes 570 * the device to enter a Connect/Disconnect loop 571 */ 572 if (dwc->revision < DWC3_REVISION_190A) 573 reg |= DWC3_GCTL_U2RSTECN; 574 575 dwc3_core_num_eps(dwc); 576 577 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 578 579 dwc3_phy_setup(dwc); 580 581 ret = dwc3_alloc_scratch_buffers(dwc); 582 if (ret) 583 goto err0; 584 585 ret = dwc3_setup_scratch_buffers(dwc); 586 if (ret) 587 goto err1; 588 589 return 0; 590 591 err1: 592 dwc3_free_scratch_buffers(dwc); 593 594 err0: 595 return ret; 596 } 597 598 static void dwc3_core_exit(struct dwc3 *dwc) 599 { 600 dwc3_free_scratch_buffers(dwc); 601 } 602 603 static int dwc3_core_init_mode(struct dwc3 *dwc) 604 { 605 int ret; 606 607 switch (dwc->dr_mode) { 608 case USB_DR_MODE_PERIPHERAL: 609 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 610 ret = dwc3_gadget_init(dwc); 611 if (ret) { 612 dev_err(dev, "failed to initialize gadget\n"); 613 return ret; 614 } 615 break; 616 case USB_DR_MODE_HOST: 617 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 618 ret = dwc3_host_init(dwc); 619 if (ret) { 620 dev_err(dev, "failed to initialize host\n"); 621 return ret; 622 } 623 break; 624 case USB_DR_MODE_OTG: 625 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 626 ret = dwc3_host_init(dwc); 627 if (ret) { 628 dev_err(dev, "failed to initialize host\n"); 629 return ret; 630 } 631 632 ret = dwc3_gadget_init(dwc); 633 if (ret) { 634 dev_err(dev, "failed to initialize gadget\n"); 635 return ret; 636 } 637 break; 638 default: 639 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 640 return -EINVAL; 641 } 642 643 return 0; 644 } 645 646 static void dwc3_gadget_run(struct dwc3 *dwc) 647 { 648 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP); 649 mdelay(100); 650 } 651 652 static void dwc3_core_exit_mode(struct dwc3 *dwc) 653 { 654 switch (dwc->dr_mode) { 655 case USB_DR_MODE_PERIPHERAL: 656 dwc3_gadget_exit(dwc); 657 break; 658 case USB_DR_MODE_HOST: 659 dwc3_host_exit(dwc); 660 break; 661 case USB_DR_MODE_OTG: 662 dwc3_host_exit(dwc); 663 dwc3_gadget_exit(dwc); 664 break; 665 default: 666 /* do nothing */ 667 break; 668 } 669 670 /* 671 * switch back to peripheral mode 672 * This enables the phy to enter idle and then, if enabled, suspend. 673 */ 674 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 675 dwc3_gadget_run(dwc); 676 } 677 678 #define DWC3_ALIGN_MASK (16 - 1) 679 680 /** 681 * dwc3_uboot_init - dwc3 core uboot initialization code 682 * @dwc3_dev: struct dwc3_device containing initialization data 683 * 684 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux 685 * kernel driver). Pointer to dwc3_device should be passed containing 686 * base address and other initialization data. Returns '0' on success and 687 * a negative value on failure. 688 * 689 * Generally called from board_usb_init() implemented in board file. 690 */ 691 int dwc3_uboot_init(struct dwc3_device *dwc3_dev) 692 { 693 struct dwc3 *dwc; 694 struct device *dev = NULL; 695 u8 lpm_nyet_threshold; 696 u8 tx_de_emphasis; 697 u8 hird_threshold; 698 699 int ret; 700 701 void *mem; 702 const void *blob = gd->fdt_blob; 703 int node; 704 705 mem = devm_kzalloc((struct udevice *)dev, 706 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 707 if (!mem) 708 return -ENOMEM; 709 710 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 711 dwc->mem = mem; 712 713 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base + 714 DWC3_GLOBALS_REGS_START); 715 716 /* default to highest possible threshold */ 717 lpm_nyet_threshold = 0xff; 718 719 /* default to -3.5dB de-emphasis */ 720 tx_de_emphasis = 1; 721 722 /* 723 * default to assert utmi_sleep_n and use maximum allowed HIRD 724 * threshold value of 0b1100 725 */ 726 hird_threshold = 12; 727 728 dwc->check_linksts = true; 729 dwc->ts = get_timer(0); 730 dwc->maximum_speed = dwc3_dev->maximum_speed; 731 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum; 732 if (dwc3_dev->lpm_nyet_threshold) 733 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold; 734 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend; 735 if (dwc3_dev->hird_threshold) 736 hird_threshold = dwc3_dev->hird_threshold; 737 738 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize; 739 dwc->dr_mode = dwc3_dev->dr_mode; 740 741 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk; 742 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk; 743 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk; 744 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk; 745 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk; 746 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk; 747 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk; 748 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk; 749 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk; 750 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; 751 dwc->dis_u1u2_quirk = dwc3_dev->dis_u2_susphy_quirk; 752 753 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk; 754 if (dwc3_dev->tx_de_emphasis) 755 tx_de_emphasis = dwc3_dev->tx_de_emphasis; 756 757 /* default to superspeed if no maximum_speed passed */ 758 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 759 dwc->maximum_speed = USB_SPEED_SUPER; 760 else if (dwc->maximum_speed == USB_SPEED_SUPER && 761 rkusb_force_usb2_enabled()) 762 dwc->maximum_speed = USB_SPEED_HIGH; 763 764 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 765 dwc->tx_de_emphasis = tx_de_emphasis; 766 767 dwc->hird_threshold = hird_threshold 768 | (dwc->is_utmi_l1_suspend << 4); 769 770 dwc->hsphy_mode = dwc3_dev->hsphy_mode; 771 772 dwc->index = dwc3_dev->index; 773 774 if (dwc3_dev->usb2_phyif_utmi_width) 775 dwc->usb2_phyif_utmi_width = dwc3_dev->usb2_phyif_utmi_width; 776 777 node = fdt_node_offset_by_compatible(blob, -1, 778 "rockchip,rk3399-xhci"); 779 if (node < 0) 780 debug("%s dwc3 node not found\n", __func__); 781 else 782 dwc->usb2_phyif_utmi_width = 783 fdtdec_get_int(blob, node, "snps,phyif-utmi-bits", -1); 784 785 dwc3_cache_hwparams(dwc); 786 787 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 788 if (ret) { 789 dev_err(dwc->dev, "failed to allocate event buffers\n"); 790 return -ENOMEM; 791 } 792 793 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 794 dwc->dr_mode = USB_DR_MODE_HOST; 795 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 796 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 797 798 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 799 dwc->dr_mode = USB_DR_MODE_OTG; 800 801 ret = dwc3_core_init(dwc); 802 if (ret) { 803 dev_err(dev, "failed to initialize core\n"); 804 goto err0; 805 } 806 807 ret = dwc3_event_buffers_setup(dwc); 808 if (ret) { 809 dev_err(dwc->dev, "failed to setup event buffers\n"); 810 goto err1; 811 } 812 813 ret = dwc3_core_init_mode(dwc); 814 if (ret) 815 goto err2; 816 817 list_add_tail(&dwc->list, &dwc3_list); 818 819 return 0; 820 821 err2: 822 dwc3_event_buffers_cleanup(dwc); 823 824 err1: 825 dwc3_core_exit(dwc); 826 827 err0: 828 dwc3_free_event_buffers(dwc); 829 830 return ret; 831 } 832 833 /** 834 * dwc3_uboot_exit - dwc3 core uboot cleanup code 835 * @index: index of this controller 836 * 837 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc 838 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller 839 * should be passed and should match with the index passed in 840 * dwc3_device during init. 841 * 842 * Generally called from board file. 843 */ 844 void dwc3_uboot_exit(int index) 845 { 846 struct dwc3 *dwc; 847 848 list_for_each_entry(dwc, &dwc3_list, list) { 849 if (dwc->index != index) 850 continue; 851 852 dwc3_core_exit_mode(dwc); 853 dwc3_event_buffers_cleanup(dwc); 854 dwc3_free_event_buffers(dwc); 855 dwc3_core_exit(dwc); 856 list_del(&dwc->list); 857 kfree(dwc->mem); 858 break; 859 } 860 } 861 862 /** 863 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt 864 * @index: index of this controller 865 * 866 * Invokes dwc3 gadget interrupts. 867 * 868 * Generally called from board file. 869 */ 870 void dwc3_uboot_handle_interrupt(int index) 871 { 872 struct dwc3 *dwc = NULL; 873 874 list_for_each_entry(dwc, &dwc3_list, list) { 875 if (dwc->index != index) 876 continue; 877 878 dwc3_gadget_uboot_handle_interrupt(dwc); 879 break; 880 } 881 } 882 883 MODULE_ALIAS("platform:dwc3"); 884 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 885 MODULE_LICENSE("GPL v2"); 886 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 887 888 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) 889 int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys) 890 { 891 int i, ret, count; 892 struct phy *usb_phys; 893 894 /* Return if no phy declared */ 895 if (!dev_read_prop(dev, "phys", NULL)) 896 return 0; 897 count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); 898 if (count <= 0) 899 return count; 900 901 usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), 902 GFP_KERNEL); 903 if (!usb_phys) 904 return -ENOMEM; 905 906 for (i = 0; i < count; i++) { 907 ret = generic_phy_get_by_index(dev, i, &usb_phys[i]); 908 if (ret && ret != -ENOENT) { 909 pr_err("Failed to get USB PHY%d for %s\n", 910 i, dev->name); 911 return ret; 912 } 913 } 914 915 for (i = 0; i < count; i++) { 916 ret = generic_phy_init(&usb_phys[i]); 917 if (ret) { 918 pr_err("Can't init USB PHY%d for %s\n", 919 i, dev->name); 920 goto phys_init_err; 921 } 922 } 923 924 for (i = 0; i < count; i++) { 925 ret = generic_phy_power_on(&usb_phys[i]); 926 if (ret) { 927 pr_err("Can't power USB PHY%d for %s\n", 928 i, dev->name); 929 goto phys_poweron_err; 930 } 931 } 932 933 *array = usb_phys; 934 *num_phys = count; 935 return 0; 936 937 phys_poweron_err: 938 for (i = count - 1; i >= 0; i--) 939 generic_phy_power_off(&usb_phys[i]); 940 941 for (i = 0; i < count; i++) 942 generic_phy_exit(&usb_phys[i]); 943 944 return ret; 945 946 phys_init_err: 947 for (; i >= 0; i--) 948 generic_phy_exit(&usb_phys[i]); 949 950 return ret; 951 } 952 953 int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys) 954 { 955 int i, ret; 956 957 for (i = 0; i < num_phys; i++) { 958 if (!generic_phy_valid(&usb_phys[i])) 959 continue; 960 961 ret = generic_phy_power_off(&usb_phys[i]); 962 ret |= generic_phy_exit(&usb_phys[i]); 963 if (ret) { 964 pr_err("Can't shutdown USB PHY%d for %s\n", 965 i, dev->name); 966 } 967 } 968 969 return 0; 970 } 971 #endif 972 973 #if CONFIG_IS_ENABLED(DM_USB) 974 void dwc3_of_parse(struct dwc3 *dwc) 975 { 976 const u8 *tmp; 977 struct udevice *dev = dwc->dev; 978 u8 lpm_nyet_threshold; 979 u8 tx_de_emphasis; 980 u8 hird_threshold; 981 982 /* default to highest possible threshold */ 983 lpm_nyet_threshold = 0xff; 984 985 /* default to -3.5dB de-emphasis */ 986 tx_de_emphasis = 1; 987 988 /* 989 * default to assert utmi_sleep_n and use maximum allowed HIRD 990 * threshold value of 0b1100 991 */ 992 hird_threshold = 12; 993 994 dwc->hsphy_mode = usb_get_phy_mode(dev->node); 995 996 dwc->has_lpm_erratum = dev_read_bool(dev, 997 "snps,has-lpm-erratum"); 998 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1); 999 if (tmp) 1000 lpm_nyet_threshold = *tmp; 1001 1002 dwc->is_utmi_l1_suspend = dev_read_bool(dev, 1003 "snps,is-utmi-l1-suspend"); 1004 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1); 1005 if (tmp) 1006 hird_threshold = *tmp; 1007 1008 dwc->disable_scramble_quirk = dev_read_bool(dev, 1009 "snps,disable_scramble_quirk"); 1010 dwc->u2exit_lfps_quirk = dev_read_bool(dev, 1011 "snps,u2exit_lfps_quirk"); 1012 dwc->u2ss_inp3_quirk = dev_read_bool(dev, 1013 "snps,u2ss_inp3_quirk"); 1014 dwc->req_p1p2p3_quirk = dev_read_bool(dev, 1015 "snps,req_p1p2p3_quirk"); 1016 dwc->del_p1p2p3_quirk = dev_read_bool(dev, 1017 "snps,del_p1p2p3_quirk"); 1018 dwc->del_phy_power_chg_quirk = dev_read_bool(dev, 1019 "snps,del_phy_power_chg_quirk"); 1020 dwc->lfps_filter_quirk = dev_read_bool(dev, 1021 "snps,lfps_filter_quirk"); 1022 dwc->rx_detect_poll_quirk = dev_read_bool(dev, 1023 "snps,rx_detect_poll_quirk"); 1024 dwc->dis_u3_susphy_quirk = dev_read_bool(dev, 1025 "snps,dis_u3_susphy_quirk"); 1026 dwc->dis_u2_susphy_quirk = dev_read_bool(dev, 1027 "snps,dis_u2_susphy_quirk"); 1028 dwc->dis_enblslpm_quirk = dev_read_bool(dev, 1029 "snps,dis_enblslpm_quirk"); 1030 dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev, 1031 "snps,dis-u2-freeclk-exists-quirk"); 1032 dwc->tx_de_emphasis_quirk = dev_read_bool(dev, 1033 "snps,tx_de_emphasis_quirk"); 1034 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1); 1035 if (tmp) 1036 tx_de_emphasis = *tmp; 1037 1038 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1039 dwc->tx_de_emphasis = tx_de_emphasis; 1040 1041 dwc->hird_threshold = hird_threshold 1042 | (dwc->is_utmi_l1_suspend << 4); 1043 } 1044 1045 int dwc3_init(struct dwc3 *dwc) 1046 { 1047 int ret; 1048 1049 dwc3_cache_hwparams(dwc); 1050 1051 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1052 if (ret) { 1053 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1054 return -ENOMEM; 1055 } 1056 1057 ret = dwc3_core_init(dwc); 1058 if (ret) { 1059 dev_err(dev, "failed to initialize core\n"); 1060 goto core_fail; 1061 } 1062 1063 ret = dwc3_event_buffers_setup(dwc); 1064 if (ret) { 1065 dev_err(dwc->dev, "failed to setup event buffers\n"); 1066 goto event_fail; 1067 } 1068 1069 ret = dwc3_core_init_mode(dwc); 1070 if (ret) 1071 goto mode_fail; 1072 1073 return 0; 1074 1075 mode_fail: 1076 dwc3_event_buffers_cleanup(dwc); 1077 1078 event_fail: 1079 dwc3_core_exit(dwc); 1080 1081 core_fail: 1082 dwc3_free_event_buffers(dwc); 1083 1084 return ret; 1085 } 1086 1087 void dwc3_remove(struct dwc3 *dwc) 1088 { 1089 dwc3_core_exit_mode(dwc); 1090 dwc3_event_buffers_cleanup(dwc); 1091 dwc3_free_event_buffers(dwc); 1092 dwc3_core_exit(dwc); 1093 kfree(dwc->mem); 1094 } 1095 #endif 1096