1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported 10 * to uboot. 11 * 12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <common.h> 18 #include <malloc.h> 19 #include <fdtdec.h> 20 #include <dwc3-uboot.h> 21 #include <asm/dma-mapping.h> 22 #include <linux/ioport.h> 23 #include <dm.h> 24 #include <generic-phy.h> 25 #include <linux/usb/ch9.h> 26 #include <linux/usb/gadget.h> 27 28 #include "core.h" 29 #include "gadget.h" 30 #include "io.h" 31 32 #include "linux-compat.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 static LIST_HEAD(dwc3_list); 37 /* -------------------------------------------------------------------------- */ 38 39 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 40 { 41 u32 reg; 42 43 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 44 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 45 reg |= DWC3_GCTL_PRTCAPDIR(mode); 46 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 47 } 48 49 /** 50 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 51 * @dwc: pointer to our context structure 52 */ 53 static int dwc3_core_soft_reset(struct dwc3 *dwc) 54 { 55 u32 reg; 56 57 /* Before Resetting PHY, put Core in Reset */ 58 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 59 reg |= DWC3_GCTL_CORESOFTRESET; 60 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 61 62 /* Assert USB3 PHY reset */ 63 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 64 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 65 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 66 67 /* Assert USB2 PHY reset */ 68 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 69 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 70 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 71 72 mdelay(100); 73 74 /* Clear USB3 PHY reset */ 75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 76 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 78 79 /* Clear USB2 PHY reset */ 80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 81 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 83 84 mdelay(100); 85 86 /* After PHYs are stable we can take Core out of reset state */ 87 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 88 reg &= ~DWC3_GCTL_CORESOFTRESET; 89 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 90 91 return 0; 92 } 93 94 /** 95 * dwc3_free_one_event_buffer - Frees one event buffer 96 * @dwc: Pointer to our controller context structure 97 * @evt: Pointer to event buffer to be freed 98 */ 99 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 100 struct dwc3_event_buffer *evt) 101 { 102 dma_free_coherent(evt->buf); 103 } 104 105 /** 106 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 107 * @dwc: Pointer to our controller context structure 108 * @length: size of the event buffer 109 * 110 * Returns a pointer to the allocated event buffer structure on success 111 * otherwise ERR_PTR(errno). 112 */ 113 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 114 unsigned length) 115 { 116 struct dwc3_event_buffer *evt; 117 118 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt), 119 GFP_KERNEL); 120 if (!evt) 121 return ERR_PTR(-ENOMEM); 122 123 evt->dwc = dwc; 124 evt->length = length; 125 evt->buf = dma_alloc_coherent(length, 126 (unsigned long *)&evt->dma); 127 if (!evt->buf) 128 return ERR_PTR(-ENOMEM); 129 130 dwc3_flush_cache((uintptr_t)evt->buf, evt->length); 131 132 return evt; 133 } 134 135 /** 136 * dwc3_free_event_buffers - frees all allocated event buffers 137 * @dwc: Pointer to our controller context structure 138 */ 139 static void dwc3_free_event_buffers(struct dwc3 *dwc) 140 { 141 struct dwc3_event_buffer *evt; 142 int i; 143 144 for (i = 0; i < dwc->num_event_buffers; i++) { 145 evt = dwc->ev_buffs[i]; 146 if (evt) 147 dwc3_free_one_event_buffer(dwc, evt); 148 } 149 } 150 151 /** 152 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 153 * @dwc: pointer to our controller context structure 154 * @length: size of event buffer 155 * 156 * Returns 0 on success otherwise negative errno. In the error case, dwc 157 * may contain some buffers allocated but not all which were requested. 158 */ 159 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 160 { 161 int num; 162 int i; 163 164 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 165 dwc->num_event_buffers = num; 166 167 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE, 168 sizeof(*dwc->ev_buffs) * num); 169 if (!dwc->ev_buffs) 170 return -ENOMEM; 171 172 for (i = 0; i < num; i++) { 173 struct dwc3_event_buffer *evt; 174 175 evt = dwc3_alloc_one_event_buffer(dwc, length); 176 if (IS_ERR(evt)) { 177 dev_err(dwc->dev, "can't allocate event buffer\n"); 178 return PTR_ERR(evt); 179 } 180 dwc->ev_buffs[i] = evt; 181 } 182 183 return 0; 184 } 185 186 /** 187 * dwc3_event_buffers_setup - setup our allocated event buffers 188 * @dwc: pointer to our controller context structure 189 * 190 * Returns 0 on success otherwise negative errno. 191 */ 192 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 193 { 194 struct dwc3_event_buffer *evt; 195 int n; 196 197 for (n = 0; n < dwc->num_event_buffers; n++) { 198 evt = dwc->ev_buffs[n]; 199 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 200 evt->buf, (unsigned long long) evt->dma, 201 evt->length); 202 203 evt->lpos = 0; 204 205 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 206 lower_32_bits(evt->dma)); 207 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 208 upper_32_bits(evt->dma)); 209 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 210 DWC3_GEVNTSIZ_SIZE(evt->length)); 211 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 212 } 213 214 return 0; 215 } 216 217 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 218 { 219 struct dwc3_event_buffer *evt; 220 int n; 221 222 for (n = 0; n < dwc->num_event_buffers; n++) { 223 evt = dwc->ev_buffs[n]; 224 225 evt->lpos = 0; 226 227 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 228 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 229 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 230 | DWC3_GEVNTSIZ_SIZE(0)); 231 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 232 } 233 } 234 235 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 236 { 237 if (!dwc->has_hibernation) 238 return 0; 239 240 if (!dwc->nr_scratch) 241 return 0; 242 243 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 244 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 245 if (!dwc->scratchbuf) 246 return -ENOMEM; 247 248 return 0; 249 } 250 251 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 252 { 253 dma_addr_t scratch_addr; 254 u32 param; 255 int ret; 256 257 if (!dwc->has_hibernation) 258 return 0; 259 260 if (!dwc->nr_scratch) 261 return 0; 262 263 scratch_addr = dma_map_single(dwc->scratchbuf, 264 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 265 DMA_BIDIRECTIONAL); 266 if (dma_mapping_error(dwc->dev, scratch_addr)) { 267 dev_err(dwc->dev, "failed to map scratch buffer\n"); 268 ret = -EFAULT; 269 goto err0; 270 } 271 272 dwc->scratch_addr = scratch_addr; 273 274 param = lower_32_bits(scratch_addr); 275 276 ret = dwc3_send_gadget_generic_command(dwc, 277 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 278 if (ret < 0) 279 goto err1; 280 281 param = upper_32_bits(scratch_addr); 282 283 ret = dwc3_send_gadget_generic_command(dwc, 284 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 285 if (ret < 0) 286 goto err1; 287 288 return 0; 289 290 err1: 291 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 292 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 293 294 err0: 295 return ret; 296 } 297 298 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 299 { 300 if (!dwc->has_hibernation) 301 return; 302 303 if (!dwc->nr_scratch) 304 return; 305 306 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 307 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 308 kfree(dwc->scratchbuf); 309 } 310 311 static void dwc3_core_num_eps(struct dwc3 *dwc) 312 { 313 struct dwc3_hwparams *parms = &dwc->hwparams; 314 315 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 316 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 317 318 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", 319 dwc->num_in_eps, dwc->num_out_eps); 320 } 321 322 static void dwc3_cache_hwparams(struct dwc3 *dwc) 323 { 324 struct dwc3_hwparams *parms = &dwc->hwparams; 325 326 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 327 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 328 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 329 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 330 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 331 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 332 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 333 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 334 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 335 } 336 337 static void dwc3_hsphy_mode_setup(struct dwc3 *dwc) 338 { 339 enum usb_phy_interface hsphy_mode = dwc->hsphy_mode; 340 u32 reg; 341 342 /* Set dwc3 usb2 phy config */ 343 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 344 345 switch (hsphy_mode) { 346 case USBPHY_INTERFACE_MODE_UTMI: 347 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 348 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 349 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 350 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 351 break; 352 case USBPHY_INTERFACE_MODE_UTMIW: 353 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 354 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 355 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 356 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 357 break; 358 default: 359 break; 360 } 361 362 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 363 } 364 365 /** 366 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 367 * @dwc: Pointer to our controller context structure 368 */ 369 static void dwc3_phy_setup(struct dwc3 *dwc) 370 { 371 u32 reg; 372 373 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 374 375 /* 376 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 377 * to '0' during coreConsultant configuration. So default value 378 * will be '0' when the core is reset. Application needs to set it 379 * to '1' after the core initialization is completed. 380 */ 381 if (dwc->revision > DWC3_REVISION_194A) 382 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 383 384 if (dwc->u2ss_inp3_quirk) 385 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 386 387 if (dwc->req_p1p2p3_quirk) 388 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 389 390 if (dwc->del_p1p2p3_quirk) 391 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 392 393 if (dwc->del_phy_power_chg_quirk) 394 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 395 396 if (dwc->lfps_filter_quirk) 397 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 398 399 if (dwc->rx_detect_poll_quirk) 400 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 401 402 if (dwc->tx_de_emphasis_quirk) 403 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 404 405 if (dwc->dis_u3_susphy_quirk) 406 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 407 408 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 409 410 dwc3_hsphy_mode_setup(dwc); 411 412 mdelay(100); 413 414 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 415 416 /* 417 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 418 * '0' during coreConsultant configuration. So default value will 419 * be '0' when the core is reset. Application needs to set it to 420 * '1' after the core initialization is completed. 421 */ 422 if (dwc->revision > DWC3_REVISION_194A) 423 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 424 425 if (dwc->dis_u2_susphy_quirk) 426 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 427 428 if (dwc->dis_enblslpm_quirk) 429 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 430 431 if (dwc->dis_u2_freeclk_exists_quirk) 432 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 433 434 if (dwc->usb2_phyif_utmi_width == 16) { 435 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 436 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 437 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 438 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT); 439 } 440 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 441 442 mdelay(100); 443 } 444 445 /** 446 * dwc3_core_init - Low-level initialization of DWC3 Core 447 * @dwc: Pointer to our controller context structure 448 * 449 * Returns 0 on success otherwise negative errno. 450 */ 451 static int dwc3_core_init(struct dwc3 *dwc) 452 { 453 unsigned long timeout; 454 u32 hwparams4 = dwc->hwparams.hwparams4; 455 u32 reg; 456 int ret; 457 458 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 459 /* This should read as U3 followed by revision number */ 460 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 461 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 462 ret = -ENODEV; 463 goto err0; 464 } 465 dwc->revision = reg; 466 467 /* Handle USB2.0-only core configuration */ 468 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 469 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 470 if (dwc->maximum_speed == USB_SPEED_SUPER) 471 dwc->maximum_speed = USB_SPEED_HIGH; 472 } 473 474 /* issue device SoftReset too */ 475 timeout = 5000; 476 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 477 while (timeout--) { 478 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 479 if (!(reg & DWC3_DCTL_CSFTRST)) 480 break; 481 }; 482 483 if (!timeout) { 484 dev_err(dwc->dev, "Reset Timed Out\n"); 485 ret = -ETIMEDOUT; 486 goto err0; 487 } 488 489 ret = dwc3_core_soft_reset(dwc); 490 if (ret) 491 goto err0; 492 493 if (dwc->revision >= DWC3_REVISION_250A) { 494 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 495 496 if (dwc->maximum_speed == USB_SPEED_HIGH || 497 dwc->maximum_speed == USB_SPEED_FULL) 498 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 499 500 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 501 } 502 503 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 504 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 505 506 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 507 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 508 /** 509 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 510 * issue which would cause xHCI compliance tests to fail. 511 * 512 * Because of that we cannot enable clock gating on such 513 * configurations. 514 * 515 * Refers to: 516 * 517 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 518 * SOF/ITP Mode Used 519 */ 520 if ((dwc->dr_mode == USB_DR_MODE_HOST || 521 dwc->dr_mode == USB_DR_MODE_OTG) && 522 (dwc->revision >= DWC3_REVISION_210A && 523 dwc->revision <= DWC3_REVISION_250A)) 524 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 525 else 526 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 527 break; 528 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 529 /* enable hibernation here */ 530 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 531 532 /* 533 * REVISIT Enabling this bit so that host-mode hibernation 534 * will work. Device-mode hibernation is not yet implemented. 535 */ 536 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 537 break; 538 default: 539 dev_dbg(dwc->dev, "No power optimization available\n"); 540 } 541 542 /* check if current dwc3 is on simulation board */ 543 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 544 dev_dbg(dwc->dev, "it is on FPGA board\n"); 545 dwc->is_fpga = true; 546 } 547 548 if(dwc->disable_scramble_quirk && !dwc->is_fpga) 549 WARN(true, 550 "disable_scramble cannot be used on non-FPGA builds\n"); 551 552 if (dwc->disable_scramble_quirk && dwc->is_fpga) 553 reg |= DWC3_GCTL_DISSCRAMBLE; 554 else 555 reg &= ~DWC3_GCTL_DISSCRAMBLE; 556 557 if (dwc->u2exit_lfps_quirk) 558 reg |= DWC3_GCTL_U2EXIT_LFPS; 559 560 /* 561 * WORKAROUND: DWC3 revisions <1.90a have a bug 562 * where the device can fail to connect at SuperSpeed 563 * and falls back to high-speed mode which causes 564 * the device to enter a Connect/Disconnect loop 565 */ 566 if (dwc->revision < DWC3_REVISION_190A) 567 reg |= DWC3_GCTL_U2RSTECN; 568 569 dwc3_core_num_eps(dwc); 570 571 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 572 573 dwc3_phy_setup(dwc); 574 575 ret = dwc3_alloc_scratch_buffers(dwc); 576 if (ret) 577 goto err0; 578 579 ret = dwc3_setup_scratch_buffers(dwc); 580 if (ret) 581 goto err1; 582 583 return 0; 584 585 err1: 586 dwc3_free_scratch_buffers(dwc); 587 588 err0: 589 return ret; 590 } 591 592 static void dwc3_core_exit(struct dwc3 *dwc) 593 { 594 dwc3_free_scratch_buffers(dwc); 595 } 596 597 static int dwc3_core_init_mode(struct dwc3 *dwc) 598 { 599 int ret; 600 601 switch (dwc->dr_mode) { 602 case USB_DR_MODE_PERIPHERAL: 603 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 604 ret = dwc3_gadget_init(dwc); 605 if (ret) { 606 dev_err(dev, "failed to initialize gadget\n"); 607 return ret; 608 } 609 break; 610 case USB_DR_MODE_HOST: 611 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 612 ret = dwc3_host_init(dwc); 613 if (ret) { 614 dev_err(dev, "failed to initialize host\n"); 615 return ret; 616 } 617 break; 618 case USB_DR_MODE_OTG: 619 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 620 ret = dwc3_host_init(dwc); 621 if (ret) { 622 dev_err(dev, "failed to initialize host\n"); 623 return ret; 624 } 625 626 ret = dwc3_gadget_init(dwc); 627 if (ret) { 628 dev_err(dev, "failed to initialize gadget\n"); 629 return ret; 630 } 631 break; 632 default: 633 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 634 return -EINVAL; 635 } 636 637 return 0; 638 } 639 640 static void dwc3_gadget_run(struct dwc3 *dwc) 641 { 642 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP); 643 mdelay(100); 644 } 645 646 static void dwc3_core_exit_mode(struct dwc3 *dwc) 647 { 648 switch (dwc->dr_mode) { 649 case USB_DR_MODE_PERIPHERAL: 650 dwc3_gadget_exit(dwc); 651 break; 652 case USB_DR_MODE_HOST: 653 dwc3_host_exit(dwc); 654 break; 655 case USB_DR_MODE_OTG: 656 dwc3_host_exit(dwc); 657 dwc3_gadget_exit(dwc); 658 break; 659 default: 660 /* do nothing */ 661 break; 662 } 663 664 /* 665 * switch back to peripheral mode 666 * This enables the phy to enter idle and then, if enabled, suspend. 667 */ 668 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 669 dwc3_gadget_run(dwc); 670 } 671 672 #define DWC3_ALIGN_MASK (16 - 1) 673 674 /** 675 * dwc3_uboot_init - dwc3 core uboot initialization code 676 * @dwc3_dev: struct dwc3_device containing initialization data 677 * 678 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux 679 * kernel driver). Pointer to dwc3_device should be passed containing 680 * base address and other initialization data. Returns '0' on success and 681 * a negative value on failure. 682 * 683 * Generally called from board_usb_init() implemented in board file. 684 */ 685 int dwc3_uboot_init(struct dwc3_device *dwc3_dev) 686 { 687 struct dwc3 *dwc; 688 struct device *dev = NULL; 689 u8 lpm_nyet_threshold; 690 u8 tx_de_emphasis; 691 u8 hird_threshold; 692 693 int ret; 694 695 void *mem; 696 const void *blob = gd->fdt_blob; 697 int node; 698 699 mem = devm_kzalloc((struct udevice *)dev, 700 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 701 if (!mem) 702 return -ENOMEM; 703 704 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 705 dwc->mem = mem; 706 707 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base + 708 DWC3_GLOBALS_REGS_START); 709 710 /* default to highest possible threshold */ 711 lpm_nyet_threshold = 0xff; 712 713 /* default to -3.5dB de-emphasis */ 714 tx_de_emphasis = 1; 715 716 /* 717 * default to assert utmi_sleep_n and use maximum allowed HIRD 718 * threshold value of 0b1100 719 */ 720 hird_threshold = 12; 721 722 dwc->maximum_speed = dwc3_dev->maximum_speed; 723 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum; 724 if (dwc3_dev->lpm_nyet_threshold) 725 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold; 726 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend; 727 if (dwc3_dev->hird_threshold) 728 hird_threshold = dwc3_dev->hird_threshold; 729 730 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize; 731 dwc->dr_mode = dwc3_dev->dr_mode; 732 733 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk; 734 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk; 735 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk; 736 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk; 737 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk; 738 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk; 739 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk; 740 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk; 741 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk; 742 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; 743 dwc->dis_u1u2_quirk = dwc3_dev->dis_u2_susphy_quirk; 744 745 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk; 746 if (dwc3_dev->tx_de_emphasis) 747 tx_de_emphasis = dwc3_dev->tx_de_emphasis; 748 749 /* default to superspeed if no maximum_speed passed */ 750 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 751 dwc->maximum_speed = USB_SPEED_SUPER; 752 753 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 754 dwc->tx_de_emphasis = tx_de_emphasis; 755 756 dwc->hird_threshold = hird_threshold 757 | (dwc->is_utmi_l1_suspend << 4); 758 759 dwc->hsphy_mode = dwc3_dev->hsphy_mode; 760 761 dwc->index = dwc3_dev->index; 762 763 if (dwc3_dev->usb2_phyif_utmi_width) 764 dwc->usb2_phyif_utmi_width = dwc3_dev->usb2_phyif_utmi_width; 765 766 node = fdt_node_offset_by_compatible(blob, -1, 767 "rockchip,rk3399-xhci"); 768 if (node < 0) 769 debug("%s dwc3 node not found\n", __func__); 770 else 771 dwc->usb2_phyif_utmi_width = 772 fdtdec_get_int(blob, node, "snps,phyif-utmi-bits", -1); 773 774 dwc3_cache_hwparams(dwc); 775 776 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 777 if (ret) { 778 dev_err(dwc->dev, "failed to allocate event buffers\n"); 779 return -ENOMEM; 780 } 781 782 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 783 dwc->dr_mode = USB_DR_MODE_HOST; 784 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 785 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 786 787 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 788 dwc->dr_mode = USB_DR_MODE_OTG; 789 790 ret = dwc3_core_init(dwc); 791 if (ret) { 792 dev_err(dev, "failed to initialize core\n"); 793 goto err0; 794 } 795 796 ret = dwc3_event_buffers_setup(dwc); 797 if (ret) { 798 dev_err(dwc->dev, "failed to setup event buffers\n"); 799 goto err1; 800 } 801 802 ret = dwc3_core_init_mode(dwc); 803 if (ret) 804 goto err2; 805 806 list_add_tail(&dwc->list, &dwc3_list); 807 808 return 0; 809 810 err2: 811 dwc3_event_buffers_cleanup(dwc); 812 813 err1: 814 dwc3_core_exit(dwc); 815 816 err0: 817 dwc3_free_event_buffers(dwc); 818 819 return ret; 820 } 821 822 /** 823 * dwc3_uboot_exit - dwc3 core uboot cleanup code 824 * @index: index of this controller 825 * 826 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc 827 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller 828 * should be passed and should match with the index passed in 829 * dwc3_device during init. 830 * 831 * Generally called from board file. 832 */ 833 void dwc3_uboot_exit(int index) 834 { 835 struct dwc3 *dwc; 836 837 list_for_each_entry(dwc, &dwc3_list, list) { 838 if (dwc->index != index) 839 continue; 840 841 dwc3_core_exit_mode(dwc); 842 dwc3_event_buffers_cleanup(dwc); 843 dwc3_free_event_buffers(dwc); 844 dwc3_core_exit(dwc); 845 list_del(&dwc->list); 846 kfree(dwc->mem); 847 break; 848 } 849 } 850 851 /** 852 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt 853 * @index: index of this controller 854 * 855 * Invokes dwc3 gadget interrupts. 856 * 857 * Generally called from board file. 858 */ 859 void dwc3_uboot_handle_interrupt(int index) 860 { 861 struct dwc3 *dwc = NULL; 862 863 list_for_each_entry(dwc, &dwc3_list, list) { 864 if (dwc->index != index) 865 continue; 866 867 dwc3_gadget_uboot_handle_interrupt(dwc); 868 break; 869 } 870 } 871 872 MODULE_ALIAS("platform:dwc3"); 873 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 874 MODULE_LICENSE("GPL v2"); 875 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 876 877 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) 878 int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys) 879 { 880 int i, ret, count; 881 struct phy *usb_phys; 882 883 /* Return if no phy declared */ 884 if (!dev_read_prop(dev, "phys", NULL)) 885 return 0; 886 count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); 887 if (count <= 0) 888 return count; 889 890 usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), 891 GFP_KERNEL); 892 if (!usb_phys) 893 return -ENOMEM; 894 895 for (i = 0; i < count; i++) { 896 ret = generic_phy_get_by_index(dev, i, &usb_phys[i]); 897 if (ret && ret != -ENOENT) { 898 pr_err("Failed to get USB PHY%d for %s\n", 899 i, dev->name); 900 return ret; 901 } 902 } 903 904 for (i = 0; i < count; i++) { 905 ret = generic_phy_init(&usb_phys[i]); 906 if (ret) { 907 pr_err("Can't init USB PHY%d for %s\n", 908 i, dev->name); 909 goto phys_init_err; 910 } 911 } 912 913 for (i = 0; i < count; i++) { 914 ret = generic_phy_power_on(&usb_phys[i]); 915 if (ret) { 916 pr_err("Can't power USB PHY%d for %s\n", 917 i, dev->name); 918 goto phys_poweron_err; 919 } 920 } 921 922 *array = usb_phys; 923 *num_phys = count; 924 return 0; 925 926 phys_poweron_err: 927 for (i = count - 1; i >= 0; i--) 928 generic_phy_power_off(&usb_phys[i]); 929 930 for (i = 0; i < count; i++) 931 generic_phy_exit(&usb_phys[i]); 932 933 return ret; 934 935 phys_init_err: 936 for (; i >= 0; i--) 937 generic_phy_exit(&usb_phys[i]); 938 939 return ret; 940 } 941 942 int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys) 943 { 944 int i, ret; 945 946 for (i = 0; i < num_phys; i++) { 947 if (!generic_phy_valid(&usb_phys[i])) 948 continue; 949 950 ret = generic_phy_power_off(&usb_phys[i]); 951 ret |= generic_phy_exit(&usb_phys[i]); 952 if (ret) { 953 pr_err("Can't shutdown USB PHY%d for %s\n", 954 i, dev->name); 955 } 956 } 957 958 return 0; 959 } 960 #endif 961 962 #if CONFIG_IS_ENABLED(DM_USB) 963 void dwc3_of_parse(struct dwc3 *dwc) 964 { 965 const u8 *tmp; 966 struct udevice *dev = dwc->dev; 967 u8 lpm_nyet_threshold; 968 u8 tx_de_emphasis; 969 u8 hird_threshold; 970 971 /* default to highest possible threshold */ 972 lpm_nyet_threshold = 0xff; 973 974 /* default to -3.5dB de-emphasis */ 975 tx_de_emphasis = 1; 976 977 /* 978 * default to assert utmi_sleep_n and use maximum allowed HIRD 979 * threshold value of 0b1100 980 */ 981 hird_threshold = 12; 982 983 dwc->hsphy_mode = usb_get_phy_mode(dev->node); 984 985 dwc->has_lpm_erratum = dev_read_bool(dev, 986 "snps,has-lpm-erratum"); 987 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1); 988 if (tmp) 989 lpm_nyet_threshold = *tmp; 990 991 dwc->is_utmi_l1_suspend = dev_read_bool(dev, 992 "snps,is-utmi-l1-suspend"); 993 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1); 994 if (tmp) 995 hird_threshold = *tmp; 996 997 dwc->disable_scramble_quirk = dev_read_bool(dev, 998 "snps,disable_scramble_quirk"); 999 dwc->u2exit_lfps_quirk = dev_read_bool(dev, 1000 "snps,u2exit_lfps_quirk"); 1001 dwc->u2ss_inp3_quirk = dev_read_bool(dev, 1002 "snps,u2ss_inp3_quirk"); 1003 dwc->req_p1p2p3_quirk = dev_read_bool(dev, 1004 "snps,req_p1p2p3_quirk"); 1005 dwc->del_p1p2p3_quirk = dev_read_bool(dev, 1006 "snps,del_p1p2p3_quirk"); 1007 dwc->del_phy_power_chg_quirk = dev_read_bool(dev, 1008 "snps,del_phy_power_chg_quirk"); 1009 dwc->lfps_filter_quirk = dev_read_bool(dev, 1010 "snps,lfps_filter_quirk"); 1011 dwc->rx_detect_poll_quirk = dev_read_bool(dev, 1012 "snps,rx_detect_poll_quirk"); 1013 dwc->dis_u3_susphy_quirk = dev_read_bool(dev, 1014 "snps,dis_u3_susphy_quirk"); 1015 dwc->dis_u2_susphy_quirk = dev_read_bool(dev, 1016 "snps,dis_u2_susphy_quirk"); 1017 dwc->dis_enblslpm_quirk = dev_read_bool(dev, 1018 "snps,dis_enblslpm_quirk"); 1019 dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev, 1020 "snps,dis-u2-freeclk-exists-quirk"); 1021 dwc->tx_de_emphasis_quirk = dev_read_bool(dev, 1022 "snps,tx_de_emphasis_quirk"); 1023 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1); 1024 if (tmp) 1025 tx_de_emphasis = *tmp; 1026 1027 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1028 dwc->tx_de_emphasis = tx_de_emphasis; 1029 1030 dwc->hird_threshold = hird_threshold 1031 | (dwc->is_utmi_l1_suspend << 4); 1032 } 1033 1034 int dwc3_init(struct dwc3 *dwc) 1035 { 1036 int ret; 1037 1038 dwc3_cache_hwparams(dwc); 1039 1040 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1041 if (ret) { 1042 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1043 return -ENOMEM; 1044 } 1045 1046 ret = dwc3_core_init(dwc); 1047 if (ret) { 1048 dev_err(dev, "failed to initialize core\n"); 1049 goto core_fail; 1050 } 1051 1052 ret = dwc3_event_buffers_setup(dwc); 1053 if (ret) { 1054 dev_err(dwc->dev, "failed to setup event buffers\n"); 1055 goto event_fail; 1056 } 1057 1058 ret = dwc3_core_init_mode(dwc); 1059 if (ret) 1060 goto mode_fail; 1061 1062 return 0; 1063 1064 mode_fail: 1065 dwc3_event_buffers_cleanup(dwc); 1066 1067 event_fail: 1068 dwc3_core_exit(dwc); 1069 1070 core_fail: 1071 dwc3_free_event_buffers(dwc); 1072 1073 return ret; 1074 } 1075 1076 void dwc3_remove(struct dwc3 *dwc) 1077 { 1078 dwc3_core_exit_mode(dwc); 1079 dwc3_event_buffers_cleanup(dwc); 1080 dwc3_free_event_buffers(dwc); 1081 dwc3_core_exit(dwc); 1082 kfree(dwc->mem); 1083 } 1084 #endif 1085