1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported 10 * to uboot. 11 * 12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <common.h> 18 #include <malloc.h> 19 #include <fdtdec.h> 20 #include <dwc3-uboot.h> 21 #include <asm/dma-mapping.h> 22 #include <linux/ioport.h> 23 #include <dm.h> 24 #include <generic-phy.h> 25 #include <linux/usb/ch9.h> 26 #include <linux/usb/gadget.h> 27 28 #include "core.h" 29 #include "gadget.h" 30 #include "io.h" 31 32 #include "linux-compat.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 static LIST_HEAD(dwc3_list); 37 /* -------------------------------------------------------------------------- */ 38 39 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 40 { 41 u32 reg; 42 43 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 44 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 45 reg |= DWC3_GCTL_PRTCAPDIR(mode); 46 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 47 } 48 49 /** 50 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 51 * @dwc: pointer to our context structure 52 */ 53 static int dwc3_core_soft_reset(struct dwc3 *dwc) 54 { 55 u32 reg; 56 57 /* Before Resetting PHY, put Core in Reset */ 58 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 59 reg |= DWC3_GCTL_CORESOFTRESET; 60 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 61 62 /* Assert USB3 PHY reset */ 63 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 64 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 65 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 66 67 /* Assert USB2 PHY reset */ 68 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 69 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 70 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 71 72 mdelay(100); 73 74 /* Clear USB3 PHY reset */ 75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 76 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 78 79 /* Clear USB2 PHY reset */ 80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 81 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 83 84 mdelay(100); 85 86 /* After PHYs are stable we can take Core out of reset state */ 87 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 88 reg &= ~DWC3_GCTL_CORESOFTRESET; 89 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 90 91 return 0; 92 } 93 94 /** 95 * dwc3_free_one_event_buffer - Frees one event buffer 96 * @dwc: Pointer to our controller context structure 97 * @evt: Pointer to event buffer to be freed 98 */ 99 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 100 struct dwc3_event_buffer *evt) 101 { 102 dma_free_coherent(evt->buf); 103 } 104 105 /** 106 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 107 * @dwc: Pointer to our controller context structure 108 * @length: size of the event buffer 109 * 110 * Returns a pointer to the allocated event buffer structure on success 111 * otherwise ERR_PTR(errno). 112 */ 113 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 114 unsigned length) 115 { 116 struct dwc3_event_buffer *evt; 117 118 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt), 119 GFP_KERNEL); 120 if (!evt) 121 return ERR_PTR(-ENOMEM); 122 123 evt->dwc = dwc; 124 evt->length = length; 125 evt->buf = dma_alloc_coherent(length, 126 (unsigned long *)&evt->dma); 127 if (!evt->buf) 128 return ERR_PTR(-ENOMEM); 129 130 dwc3_flush_cache((uintptr_t)evt->buf, evt->length); 131 132 return evt; 133 } 134 135 /** 136 * dwc3_free_event_buffers - frees all allocated event buffers 137 * @dwc: Pointer to our controller context structure 138 */ 139 static void dwc3_free_event_buffers(struct dwc3 *dwc) 140 { 141 struct dwc3_event_buffer *evt; 142 int i; 143 144 for (i = 0; i < dwc->num_event_buffers; i++) { 145 evt = dwc->ev_buffs[i]; 146 if (evt) 147 dwc3_free_one_event_buffer(dwc, evt); 148 } 149 } 150 151 /** 152 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 153 * @dwc: pointer to our controller context structure 154 * @length: size of event buffer 155 * 156 * Returns 0 on success otherwise negative errno. In the error case, dwc 157 * may contain some buffers allocated but not all which were requested. 158 */ 159 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 160 { 161 int num; 162 int i; 163 164 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 165 dwc->num_event_buffers = num; 166 167 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE, 168 sizeof(*dwc->ev_buffs) * num); 169 if (!dwc->ev_buffs) 170 return -ENOMEM; 171 172 for (i = 0; i < num; i++) { 173 struct dwc3_event_buffer *evt; 174 175 evt = dwc3_alloc_one_event_buffer(dwc, length); 176 if (IS_ERR(evt)) { 177 dev_err(dwc->dev, "can't allocate event buffer\n"); 178 return PTR_ERR(evt); 179 } 180 dwc->ev_buffs[i] = evt; 181 } 182 183 return 0; 184 } 185 186 /** 187 * dwc3_event_buffers_setup - setup our allocated event buffers 188 * @dwc: pointer to our controller context structure 189 * 190 * Returns 0 on success otherwise negative errno. 191 */ 192 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 193 { 194 struct dwc3_event_buffer *evt; 195 int n; 196 197 for (n = 0; n < dwc->num_event_buffers; n++) { 198 evt = dwc->ev_buffs[n]; 199 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 200 evt->buf, (unsigned long long) evt->dma, 201 evt->length); 202 203 evt->lpos = 0; 204 205 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 206 lower_32_bits(evt->dma)); 207 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 208 upper_32_bits(evt->dma)); 209 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 210 DWC3_GEVNTSIZ_SIZE(evt->length)); 211 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 212 } 213 214 return 0; 215 } 216 217 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 218 { 219 struct dwc3_event_buffer *evt; 220 int n; 221 222 for (n = 0; n < dwc->num_event_buffers; n++) { 223 evt = dwc->ev_buffs[n]; 224 225 evt->lpos = 0; 226 227 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 228 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 229 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 230 | DWC3_GEVNTSIZ_SIZE(0)); 231 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 232 } 233 } 234 235 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 236 { 237 if (!dwc->has_hibernation) 238 return 0; 239 240 if (!dwc->nr_scratch) 241 return 0; 242 243 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 244 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 245 if (!dwc->scratchbuf) 246 return -ENOMEM; 247 248 return 0; 249 } 250 251 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 252 { 253 dma_addr_t scratch_addr; 254 u32 param; 255 int ret; 256 257 if (!dwc->has_hibernation) 258 return 0; 259 260 if (!dwc->nr_scratch) 261 return 0; 262 263 scratch_addr = dma_map_single(dwc->scratchbuf, 264 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 265 DMA_BIDIRECTIONAL); 266 if (dma_mapping_error(dwc->dev, scratch_addr)) { 267 dev_err(dwc->dev, "failed to map scratch buffer\n"); 268 ret = -EFAULT; 269 goto err0; 270 } 271 272 dwc->scratch_addr = scratch_addr; 273 274 param = lower_32_bits(scratch_addr); 275 276 ret = dwc3_send_gadget_generic_command(dwc, 277 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 278 if (ret < 0) 279 goto err1; 280 281 param = upper_32_bits(scratch_addr); 282 283 ret = dwc3_send_gadget_generic_command(dwc, 284 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 285 if (ret < 0) 286 goto err1; 287 288 return 0; 289 290 err1: 291 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 292 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 293 294 err0: 295 return ret; 296 } 297 298 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 299 { 300 if (!dwc->has_hibernation) 301 return; 302 303 if (!dwc->nr_scratch) 304 return; 305 306 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 307 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 308 kfree(dwc->scratchbuf); 309 } 310 311 static void dwc3_core_num_eps(struct dwc3 *dwc) 312 { 313 struct dwc3_hwparams *parms = &dwc->hwparams; 314 315 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 316 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 317 318 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", 319 dwc->num_in_eps, dwc->num_out_eps); 320 } 321 322 static void dwc3_cache_hwparams(struct dwc3 *dwc) 323 { 324 struct dwc3_hwparams *parms = &dwc->hwparams; 325 326 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 327 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 328 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 329 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 330 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 331 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 332 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 333 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 334 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 335 } 336 337 /** 338 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 339 * @dwc: Pointer to our controller context structure 340 */ 341 static void dwc3_phy_setup(struct dwc3 *dwc) 342 { 343 u32 reg; 344 345 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 346 347 /* 348 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 349 * to '0' during coreConsultant configuration. So default value 350 * will be '0' when the core is reset. Application needs to set it 351 * to '1' after the core initialization is completed. 352 */ 353 if (dwc->revision > DWC3_REVISION_194A) 354 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 355 356 if (dwc->u2ss_inp3_quirk) 357 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 358 359 if (dwc->req_p1p2p3_quirk) 360 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 361 362 if (dwc->del_p1p2p3_quirk) 363 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 364 365 if (dwc->del_phy_power_chg_quirk) 366 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 367 368 if (dwc->lfps_filter_quirk) 369 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 370 371 if (dwc->rx_detect_poll_quirk) 372 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 373 374 if (dwc->tx_de_emphasis_quirk) 375 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 376 377 if (dwc->dis_u3_susphy_quirk) 378 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 379 380 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 381 382 mdelay(100); 383 384 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 385 386 /* 387 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 388 * '0' during coreConsultant configuration. So default value will 389 * be '0' when the core is reset. Application needs to set it to 390 * '1' after the core initialization is completed. 391 */ 392 if (dwc->revision > DWC3_REVISION_194A) 393 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 394 395 if (dwc->dis_u2_susphy_quirk) 396 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 397 398 if (dwc->usb2_phyif_utmi_width == 16) { 399 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 400 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 401 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 402 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT); 403 } 404 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 405 406 mdelay(100); 407 } 408 409 /** 410 * dwc3_core_init - Low-level initialization of DWC3 Core 411 * @dwc: Pointer to our controller context structure 412 * 413 * Returns 0 on success otherwise negative errno. 414 */ 415 static int dwc3_core_init(struct dwc3 *dwc) 416 { 417 unsigned long timeout; 418 u32 hwparams4 = dwc->hwparams.hwparams4; 419 u32 reg; 420 int ret; 421 422 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 423 /* This should read as U3 followed by revision number */ 424 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 425 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 426 ret = -ENODEV; 427 goto err0; 428 } 429 dwc->revision = reg; 430 431 /* Handle USB2.0-only core configuration */ 432 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 433 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 434 if (dwc->maximum_speed == USB_SPEED_SUPER) 435 dwc->maximum_speed = USB_SPEED_HIGH; 436 } 437 438 /* issue device SoftReset too */ 439 timeout = 5000; 440 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 441 while (timeout--) { 442 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 443 if (!(reg & DWC3_DCTL_CSFTRST)) 444 break; 445 }; 446 447 if (!timeout) { 448 dev_err(dwc->dev, "Reset Timed Out\n"); 449 ret = -ETIMEDOUT; 450 goto err0; 451 } 452 453 dwc3_phy_setup(dwc); 454 455 ret = dwc3_core_soft_reset(dwc); 456 if (ret) 457 goto err0; 458 459 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 460 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 461 462 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 463 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 464 /** 465 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 466 * issue which would cause xHCI compliance tests to fail. 467 * 468 * Because of that we cannot enable clock gating on such 469 * configurations. 470 * 471 * Refers to: 472 * 473 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 474 * SOF/ITP Mode Used 475 */ 476 if ((dwc->dr_mode == USB_DR_MODE_HOST || 477 dwc->dr_mode == USB_DR_MODE_OTG) && 478 (dwc->revision >= DWC3_REVISION_210A && 479 dwc->revision <= DWC3_REVISION_250A)) 480 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 481 else 482 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 483 break; 484 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 485 /* enable hibernation here */ 486 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 487 488 /* 489 * REVISIT Enabling this bit so that host-mode hibernation 490 * will work. Device-mode hibernation is not yet implemented. 491 */ 492 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 493 break; 494 default: 495 dev_dbg(dwc->dev, "No power optimization available\n"); 496 } 497 498 /* check if current dwc3 is on simulation board */ 499 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 500 dev_dbg(dwc->dev, "it is on FPGA board\n"); 501 dwc->is_fpga = true; 502 } 503 504 if(dwc->disable_scramble_quirk && !dwc->is_fpga) 505 WARN(true, 506 "disable_scramble cannot be used on non-FPGA builds\n"); 507 508 if (dwc->disable_scramble_quirk && dwc->is_fpga) 509 reg |= DWC3_GCTL_DISSCRAMBLE; 510 else 511 reg &= ~DWC3_GCTL_DISSCRAMBLE; 512 513 if (dwc->u2exit_lfps_quirk) 514 reg |= DWC3_GCTL_U2EXIT_LFPS; 515 516 /* 517 * WORKAROUND: DWC3 revisions <1.90a have a bug 518 * where the device can fail to connect at SuperSpeed 519 * and falls back to high-speed mode which causes 520 * the device to enter a Connect/Disconnect loop 521 */ 522 if (dwc->revision < DWC3_REVISION_190A) 523 reg |= DWC3_GCTL_U2RSTECN; 524 525 dwc3_core_num_eps(dwc); 526 527 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 528 529 ret = dwc3_alloc_scratch_buffers(dwc); 530 if (ret) 531 goto err0; 532 533 ret = dwc3_setup_scratch_buffers(dwc); 534 if (ret) 535 goto err1; 536 537 return 0; 538 539 err1: 540 dwc3_free_scratch_buffers(dwc); 541 542 err0: 543 return ret; 544 } 545 546 static void dwc3_core_exit(struct dwc3 *dwc) 547 { 548 dwc3_free_scratch_buffers(dwc); 549 } 550 551 static int dwc3_core_init_mode(struct dwc3 *dwc) 552 { 553 int ret; 554 555 switch (dwc->dr_mode) { 556 case USB_DR_MODE_PERIPHERAL: 557 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 558 ret = dwc3_gadget_init(dwc); 559 if (ret) { 560 dev_err(dev, "failed to initialize gadget\n"); 561 return ret; 562 } 563 break; 564 case USB_DR_MODE_HOST: 565 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 566 ret = dwc3_host_init(dwc); 567 if (ret) { 568 dev_err(dev, "failed to initialize host\n"); 569 return ret; 570 } 571 break; 572 case USB_DR_MODE_OTG: 573 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 574 ret = dwc3_host_init(dwc); 575 if (ret) { 576 dev_err(dev, "failed to initialize host\n"); 577 return ret; 578 } 579 580 ret = dwc3_gadget_init(dwc); 581 if (ret) { 582 dev_err(dev, "failed to initialize gadget\n"); 583 return ret; 584 } 585 break; 586 default: 587 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 588 return -EINVAL; 589 } 590 591 return 0; 592 } 593 594 static void dwc3_gadget_run(struct dwc3 *dwc) 595 { 596 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP); 597 mdelay(100); 598 } 599 600 static void dwc3_core_exit_mode(struct dwc3 *dwc) 601 { 602 switch (dwc->dr_mode) { 603 case USB_DR_MODE_PERIPHERAL: 604 dwc3_gadget_exit(dwc); 605 break; 606 case USB_DR_MODE_HOST: 607 dwc3_host_exit(dwc); 608 break; 609 case USB_DR_MODE_OTG: 610 dwc3_host_exit(dwc); 611 dwc3_gadget_exit(dwc); 612 break; 613 default: 614 /* do nothing */ 615 break; 616 } 617 618 /* 619 * switch back to peripheral mode 620 * This enables the phy to enter idle and then, if enabled, suspend. 621 */ 622 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 623 dwc3_gadget_run(dwc); 624 } 625 626 static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev, 627 struct dwc3 *dwc) 628 { 629 enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode; 630 u32 reg; 631 632 /* Set dwc3 usb2 phy config */ 633 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 634 635 switch (hsphy_mode) { 636 case USBPHY_INTERFACE_MODE_UTMI: 637 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 638 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 639 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 640 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 641 break; 642 case USBPHY_INTERFACE_MODE_UTMIW: 643 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 644 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 645 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 646 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 647 break; 648 default: 649 break; 650 } 651 652 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 653 } 654 655 #define DWC3_ALIGN_MASK (16 - 1) 656 657 /** 658 * dwc3_uboot_init - dwc3 core uboot initialization code 659 * @dwc3_dev: struct dwc3_device containing initialization data 660 * 661 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux 662 * kernel driver). Pointer to dwc3_device should be passed containing 663 * base address and other initialization data. Returns '0' on success and 664 * a negative value on failure. 665 * 666 * Generally called from board_usb_init() implemented in board file. 667 */ 668 int dwc3_uboot_init(struct dwc3_device *dwc3_dev) 669 { 670 struct dwc3 *dwc; 671 struct device *dev = NULL; 672 u8 lpm_nyet_threshold; 673 u8 tx_de_emphasis; 674 u8 hird_threshold; 675 676 int ret; 677 678 void *mem; 679 const void *blob = gd->fdt_blob; 680 int node; 681 682 mem = devm_kzalloc((struct udevice *)dev, 683 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 684 if (!mem) 685 return -ENOMEM; 686 687 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 688 dwc->mem = mem; 689 690 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base + 691 DWC3_GLOBALS_REGS_START); 692 693 /* default to highest possible threshold */ 694 lpm_nyet_threshold = 0xff; 695 696 /* default to -3.5dB de-emphasis */ 697 tx_de_emphasis = 1; 698 699 /* 700 * default to assert utmi_sleep_n and use maximum allowed HIRD 701 * threshold value of 0b1100 702 */ 703 hird_threshold = 12; 704 705 dwc->maximum_speed = dwc3_dev->maximum_speed; 706 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum; 707 if (dwc3_dev->lpm_nyet_threshold) 708 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold; 709 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend; 710 if (dwc3_dev->hird_threshold) 711 hird_threshold = dwc3_dev->hird_threshold; 712 713 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize; 714 dwc->dr_mode = dwc3_dev->dr_mode; 715 716 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk; 717 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk; 718 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk; 719 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk; 720 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk; 721 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk; 722 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk; 723 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk; 724 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk; 725 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; 726 727 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk; 728 if (dwc3_dev->tx_de_emphasis) 729 tx_de_emphasis = dwc3_dev->tx_de_emphasis; 730 731 /* default to superspeed if no maximum_speed passed */ 732 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 733 dwc->maximum_speed = USB_SPEED_SUPER; 734 735 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 736 dwc->tx_de_emphasis = tx_de_emphasis; 737 738 dwc->hird_threshold = hird_threshold 739 | (dwc->is_utmi_l1_suspend << 4); 740 741 dwc->index = dwc3_dev->index; 742 743 if (dwc3_dev->usb2_phyif_utmi_width) 744 dwc->usb2_phyif_utmi_width = dwc3_dev->usb2_phyif_utmi_width; 745 746 node = fdt_node_offset_by_compatible(blob, -1, 747 "rockchip,rk3399-xhci"); 748 if (node < 0) 749 debug("%s dwc3 node not found\n", __func__); 750 else 751 dwc->usb2_phyif_utmi_width = 752 fdtdec_get_int(blob, node, "snps,phyif-utmi-bits", -1); 753 754 dwc3_cache_hwparams(dwc); 755 756 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 757 if (ret) { 758 dev_err(dwc->dev, "failed to allocate event buffers\n"); 759 return -ENOMEM; 760 } 761 762 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 763 dwc->dr_mode = USB_DR_MODE_HOST; 764 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 765 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 766 767 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 768 dwc->dr_mode = USB_DR_MODE_OTG; 769 770 ret = dwc3_core_init(dwc); 771 if (ret) { 772 dev_err(dev, "failed to initialize core\n"); 773 goto err0; 774 } 775 776 dwc3_uboot_hsphy_mode(dwc3_dev, dwc); 777 778 ret = dwc3_event_buffers_setup(dwc); 779 if (ret) { 780 dev_err(dwc->dev, "failed to setup event buffers\n"); 781 goto err1; 782 } 783 784 ret = dwc3_core_init_mode(dwc); 785 if (ret) 786 goto err2; 787 788 list_add_tail(&dwc->list, &dwc3_list); 789 790 return 0; 791 792 err2: 793 dwc3_event_buffers_cleanup(dwc); 794 795 err1: 796 dwc3_core_exit(dwc); 797 798 err0: 799 dwc3_free_event_buffers(dwc); 800 801 return ret; 802 } 803 804 /** 805 * dwc3_uboot_exit - dwc3 core uboot cleanup code 806 * @index: index of this controller 807 * 808 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc 809 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller 810 * should be passed and should match with the index passed in 811 * dwc3_device during init. 812 * 813 * Generally called from board file. 814 */ 815 void dwc3_uboot_exit(int index) 816 { 817 struct dwc3 *dwc; 818 819 list_for_each_entry(dwc, &dwc3_list, list) { 820 if (dwc->index != index) 821 continue; 822 823 dwc3_core_exit_mode(dwc); 824 dwc3_event_buffers_cleanup(dwc); 825 dwc3_free_event_buffers(dwc); 826 dwc3_core_exit(dwc); 827 list_del(&dwc->list); 828 kfree(dwc->mem); 829 break; 830 } 831 } 832 833 /** 834 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt 835 * @index: index of this controller 836 * 837 * Invokes dwc3 gadget interrupts. 838 * 839 * Generally called from board file. 840 */ 841 void dwc3_uboot_handle_interrupt(int index) 842 { 843 struct dwc3 *dwc = NULL; 844 845 list_for_each_entry(dwc, &dwc3_list, list) { 846 if (dwc->index != index) 847 continue; 848 849 dwc3_gadget_uboot_handle_interrupt(dwc); 850 break; 851 } 852 } 853 854 MODULE_ALIAS("platform:dwc3"); 855 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 856 MODULE_LICENSE("GPL v2"); 857 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 858 859 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) 860 int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys) 861 { 862 int i, ret, count; 863 struct phy *usb_phys; 864 865 /* Return if no phy declared */ 866 if (!dev_read_prop(dev, "phys", NULL)) 867 return 0; 868 count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); 869 if (count <= 0) 870 return count; 871 872 usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), 873 GFP_KERNEL); 874 if (!usb_phys) 875 return -ENOMEM; 876 877 for (i = 0; i < count; i++) { 878 ret = generic_phy_get_by_index(dev, i, &usb_phys[i]); 879 if (ret && ret != -ENOENT) { 880 pr_err("Failed to get USB PHY%d for %s\n", 881 i, dev->name); 882 return ret; 883 } 884 } 885 886 for (i = 0; i < count; i++) { 887 ret = generic_phy_init(&usb_phys[i]); 888 if (ret) { 889 pr_err("Can't init USB PHY%d for %s\n", 890 i, dev->name); 891 goto phys_init_err; 892 } 893 } 894 895 for (i = 0; i < count; i++) { 896 ret = generic_phy_power_on(&usb_phys[i]); 897 if (ret) { 898 pr_err("Can't power USB PHY%d for %s\n", 899 i, dev->name); 900 goto phys_poweron_err; 901 } 902 } 903 904 *array = usb_phys; 905 *num_phys = count; 906 return 0; 907 908 phys_poweron_err: 909 for (i = count - 1; i >= 0; i--) 910 generic_phy_power_off(&usb_phys[i]); 911 912 for (i = 0; i < count; i++) 913 generic_phy_exit(&usb_phys[i]); 914 915 return ret; 916 917 phys_init_err: 918 for (; i >= 0; i--) 919 generic_phy_exit(&usb_phys[i]); 920 921 return ret; 922 } 923 924 int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys) 925 { 926 int i, ret; 927 928 for (i = 0; i < num_phys; i++) { 929 if (!generic_phy_valid(&usb_phys[i])) 930 continue; 931 932 ret = generic_phy_power_off(&usb_phys[i]); 933 ret |= generic_phy_exit(&usb_phys[i]); 934 if (ret) { 935 pr_err("Can't shutdown USB PHY%d for %s\n", 936 i, dev->name); 937 } 938 } 939 940 return 0; 941 } 942 #endif 943 944 #if CONFIG_IS_ENABLED(DM_USB) 945 void dwc3_of_parse(struct dwc3 *dwc) 946 { 947 const u8 *tmp; 948 struct udevice *dev = dwc->dev; 949 u8 lpm_nyet_threshold; 950 u8 tx_de_emphasis; 951 u8 hird_threshold; 952 953 /* default to highest possible threshold */ 954 lpm_nyet_threshold = 0xff; 955 956 /* default to -3.5dB de-emphasis */ 957 tx_de_emphasis = 1; 958 959 /* 960 * default to assert utmi_sleep_n and use maximum allowed HIRD 961 * threshold value of 0b1100 962 */ 963 hird_threshold = 12; 964 965 dwc->has_lpm_erratum = dev_read_bool(dev, 966 "snps,has-lpm-erratum"); 967 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1); 968 if (tmp) 969 lpm_nyet_threshold = *tmp; 970 971 dwc->is_utmi_l1_suspend = dev_read_bool(dev, 972 "snps,is-utmi-l1-suspend"); 973 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1); 974 if (tmp) 975 hird_threshold = *tmp; 976 977 dwc->disable_scramble_quirk = dev_read_bool(dev, 978 "snps,disable_scramble_quirk"); 979 dwc->u2exit_lfps_quirk = dev_read_bool(dev, 980 "snps,u2exit_lfps_quirk"); 981 dwc->u2ss_inp3_quirk = dev_read_bool(dev, 982 "snps,u2ss_inp3_quirk"); 983 dwc->req_p1p2p3_quirk = dev_read_bool(dev, 984 "snps,req_p1p2p3_quirk"); 985 dwc->del_p1p2p3_quirk = dev_read_bool(dev, 986 "snps,del_p1p2p3_quirk"); 987 dwc->del_phy_power_chg_quirk = dev_read_bool(dev, 988 "snps,del_phy_power_chg_quirk"); 989 dwc->lfps_filter_quirk = dev_read_bool(dev, 990 "snps,lfps_filter_quirk"); 991 dwc->rx_detect_poll_quirk = dev_read_bool(dev, 992 "snps,rx_detect_poll_quirk"); 993 dwc->dis_u3_susphy_quirk = dev_read_bool(dev, 994 "snps,dis_u3_susphy_quirk"); 995 dwc->dis_u2_susphy_quirk = dev_read_bool(dev, 996 "snps,dis_u2_susphy_quirk"); 997 dwc->tx_de_emphasis_quirk = dev_read_bool(dev, 998 "snps,tx_de_emphasis_quirk"); 999 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1); 1000 if (tmp) 1001 tx_de_emphasis = *tmp; 1002 1003 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1004 dwc->tx_de_emphasis = tx_de_emphasis; 1005 1006 dwc->hird_threshold = hird_threshold 1007 | (dwc->is_utmi_l1_suspend << 4); 1008 } 1009 1010 int dwc3_init(struct dwc3 *dwc) 1011 { 1012 int ret; 1013 1014 dwc3_cache_hwparams(dwc); 1015 1016 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1017 if (ret) { 1018 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1019 return -ENOMEM; 1020 } 1021 1022 ret = dwc3_core_init(dwc); 1023 if (ret) { 1024 dev_err(dev, "failed to initialize core\n"); 1025 goto core_fail; 1026 } 1027 1028 ret = dwc3_event_buffers_setup(dwc); 1029 if (ret) { 1030 dev_err(dwc->dev, "failed to setup event buffers\n"); 1031 goto event_fail; 1032 } 1033 1034 ret = dwc3_core_init_mode(dwc); 1035 if (ret) 1036 goto mode_fail; 1037 1038 return 0; 1039 1040 mode_fail: 1041 dwc3_event_buffers_cleanup(dwc); 1042 1043 event_fail: 1044 dwc3_core_exit(dwc); 1045 1046 core_fail: 1047 dwc3_free_event_buffers(dwc); 1048 1049 return ret; 1050 } 1051 1052 void dwc3_remove(struct dwc3 *dwc) 1053 { 1054 dwc3_core_exit_mode(dwc); 1055 dwc3_event_buffers_cleanup(dwc); 1056 dwc3_free_event_buffers(dwc); 1057 dwc3_core_exit(dwc); 1058 kfree(dwc->mem); 1059 } 1060 #endif 1061