1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported 10 * to uboot. 11 * 12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <common.h> 18 #include <malloc.h> 19 #include <fdtdec.h> 20 #include <dwc3-uboot.h> 21 #include <asm/dma-mapping.h> 22 #include <linux/ioport.h> 23 #include <dm.h> 24 25 #include <linux/usb/ch9.h> 26 #include <linux/usb/gadget.h> 27 28 #include "core.h" 29 #include "gadget.h" 30 #include "io.h" 31 32 #include "linux-compat.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 static LIST_HEAD(dwc3_list); 37 /* -------------------------------------------------------------------------- */ 38 39 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 40 { 41 u32 reg; 42 43 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 44 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 45 reg |= DWC3_GCTL_PRTCAPDIR(mode); 46 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 47 } 48 49 /** 50 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 51 * @dwc: pointer to our context structure 52 */ 53 static int dwc3_core_soft_reset(struct dwc3 *dwc) 54 { 55 u32 reg; 56 57 /* Before Resetting PHY, put Core in Reset */ 58 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 59 reg |= DWC3_GCTL_CORESOFTRESET; 60 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 61 62 /* Assert USB3 PHY reset */ 63 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 64 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 65 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 66 67 /* Assert USB2 PHY reset */ 68 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 69 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 70 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 71 72 mdelay(100); 73 74 /* Clear USB3 PHY reset */ 75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 76 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 78 79 /* Clear USB2 PHY reset */ 80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 81 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 83 84 mdelay(100); 85 86 /* After PHYs are stable we can take Core out of reset state */ 87 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 88 reg &= ~DWC3_GCTL_CORESOFTRESET; 89 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 90 91 return 0; 92 } 93 94 /** 95 * dwc3_free_one_event_buffer - Frees one event buffer 96 * @dwc: Pointer to our controller context structure 97 * @evt: Pointer to event buffer to be freed 98 */ 99 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 100 struct dwc3_event_buffer *evt) 101 { 102 dma_free_coherent(evt->buf); 103 } 104 105 /** 106 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 107 * @dwc: Pointer to our controller context structure 108 * @length: size of the event buffer 109 * 110 * Returns a pointer to the allocated event buffer structure on success 111 * otherwise ERR_PTR(errno). 112 */ 113 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 114 unsigned length) 115 { 116 struct dwc3_event_buffer *evt; 117 118 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt), 119 GFP_KERNEL); 120 if (!evt) 121 return ERR_PTR(-ENOMEM); 122 123 evt->dwc = dwc; 124 evt->length = length; 125 evt->buf = dma_alloc_coherent(length, 126 (unsigned long *)&evt->dma); 127 if (!evt->buf) 128 return ERR_PTR(-ENOMEM); 129 130 dwc3_flush_cache((uintptr_t)evt->buf, evt->length); 131 132 return evt; 133 } 134 135 /** 136 * dwc3_free_event_buffers - frees all allocated event buffers 137 * @dwc: Pointer to our controller context structure 138 */ 139 static void dwc3_free_event_buffers(struct dwc3 *dwc) 140 { 141 struct dwc3_event_buffer *evt; 142 int i; 143 144 for (i = 0; i < dwc->num_event_buffers; i++) { 145 evt = dwc->ev_buffs[i]; 146 if (evt) 147 dwc3_free_one_event_buffer(dwc, evt); 148 } 149 } 150 151 /** 152 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 153 * @dwc: pointer to our controller context structure 154 * @length: size of event buffer 155 * 156 * Returns 0 on success otherwise negative errno. In the error case, dwc 157 * may contain some buffers allocated but not all which were requested. 158 */ 159 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 160 { 161 int num; 162 int i; 163 164 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 165 dwc->num_event_buffers = num; 166 167 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE, 168 sizeof(*dwc->ev_buffs) * num); 169 if (!dwc->ev_buffs) 170 return -ENOMEM; 171 172 for (i = 0; i < num; i++) { 173 struct dwc3_event_buffer *evt; 174 175 evt = dwc3_alloc_one_event_buffer(dwc, length); 176 if (IS_ERR(evt)) { 177 dev_err(dwc->dev, "can't allocate event buffer\n"); 178 return PTR_ERR(evt); 179 } 180 dwc->ev_buffs[i] = evt; 181 } 182 183 return 0; 184 } 185 186 /** 187 * dwc3_event_buffers_setup - setup our allocated event buffers 188 * @dwc: pointer to our controller context structure 189 * 190 * Returns 0 on success otherwise negative errno. 191 */ 192 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 193 { 194 struct dwc3_event_buffer *evt; 195 int n; 196 197 for (n = 0; n < dwc->num_event_buffers; n++) { 198 evt = dwc->ev_buffs[n]; 199 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 200 evt->buf, (unsigned long long) evt->dma, 201 evt->length); 202 203 evt->lpos = 0; 204 205 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 206 lower_32_bits(evt->dma)); 207 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 208 upper_32_bits(evt->dma)); 209 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 210 DWC3_GEVNTSIZ_SIZE(evt->length)); 211 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 212 } 213 214 return 0; 215 } 216 217 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 218 { 219 struct dwc3_event_buffer *evt; 220 int n; 221 222 for (n = 0; n < dwc->num_event_buffers; n++) { 223 evt = dwc->ev_buffs[n]; 224 225 evt->lpos = 0; 226 227 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 228 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 229 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 230 | DWC3_GEVNTSIZ_SIZE(0)); 231 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 232 } 233 } 234 235 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 236 { 237 if (!dwc->has_hibernation) 238 return 0; 239 240 if (!dwc->nr_scratch) 241 return 0; 242 243 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 244 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 245 if (!dwc->scratchbuf) 246 return -ENOMEM; 247 248 return 0; 249 } 250 251 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 252 { 253 dma_addr_t scratch_addr; 254 u32 param; 255 int ret; 256 257 if (!dwc->has_hibernation) 258 return 0; 259 260 if (!dwc->nr_scratch) 261 return 0; 262 263 scratch_addr = dma_map_single(dwc->scratchbuf, 264 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 265 DMA_BIDIRECTIONAL); 266 if (dma_mapping_error(dwc->dev, scratch_addr)) { 267 dev_err(dwc->dev, "failed to map scratch buffer\n"); 268 ret = -EFAULT; 269 goto err0; 270 } 271 272 dwc->scratch_addr = scratch_addr; 273 274 param = lower_32_bits(scratch_addr); 275 276 ret = dwc3_send_gadget_generic_command(dwc, 277 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 278 if (ret < 0) 279 goto err1; 280 281 param = upper_32_bits(scratch_addr); 282 283 ret = dwc3_send_gadget_generic_command(dwc, 284 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 285 if (ret < 0) 286 goto err1; 287 288 return 0; 289 290 err1: 291 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 292 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 293 294 err0: 295 return ret; 296 } 297 298 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 299 { 300 if (!dwc->has_hibernation) 301 return; 302 303 if (!dwc->nr_scratch) 304 return; 305 306 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 307 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 308 kfree(dwc->scratchbuf); 309 } 310 311 static void dwc3_core_num_eps(struct dwc3 *dwc) 312 { 313 struct dwc3_hwparams *parms = &dwc->hwparams; 314 315 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 316 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 317 318 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", 319 dwc->num_in_eps, dwc->num_out_eps); 320 } 321 322 static void dwc3_cache_hwparams(struct dwc3 *dwc) 323 { 324 struct dwc3_hwparams *parms = &dwc->hwparams; 325 326 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 327 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 328 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 329 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 330 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 331 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 332 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 333 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 334 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 335 } 336 337 /** 338 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 339 * @dwc: Pointer to our controller context structure 340 */ 341 static void dwc3_phy_setup(struct dwc3 *dwc) 342 { 343 u32 reg; 344 345 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 346 347 /* 348 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 349 * to '0' during coreConsultant configuration. So default value 350 * will be '0' when the core is reset. Application needs to set it 351 * to '1' after the core initialization is completed. 352 */ 353 if (dwc->revision > DWC3_REVISION_194A) 354 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 355 356 if (dwc->u2ss_inp3_quirk) 357 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 358 359 if (dwc->req_p1p2p3_quirk) 360 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 361 362 if (dwc->del_p1p2p3_quirk) 363 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 364 365 if (dwc->del_phy_power_chg_quirk) 366 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 367 368 if (dwc->lfps_filter_quirk) 369 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 370 371 if (dwc->rx_detect_poll_quirk) 372 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 373 374 if (dwc->tx_de_emphasis_quirk) 375 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 376 377 if (dwc->dis_u3_susphy_quirk) 378 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 379 380 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 381 382 mdelay(100); 383 384 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 385 386 /* 387 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 388 * '0' during coreConsultant configuration. So default value will 389 * be '0' when the core is reset. Application needs to set it to 390 * '1' after the core initialization is completed. 391 */ 392 if (dwc->revision > DWC3_REVISION_194A) 393 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 394 395 if (dwc->dis_u2_susphy_quirk) 396 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 397 398 if (dwc->usb2_phyif_utmi_width == 16) { 399 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 400 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; 401 reg |= DWC3_GUSB2PHYCFG_PHYIF_16BIT; 402 } 403 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 404 405 mdelay(100); 406 } 407 408 /** 409 * dwc3_core_init - Low-level initialization of DWC3 Core 410 * @dwc: Pointer to our controller context structure 411 * 412 * Returns 0 on success otherwise negative errno. 413 */ 414 static int dwc3_core_init(struct dwc3 *dwc) 415 { 416 unsigned long timeout; 417 u32 hwparams4 = dwc->hwparams.hwparams4; 418 u32 reg; 419 int ret; 420 421 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 422 /* This should read as U3 followed by revision number */ 423 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 424 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 425 ret = -ENODEV; 426 goto err0; 427 } 428 dwc->revision = reg; 429 430 /* Handle USB2.0-only core configuration */ 431 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 432 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 433 if (dwc->maximum_speed == USB_SPEED_SUPER) 434 dwc->maximum_speed = USB_SPEED_HIGH; 435 } 436 437 /* issue device SoftReset too */ 438 timeout = 5000; 439 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 440 while (timeout--) { 441 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 442 if (!(reg & DWC3_DCTL_CSFTRST)) 443 break; 444 }; 445 446 if (!timeout) { 447 dev_err(dwc->dev, "Reset Timed Out\n"); 448 ret = -ETIMEDOUT; 449 goto err0; 450 } 451 452 ret = dwc3_core_soft_reset(dwc); 453 if (ret) 454 goto err0; 455 456 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 457 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 458 459 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 460 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 461 /** 462 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 463 * issue which would cause xHCI compliance tests to fail. 464 * 465 * Because of that we cannot enable clock gating on such 466 * configurations. 467 * 468 * Refers to: 469 * 470 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 471 * SOF/ITP Mode Used 472 */ 473 if ((dwc->dr_mode == USB_DR_MODE_HOST || 474 dwc->dr_mode == USB_DR_MODE_OTG) && 475 (dwc->revision >= DWC3_REVISION_210A && 476 dwc->revision <= DWC3_REVISION_250A)) 477 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 478 else 479 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 480 break; 481 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 482 /* enable hibernation here */ 483 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 484 485 /* 486 * REVISIT Enabling this bit so that host-mode hibernation 487 * will work. Device-mode hibernation is not yet implemented. 488 */ 489 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 490 break; 491 default: 492 dev_dbg(dwc->dev, "No power optimization available\n"); 493 } 494 495 /* check if current dwc3 is on simulation board */ 496 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 497 dev_dbg(dwc->dev, "it is on FPGA board\n"); 498 dwc->is_fpga = true; 499 } 500 501 if(dwc->disable_scramble_quirk && !dwc->is_fpga) 502 WARN(true, 503 "disable_scramble cannot be used on non-FPGA builds\n"); 504 505 if (dwc->disable_scramble_quirk && dwc->is_fpga) 506 reg |= DWC3_GCTL_DISSCRAMBLE; 507 else 508 reg &= ~DWC3_GCTL_DISSCRAMBLE; 509 510 if (dwc->u2exit_lfps_quirk) 511 reg |= DWC3_GCTL_U2EXIT_LFPS; 512 513 /* 514 * WORKAROUND: DWC3 revisions <1.90a have a bug 515 * where the device can fail to connect at SuperSpeed 516 * and falls back to high-speed mode which causes 517 * the device to enter a Connect/Disconnect loop 518 */ 519 if (dwc->revision < DWC3_REVISION_190A) 520 reg |= DWC3_GCTL_U2RSTECN; 521 522 dwc3_core_num_eps(dwc); 523 524 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 525 526 dwc3_phy_setup(dwc); 527 528 ret = dwc3_alloc_scratch_buffers(dwc); 529 if (ret) 530 goto err0; 531 532 ret = dwc3_setup_scratch_buffers(dwc); 533 if (ret) 534 goto err1; 535 536 return 0; 537 538 err1: 539 dwc3_free_scratch_buffers(dwc); 540 541 err0: 542 return ret; 543 } 544 545 static void dwc3_core_exit(struct dwc3 *dwc) 546 { 547 dwc3_free_scratch_buffers(dwc); 548 } 549 550 static int dwc3_core_init_mode(struct dwc3 *dwc) 551 { 552 int ret; 553 554 switch (dwc->dr_mode) { 555 case USB_DR_MODE_PERIPHERAL: 556 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 557 ret = dwc3_gadget_init(dwc); 558 if (ret) { 559 dev_err(dev, "failed to initialize gadget\n"); 560 return ret; 561 } 562 break; 563 case USB_DR_MODE_HOST: 564 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 565 ret = dwc3_host_init(dwc); 566 if (ret) { 567 dev_err(dev, "failed to initialize host\n"); 568 return ret; 569 } 570 break; 571 case USB_DR_MODE_OTG: 572 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 573 ret = dwc3_host_init(dwc); 574 if (ret) { 575 dev_err(dev, "failed to initialize host\n"); 576 return ret; 577 } 578 579 ret = dwc3_gadget_init(dwc); 580 if (ret) { 581 dev_err(dev, "failed to initialize gadget\n"); 582 return ret; 583 } 584 break; 585 default: 586 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 587 return -EINVAL; 588 } 589 590 return 0; 591 } 592 593 static void dwc3_core_exit_mode(struct dwc3 *dwc) 594 { 595 switch (dwc->dr_mode) { 596 case USB_DR_MODE_PERIPHERAL: 597 dwc3_gadget_exit(dwc); 598 break; 599 case USB_DR_MODE_HOST: 600 dwc3_host_exit(dwc); 601 break; 602 case USB_DR_MODE_OTG: 603 dwc3_host_exit(dwc); 604 dwc3_gadget_exit(dwc); 605 break; 606 default: 607 /* do nothing */ 608 break; 609 } 610 } 611 612 #define DWC3_ALIGN_MASK (16 - 1) 613 614 /** 615 * dwc3_uboot_init - dwc3 core uboot initialization code 616 * @dwc3_dev: struct dwc3_device containing initialization data 617 * 618 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux 619 * kernel driver). Pointer to dwc3_device should be passed containing 620 * base address and other initialization data. Returns '0' on success and 621 * a negative value on failure. 622 * 623 * Generally called from board_usb_init() implemented in board file. 624 */ 625 int dwc3_uboot_init(struct dwc3_device *dwc3_dev) 626 { 627 struct dwc3 *dwc; 628 struct device *dev = NULL; 629 u8 lpm_nyet_threshold; 630 u8 tx_de_emphasis; 631 u8 hird_threshold; 632 633 int ret; 634 635 void *mem; 636 const void *blob = gd->fdt_blob; 637 int node; 638 639 mem = devm_kzalloc((struct udevice *)dev, 640 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 641 if (!mem) 642 return -ENOMEM; 643 644 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 645 dwc->mem = mem; 646 647 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base + 648 DWC3_GLOBALS_REGS_START); 649 650 /* default to highest possible threshold */ 651 lpm_nyet_threshold = 0xff; 652 653 /* default to -3.5dB de-emphasis */ 654 tx_de_emphasis = 1; 655 656 /* 657 * default to assert utmi_sleep_n and use maximum allowed HIRD 658 * threshold value of 0b1100 659 */ 660 hird_threshold = 12; 661 662 dwc->maximum_speed = dwc3_dev->maximum_speed; 663 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum; 664 if (dwc3_dev->lpm_nyet_threshold) 665 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold; 666 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend; 667 if (dwc3_dev->hird_threshold) 668 hird_threshold = dwc3_dev->hird_threshold; 669 670 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize; 671 dwc->dr_mode = dwc3_dev->dr_mode; 672 673 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk; 674 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk; 675 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk; 676 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk; 677 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk; 678 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk; 679 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk; 680 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk; 681 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk; 682 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; 683 684 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk; 685 if (dwc3_dev->tx_de_emphasis) 686 tx_de_emphasis = dwc3_dev->tx_de_emphasis; 687 688 /* default to superspeed if no maximum_speed passed */ 689 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 690 dwc->maximum_speed = USB_SPEED_SUPER; 691 692 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 693 dwc->tx_de_emphasis = tx_de_emphasis; 694 695 dwc->hird_threshold = hird_threshold 696 | (dwc->is_utmi_l1_suspend << 4); 697 698 dwc->index = dwc3_dev->index; 699 700 if (dwc3_dev->usb2_phyif_utmi_width) 701 dwc->usb2_phyif_utmi_width = dwc3_dev->usb2_phyif_utmi_width; 702 703 node = fdt_node_offset_by_compatible(blob, -1, 704 "rockchip,rk3399-xhci"); 705 if (node < 0) 706 debug("%s dwc3 node not found\n", __func__); 707 else 708 dwc->usb2_phyif_utmi_width = 709 fdtdec_get_int(blob, node, "snps,phyif-utmi-bits", -1); 710 711 dwc3_cache_hwparams(dwc); 712 713 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 714 if (ret) { 715 dev_err(dwc->dev, "failed to allocate event buffers\n"); 716 return -ENOMEM; 717 } 718 719 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 720 dwc->dr_mode = USB_DR_MODE_HOST; 721 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 722 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 723 724 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 725 dwc->dr_mode = USB_DR_MODE_OTG; 726 727 ret = dwc3_core_init(dwc); 728 if (ret) { 729 dev_err(dev, "failed to initialize core\n"); 730 goto err0; 731 } 732 733 ret = dwc3_event_buffers_setup(dwc); 734 if (ret) { 735 dev_err(dwc->dev, "failed to setup event buffers\n"); 736 goto err1; 737 } 738 739 ret = dwc3_core_init_mode(dwc); 740 if (ret) 741 goto err2; 742 743 list_add_tail(&dwc->list, &dwc3_list); 744 745 return 0; 746 747 err2: 748 dwc3_event_buffers_cleanup(dwc); 749 750 err1: 751 dwc3_core_exit(dwc); 752 753 err0: 754 dwc3_free_event_buffers(dwc); 755 756 return ret; 757 } 758 759 /** 760 * dwc3_uboot_exit - dwc3 core uboot cleanup code 761 * @index: index of this controller 762 * 763 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc 764 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller 765 * should be passed and should match with the index passed in 766 * dwc3_device during init. 767 * 768 * Generally called from board file. 769 */ 770 void dwc3_uboot_exit(int index) 771 { 772 struct dwc3 *dwc; 773 774 list_for_each_entry(dwc, &dwc3_list, list) { 775 if (dwc->index != index) 776 continue; 777 778 dwc3_core_exit_mode(dwc); 779 dwc3_event_buffers_cleanup(dwc); 780 dwc3_free_event_buffers(dwc); 781 dwc3_core_exit(dwc); 782 list_del(&dwc->list); 783 kfree(dwc->mem); 784 break; 785 } 786 } 787 788 /** 789 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt 790 * @index: index of this controller 791 * 792 * Invokes dwc3 gadget interrupts. 793 * 794 * Generally called from board file. 795 */ 796 void dwc3_uboot_handle_interrupt(int index) 797 { 798 struct dwc3 *dwc = NULL; 799 800 list_for_each_entry(dwc, &dwc3_list, list) { 801 if (dwc->index != index) 802 continue; 803 804 dwc3_gadget_uboot_handle_interrupt(dwc); 805 break; 806 } 807 } 808 809 MODULE_ALIAS("platform:dwc3"); 810 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 811 MODULE_LICENSE("GPL v2"); 812 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 813 814 #ifdef CONFIG_DM_USB 815 816 int dwc3_init(struct dwc3 *dwc) 817 { 818 int ret; 819 820 dwc3_cache_hwparams(dwc); 821 822 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 823 if (ret) { 824 dev_err(dwc->dev, "failed to allocate event buffers\n"); 825 return -ENOMEM; 826 } 827 828 ret = dwc3_core_init(dwc); 829 if (ret) { 830 dev_err(dev, "failed to initialize core\n"); 831 goto core_fail; 832 } 833 834 ret = dwc3_event_buffers_setup(dwc); 835 if (ret) { 836 dev_err(dwc->dev, "failed to setup event buffers\n"); 837 goto event_fail; 838 } 839 840 ret = dwc3_core_init_mode(dwc); 841 if (ret) 842 goto mode_fail; 843 844 return 0; 845 846 mode_fail: 847 dwc3_event_buffers_cleanup(dwc); 848 849 event_fail: 850 dwc3_core_exit(dwc); 851 852 core_fail: 853 dwc3_free_event_buffers(dwc); 854 855 return ret; 856 } 857 858 void dwc3_remove(struct dwc3 *dwc) 859 { 860 dwc3_core_exit_mode(dwc); 861 dwc3_event_buffers_cleanup(dwc); 862 dwc3_free_event_buffers(dwc); 863 dwc3_core_exit(dwc); 864 kfree(dwc->mem); 865 } 866 867 #endif 868