1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported 10 * to uboot. 11 * 12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <common.h> 18 #include <malloc.h> 19 #include <fdtdec.h> 20 #include <dwc3-uboot.h> 21 #include <asm/dma-mapping.h> 22 #include <linux/ioport.h> 23 #include <dm.h> 24 #include <generic-phy.h> 25 #include <linux/usb/ch9.h> 26 #include <linux/usb/gadget.h> 27 28 #include "core.h" 29 #include "gadget.h" 30 #include "io.h" 31 32 #include "linux-compat.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 static LIST_HEAD(dwc3_list); 37 /* -------------------------------------------------------------------------- */ 38 39 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 40 { 41 u32 reg; 42 43 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 44 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 45 reg |= DWC3_GCTL_PRTCAPDIR(mode); 46 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 47 } 48 49 /** 50 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 51 * @dwc: pointer to our context structure 52 */ 53 static int dwc3_core_soft_reset(struct dwc3 *dwc) 54 { 55 u32 reg; 56 57 /* Before Resetting PHY, put Core in Reset */ 58 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 59 reg |= DWC3_GCTL_CORESOFTRESET; 60 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 61 62 /* Assert USB3 PHY reset */ 63 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 64 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 65 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 66 67 /* Assert USB2 PHY reset */ 68 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 69 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 70 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 71 72 mdelay(100); 73 74 /* Clear USB3 PHY reset */ 75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 76 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 78 79 /* Clear USB2 PHY reset */ 80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 81 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 83 84 mdelay(100); 85 86 /* After PHYs are stable we can take Core out of reset state */ 87 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 88 reg &= ~DWC3_GCTL_CORESOFTRESET; 89 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 90 91 return 0; 92 } 93 94 /** 95 * dwc3_free_one_event_buffer - Frees one event buffer 96 * @dwc: Pointer to our controller context structure 97 * @evt: Pointer to event buffer to be freed 98 */ 99 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 100 struct dwc3_event_buffer *evt) 101 { 102 dma_free_coherent(evt->buf); 103 } 104 105 /** 106 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 107 * @dwc: Pointer to our controller context structure 108 * @length: size of the event buffer 109 * 110 * Returns a pointer to the allocated event buffer structure on success 111 * otherwise ERR_PTR(errno). 112 */ 113 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 114 unsigned length) 115 { 116 struct dwc3_event_buffer *evt; 117 118 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt), 119 GFP_KERNEL); 120 if (!evt) 121 return ERR_PTR(-ENOMEM); 122 123 evt->dwc = dwc; 124 evt->length = length; 125 evt->buf = dma_alloc_coherent(length, 126 (unsigned long *)&evt->dma); 127 if (!evt->buf) 128 return ERR_PTR(-ENOMEM); 129 130 dwc3_flush_cache((uintptr_t)evt->buf, evt->length); 131 132 return evt; 133 } 134 135 /** 136 * dwc3_free_event_buffers - frees all allocated event buffers 137 * @dwc: Pointer to our controller context structure 138 */ 139 static void dwc3_free_event_buffers(struct dwc3 *dwc) 140 { 141 struct dwc3_event_buffer *evt; 142 int i; 143 144 for (i = 0; i < dwc->num_event_buffers; i++) { 145 evt = dwc->ev_buffs[i]; 146 if (evt) 147 dwc3_free_one_event_buffer(dwc, evt); 148 } 149 } 150 151 /** 152 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 153 * @dwc: pointer to our controller context structure 154 * @length: size of event buffer 155 * 156 * Returns 0 on success otherwise negative errno. In the error case, dwc 157 * may contain some buffers allocated but not all which were requested. 158 */ 159 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 160 { 161 int num; 162 int i; 163 164 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 165 dwc->num_event_buffers = num; 166 167 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE, 168 sizeof(*dwc->ev_buffs) * num); 169 if (!dwc->ev_buffs) 170 return -ENOMEM; 171 172 for (i = 0; i < num; i++) { 173 struct dwc3_event_buffer *evt; 174 175 evt = dwc3_alloc_one_event_buffer(dwc, length); 176 if (IS_ERR(evt)) { 177 dev_err(dwc->dev, "can't allocate event buffer\n"); 178 return PTR_ERR(evt); 179 } 180 dwc->ev_buffs[i] = evt; 181 } 182 183 return 0; 184 } 185 186 /** 187 * dwc3_event_buffers_setup - setup our allocated event buffers 188 * @dwc: pointer to our controller context structure 189 * 190 * Returns 0 on success otherwise negative errno. 191 */ 192 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 193 { 194 struct dwc3_event_buffer *evt; 195 int n; 196 197 for (n = 0; n < dwc->num_event_buffers; n++) { 198 evt = dwc->ev_buffs[n]; 199 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 200 evt->buf, (unsigned long long) evt->dma, 201 evt->length); 202 203 evt->lpos = 0; 204 205 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 206 lower_32_bits(evt->dma)); 207 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 208 upper_32_bits(evt->dma)); 209 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 210 DWC3_GEVNTSIZ_SIZE(evt->length)); 211 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 212 } 213 214 return 0; 215 } 216 217 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 218 { 219 struct dwc3_event_buffer *evt; 220 int n; 221 222 for (n = 0; n < dwc->num_event_buffers; n++) { 223 evt = dwc->ev_buffs[n]; 224 225 evt->lpos = 0; 226 227 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 228 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 229 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 230 | DWC3_GEVNTSIZ_SIZE(0)); 231 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 232 } 233 } 234 235 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 236 { 237 if (!dwc->has_hibernation) 238 return 0; 239 240 if (!dwc->nr_scratch) 241 return 0; 242 243 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 244 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 245 if (!dwc->scratchbuf) 246 return -ENOMEM; 247 248 return 0; 249 } 250 251 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 252 { 253 dma_addr_t scratch_addr; 254 u32 param; 255 int ret; 256 257 if (!dwc->has_hibernation) 258 return 0; 259 260 if (!dwc->nr_scratch) 261 return 0; 262 263 scratch_addr = dma_map_single(dwc->scratchbuf, 264 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 265 DMA_BIDIRECTIONAL); 266 if (dma_mapping_error(dwc->dev, scratch_addr)) { 267 dev_err(dwc->dev, "failed to map scratch buffer\n"); 268 ret = -EFAULT; 269 goto err0; 270 } 271 272 dwc->scratch_addr = scratch_addr; 273 274 param = lower_32_bits(scratch_addr); 275 276 ret = dwc3_send_gadget_generic_command(dwc, 277 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 278 if (ret < 0) 279 goto err1; 280 281 param = upper_32_bits(scratch_addr); 282 283 ret = dwc3_send_gadget_generic_command(dwc, 284 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 285 if (ret < 0) 286 goto err1; 287 288 return 0; 289 290 err1: 291 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 292 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 293 294 err0: 295 return ret; 296 } 297 298 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 299 { 300 if (!dwc->has_hibernation) 301 return; 302 303 if (!dwc->nr_scratch) 304 return; 305 306 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 307 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 308 kfree(dwc->scratchbuf); 309 } 310 311 static void dwc3_core_num_eps(struct dwc3 *dwc) 312 { 313 struct dwc3_hwparams *parms = &dwc->hwparams; 314 315 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 316 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 317 318 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", 319 dwc->num_in_eps, dwc->num_out_eps); 320 } 321 322 static void dwc3_cache_hwparams(struct dwc3 *dwc) 323 { 324 struct dwc3_hwparams *parms = &dwc->hwparams; 325 326 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 327 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 328 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 329 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 330 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 331 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 332 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 333 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 334 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 335 } 336 337 /** 338 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 339 * @dwc: Pointer to our controller context structure 340 */ 341 static void dwc3_phy_setup(struct dwc3 *dwc) 342 { 343 u32 reg; 344 345 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 346 347 /* 348 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 349 * to '0' during coreConsultant configuration. So default value 350 * will be '0' when the core is reset. Application needs to set it 351 * to '1' after the core initialization is completed. 352 */ 353 if (dwc->revision > DWC3_REVISION_194A) 354 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 355 356 if (dwc->u2ss_inp3_quirk) 357 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 358 359 if (dwc->req_p1p2p3_quirk) 360 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 361 362 if (dwc->del_p1p2p3_quirk) 363 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 364 365 if (dwc->del_phy_power_chg_quirk) 366 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 367 368 if (dwc->lfps_filter_quirk) 369 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 370 371 if (dwc->rx_detect_poll_quirk) 372 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 373 374 if (dwc->tx_de_emphasis_quirk) 375 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 376 377 if (dwc->dis_u3_susphy_quirk) 378 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 379 380 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 381 382 mdelay(100); 383 384 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 385 386 /* 387 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 388 * '0' during coreConsultant configuration. So default value will 389 * be '0' when the core is reset. Application needs to set it to 390 * '1' after the core initialization is completed. 391 */ 392 if (dwc->revision > DWC3_REVISION_194A) 393 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 394 395 if (dwc->dis_u2_susphy_quirk) 396 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 397 398 if (dwc->usb2_phyif_utmi_width == 16) { 399 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 400 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; 401 reg |= DWC3_GUSB2PHYCFG_PHYIF_16BIT; 402 } 403 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 404 405 mdelay(100); 406 } 407 408 /** 409 * dwc3_core_init - Low-level initialization of DWC3 Core 410 * @dwc: Pointer to our controller context structure 411 * 412 * Returns 0 on success otherwise negative errno. 413 */ 414 static int dwc3_core_init(struct dwc3 *dwc) 415 { 416 unsigned long timeout; 417 u32 hwparams4 = dwc->hwparams.hwparams4; 418 u32 reg; 419 int ret; 420 421 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 422 /* This should read as U3 followed by revision number */ 423 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 424 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 425 ret = -ENODEV; 426 goto err0; 427 } 428 dwc->revision = reg; 429 430 /* Handle USB2.0-only core configuration */ 431 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 432 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 433 if (dwc->maximum_speed == USB_SPEED_SUPER) 434 dwc->maximum_speed = USB_SPEED_HIGH; 435 } 436 437 /* issue device SoftReset too */ 438 timeout = 5000; 439 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 440 while (timeout--) { 441 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 442 if (!(reg & DWC3_DCTL_CSFTRST)) 443 break; 444 }; 445 446 if (!timeout) { 447 dev_err(dwc->dev, "Reset Timed Out\n"); 448 ret = -ETIMEDOUT; 449 goto err0; 450 } 451 452 dwc3_phy_setup(dwc); 453 454 ret = dwc3_core_soft_reset(dwc); 455 if (ret) 456 goto err0; 457 458 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 459 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 460 461 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 462 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 463 /** 464 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 465 * issue which would cause xHCI compliance tests to fail. 466 * 467 * Because of that we cannot enable clock gating on such 468 * configurations. 469 * 470 * Refers to: 471 * 472 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 473 * SOF/ITP Mode Used 474 */ 475 if ((dwc->dr_mode == USB_DR_MODE_HOST || 476 dwc->dr_mode == USB_DR_MODE_OTG) && 477 (dwc->revision >= DWC3_REVISION_210A && 478 dwc->revision <= DWC3_REVISION_250A)) 479 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 480 else 481 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 482 break; 483 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 484 /* enable hibernation here */ 485 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 486 487 /* 488 * REVISIT Enabling this bit so that host-mode hibernation 489 * will work. Device-mode hibernation is not yet implemented. 490 */ 491 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 492 break; 493 default: 494 dev_dbg(dwc->dev, "No power optimization available\n"); 495 } 496 497 /* check if current dwc3 is on simulation board */ 498 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 499 dev_dbg(dwc->dev, "it is on FPGA board\n"); 500 dwc->is_fpga = true; 501 } 502 503 if(dwc->disable_scramble_quirk && !dwc->is_fpga) 504 WARN(true, 505 "disable_scramble cannot be used on non-FPGA builds\n"); 506 507 if (dwc->disable_scramble_quirk && dwc->is_fpga) 508 reg |= DWC3_GCTL_DISSCRAMBLE; 509 else 510 reg &= ~DWC3_GCTL_DISSCRAMBLE; 511 512 if (dwc->u2exit_lfps_quirk) 513 reg |= DWC3_GCTL_U2EXIT_LFPS; 514 515 /* 516 * WORKAROUND: DWC3 revisions <1.90a have a bug 517 * where the device can fail to connect at SuperSpeed 518 * and falls back to high-speed mode which causes 519 * the device to enter a Connect/Disconnect loop 520 */ 521 if (dwc->revision < DWC3_REVISION_190A) 522 reg |= DWC3_GCTL_U2RSTECN; 523 524 dwc3_core_num_eps(dwc); 525 526 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 527 528 ret = dwc3_alloc_scratch_buffers(dwc); 529 if (ret) 530 goto err0; 531 532 ret = dwc3_setup_scratch_buffers(dwc); 533 if (ret) 534 goto err1; 535 536 return 0; 537 538 err1: 539 dwc3_free_scratch_buffers(dwc); 540 541 err0: 542 return ret; 543 } 544 545 static void dwc3_core_exit(struct dwc3 *dwc) 546 { 547 dwc3_free_scratch_buffers(dwc); 548 } 549 550 static int dwc3_core_init_mode(struct dwc3 *dwc) 551 { 552 int ret; 553 554 switch (dwc->dr_mode) { 555 case USB_DR_MODE_PERIPHERAL: 556 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 557 ret = dwc3_gadget_init(dwc); 558 if (ret) { 559 dev_err(dev, "failed to initialize gadget\n"); 560 return ret; 561 } 562 break; 563 case USB_DR_MODE_HOST: 564 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 565 ret = dwc3_host_init(dwc); 566 if (ret) { 567 dev_err(dev, "failed to initialize host\n"); 568 return ret; 569 } 570 break; 571 case USB_DR_MODE_OTG: 572 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 573 ret = dwc3_host_init(dwc); 574 if (ret) { 575 dev_err(dev, "failed to initialize host\n"); 576 return ret; 577 } 578 579 ret = dwc3_gadget_init(dwc); 580 if (ret) { 581 dev_err(dev, "failed to initialize gadget\n"); 582 return ret; 583 } 584 break; 585 default: 586 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 587 return -EINVAL; 588 } 589 590 return 0; 591 } 592 593 static void dwc3_gadget_run(struct dwc3 *dwc) 594 { 595 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP); 596 mdelay(100); 597 } 598 599 static void dwc3_core_exit_mode(struct dwc3 *dwc) 600 { 601 switch (dwc->dr_mode) { 602 case USB_DR_MODE_PERIPHERAL: 603 dwc3_gadget_exit(dwc); 604 break; 605 case USB_DR_MODE_HOST: 606 dwc3_host_exit(dwc); 607 break; 608 case USB_DR_MODE_OTG: 609 dwc3_host_exit(dwc); 610 dwc3_gadget_exit(dwc); 611 break; 612 default: 613 /* do nothing */ 614 break; 615 } 616 617 /* 618 * switch back to peripheral mode 619 * This enables the phy to enter idle and then, if enabled, suspend. 620 */ 621 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 622 dwc3_gadget_run(dwc); 623 } 624 625 static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev, 626 struct dwc3 *dwc) 627 { 628 enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode; 629 u32 reg; 630 631 /* Set dwc3 usb2 phy config */ 632 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 633 reg |= DWC3_GUSB2PHYCFG_PHYIF; 634 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 635 636 switch (hsphy_mode) { 637 case USBPHY_INTERFACE_MODE_UTMI: 638 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; 639 break; 640 case USBPHY_INTERFACE_MODE_UTMIW: 641 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; 642 break; 643 default: 644 break; 645 } 646 647 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 648 } 649 650 #define DWC3_ALIGN_MASK (16 - 1) 651 652 /** 653 * dwc3_uboot_init - dwc3 core uboot initialization code 654 * @dwc3_dev: struct dwc3_device containing initialization data 655 * 656 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux 657 * kernel driver). Pointer to dwc3_device should be passed containing 658 * base address and other initialization data. Returns '0' on success and 659 * a negative value on failure. 660 * 661 * Generally called from board_usb_init() implemented in board file. 662 */ 663 int dwc3_uboot_init(struct dwc3_device *dwc3_dev) 664 { 665 struct dwc3 *dwc; 666 struct device *dev = NULL; 667 u8 lpm_nyet_threshold; 668 u8 tx_de_emphasis; 669 u8 hird_threshold; 670 671 int ret; 672 673 void *mem; 674 const void *blob = gd->fdt_blob; 675 int node; 676 677 mem = devm_kzalloc((struct udevice *)dev, 678 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 679 if (!mem) 680 return -ENOMEM; 681 682 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 683 dwc->mem = mem; 684 685 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base + 686 DWC3_GLOBALS_REGS_START); 687 688 /* default to highest possible threshold */ 689 lpm_nyet_threshold = 0xff; 690 691 /* default to -3.5dB de-emphasis */ 692 tx_de_emphasis = 1; 693 694 /* 695 * default to assert utmi_sleep_n and use maximum allowed HIRD 696 * threshold value of 0b1100 697 */ 698 hird_threshold = 12; 699 700 dwc->maximum_speed = dwc3_dev->maximum_speed; 701 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum; 702 if (dwc3_dev->lpm_nyet_threshold) 703 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold; 704 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend; 705 if (dwc3_dev->hird_threshold) 706 hird_threshold = dwc3_dev->hird_threshold; 707 708 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize; 709 dwc->dr_mode = dwc3_dev->dr_mode; 710 711 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk; 712 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk; 713 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk; 714 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk; 715 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk; 716 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk; 717 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk; 718 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk; 719 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk; 720 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; 721 722 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk; 723 if (dwc3_dev->tx_de_emphasis) 724 tx_de_emphasis = dwc3_dev->tx_de_emphasis; 725 726 /* default to superspeed if no maximum_speed passed */ 727 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 728 dwc->maximum_speed = USB_SPEED_SUPER; 729 730 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 731 dwc->tx_de_emphasis = tx_de_emphasis; 732 733 dwc->hird_threshold = hird_threshold 734 | (dwc->is_utmi_l1_suspend << 4); 735 736 dwc->index = dwc3_dev->index; 737 738 if (dwc3_dev->usb2_phyif_utmi_width) 739 dwc->usb2_phyif_utmi_width = dwc3_dev->usb2_phyif_utmi_width; 740 741 node = fdt_node_offset_by_compatible(blob, -1, 742 "rockchip,rk3399-xhci"); 743 if (node < 0) 744 debug("%s dwc3 node not found\n", __func__); 745 else 746 dwc->usb2_phyif_utmi_width = 747 fdtdec_get_int(blob, node, "snps,phyif-utmi-bits", -1); 748 749 dwc3_cache_hwparams(dwc); 750 751 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 752 if (ret) { 753 dev_err(dwc->dev, "failed to allocate event buffers\n"); 754 return -ENOMEM; 755 } 756 757 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 758 dwc->dr_mode = USB_DR_MODE_HOST; 759 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 760 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 761 762 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 763 dwc->dr_mode = USB_DR_MODE_OTG; 764 765 ret = dwc3_core_init(dwc); 766 if (ret) { 767 dev_err(dev, "failed to initialize core\n"); 768 goto err0; 769 } 770 771 dwc3_uboot_hsphy_mode(dwc3_dev, dwc); 772 773 ret = dwc3_event_buffers_setup(dwc); 774 if (ret) { 775 dev_err(dwc->dev, "failed to setup event buffers\n"); 776 goto err1; 777 } 778 779 ret = dwc3_core_init_mode(dwc); 780 if (ret) 781 goto err2; 782 783 list_add_tail(&dwc->list, &dwc3_list); 784 785 return 0; 786 787 err2: 788 dwc3_event_buffers_cleanup(dwc); 789 790 err1: 791 dwc3_core_exit(dwc); 792 793 err0: 794 dwc3_free_event_buffers(dwc); 795 796 return ret; 797 } 798 799 /** 800 * dwc3_uboot_exit - dwc3 core uboot cleanup code 801 * @index: index of this controller 802 * 803 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc 804 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller 805 * should be passed and should match with the index passed in 806 * dwc3_device during init. 807 * 808 * Generally called from board file. 809 */ 810 void dwc3_uboot_exit(int index) 811 { 812 struct dwc3 *dwc; 813 814 list_for_each_entry(dwc, &dwc3_list, list) { 815 if (dwc->index != index) 816 continue; 817 818 dwc3_core_exit_mode(dwc); 819 dwc3_event_buffers_cleanup(dwc); 820 dwc3_free_event_buffers(dwc); 821 dwc3_core_exit(dwc); 822 list_del(&dwc->list); 823 kfree(dwc->mem); 824 break; 825 } 826 } 827 828 /** 829 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt 830 * @index: index of this controller 831 * 832 * Invokes dwc3 gadget interrupts. 833 * 834 * Generally called from board file. 835 */ 836 void dwc3_uboot_handle_interrupt(int index) 837 { 838 struct dwc3 *dwc = NULL; 839 840 list_for_each_entry(dwc, &dwc3_list, list) { 841 if (dwc->index != index) 842 continue; 843 844 dwc3_gadget_uboot_handle_interrupt(dwc); 845 break; 846 } 847 } 848 849 MODULE_ALIAS("platform:dwc3"); 850 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 851 MODULE_LICENSE("GPL v2"); 852 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 853 854 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) 855 int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys) 856 { 857 int i, ret, count; 858 struct phy *usb_phys; 859 860 /* Return if no phy declared */ 861 if (!dev_read_prop(dev, "phys", NULL)) 862 return 0; 863 count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); 864 if (count <= 0) 865 return count; 866 867 usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), 868 GFP_KERNEL); 869 if (!usb_phys) 870 return -ENOMEM; 871 872 for (i = 0; i < count; i++) { 873 ret = generic_phy_get_by_index(dev, i, &usb_phys[i]); 874 if (ret && ret != -ENOENT) { 875 pr_err("Failed to get USB PHY%d for %s\n", 876 i, dev->name); 877 return ret; 878 } 879 } 880 881 for (i = 0; i < count; i++) { 882 ret = generic_phy_init(&usb_phys[i]); 883 if (ret) { 884 pr_err("Can't init USB PHY%d for %s\n", 885 i, dev->name); 886 goto phys_init_err; 887 } 888 } 889 890 for (i = 0; i < count; i++) { 891 ret = generic_phy_power_on(&usb_phys[i]); 892 if (ret) { 893 pr_err("Can't power USB PHY%d for %s\n", 894 i, dev->name); 895 goto phys_poweron_err; 896 } 897 } 898 899 *array = usb_phys; 900 *num_phys = count; 901 return 0; 902 903 phys_poweron_err: 904 for (i = count - 1; i >= 0; i--) 905 generic_phy_power_off(&usb_phys[i]); 906 907 for (i = 0; i < count; i++) 908 generic_phy_exit(&usb_phys[i]); 909 910 return ret; 911 912 phys_init_err: 913 for (; i >= 0; i--) 914 generic_phy_exit(&usb_phys[i]); 915 916 return ret; 917 } 918 919 int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys) 920 { 921 int i, ret; 922 923 for (i = 0; i < num_phys; i++) { 924 if (!generic_phy_valid(&usb_phys[i])) 925 continue; 926 927 ret = generic_phy_power_off(&usb_phys[i]); 928 ret |= generic_phy_exit(&usb_phys[i]); 929 if (ret) { 930 pr_err("Can't shutdown USB PHY%d for %s\n", 931 i, dev->name); 932 } 933 } 934 935 return 0; 936 } 937 #endif 938 939 #if CONFIG_IS_ENABLED(DM_USB) 940 void dwc3_of_parse(struct dwc3 *dwc) 941 { 942 const u8 *tmp; 943 struct udevice *dev = dwc->dev; 944 u8 lpm_nyet_threshold; 945 u8 tx_de_emphasis; 946 u8 hird_threshold; 947 948 /* default to highest possible threshold */ 949 lpm_nyet_threshold = 0xff; 950 951 /* default to -3.5dB de-emphasis */ 952 tx_de_emphasis = 1; 953 954 /* 955 * default to assert utmi_sleep_n and use maximum allowed HIRD 956 * threshold value of 0b1100 957 */ 958 hird_threshold = 12; 959 960 dwc->has_lpm_erratum = dev_read_bool(dev, 961 "snps,has-lpm-erratum"); 962 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1); 963 if (tmp) 964 lpm_nyet_threshold = *tmp; 965 966 dwc->is_utmi_l1_suspend = dev_read_bool(dev, 967 "snps,is-utmi-l1-suspend"); 968 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1); 969 if (tmp) 970 hird_threshold = *tmp; 971 972 dwc->disable_scramble_quirk = dev_read_bool(dev, 973 "snps,disable_scramble_quirk"); 974 dwc->u2exit_lfps_quirk = dev_read_bool(dev, 975 "snps,u2exit_lfps_quirk"); 976 dwc->u2ss_inp3_quirk = dev_read_bool(dev, 977 "snps,u2ss_inp3_quirk"); 978 dwc->req_p1p2p3_quirk = dev_read_bool(dev, 979 "snps,req_p1p2p3_quirk"); 980 dwc->del_p1p2p3_quirk = dev_read_bool(dev, 981 "snps,del_p1p2p3_quirk"); 982 dwc->del_phy_power_chg_quirk = dev_read_bool(dev, 983 "snps,del_phy_power_chg_quirk"); 984 dwc->lfps_filter_quirk = dev_read_bool(dev, 985 "snps,lfps_filter_quirk"); 986 dwc->rx_detect_poll_quirk = dev_read_bool(dev, 987 "snps,rx_detect_poll_quirk"); 988 dwc->dis_u3_susphy_quirk = dev_read_bool(dev, 989 "snps,dis_u3_susphy_quirk"); 990 dwc->dis_u2_susphy_quirk = dev_read_bool(dev, 991 "snps,dis_u2_susphy_quirk"); 992 dwc->tx_de_emphasis_quirk = dev_read_bool(dev, 993 "snps,tx_de_emphasis_quirk"); 994 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1); 995 if (tmp) 996 tx_de_emphasis = *tmp; 997 998 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 999 dwc->tx_de_emphasis = tx_de_emphasis; 1000 1001 dwc->hird_threshold = hird_threshold 1002 | (dwc->is_utmi_l1_suspend << 4); 1003 } 1004 1005 int dwc3_init(struct dwc3 *dwc) 1006 { 1007 int ret; 1008 1009 dwc3_cache_hwparams(dwc); 1010 1011 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1012 if (ret) { 1013 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1014 return -ENOMEM; 1015 } 1016 1017 ret = dwc3_core_init(dwc); 1018 if (ret) { 1019 dev_err(dev, "failed to initialize core\n"); 1020 goto core_fail; 1021 } 1022 1023 ret = dwc3_event_buffers_setup(dwc); 1024 if (ret) { 1025 dev_err(dwc->dev, "failed to setup event buffers\n"); 1026 goto event_fail; 1027 } 1028 1029 ret = dwc3_core_init_mode(dwc); 1030 if (ret) 1031 goto mode_fail; 1032 1033 return 0; 1034 1035 mode_fail: 1036 dwc3_event_buffers_cleanup(dwc); 1037 1038 event_fail: 1039 dwc3_core_exit(dwc); 1040 1041 core_fail: 1042 dwc3_free_event_buffers(dwc); 1043 1044 return ret; 1045 } 1046 1047 void dwc3_remove(struct dwc3 *dwc) 1048 { 1049 dwc3_core_exit_mode(dwc); 1050 dwc3_event_buffers_cleanup(dwc); 1051 dwc3_free_event_buffers(dwc); 1052 dwc3_core_exit(dwc); 1053 kfree(dwc->mem); 1054 } 1055 #endif 1056