1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported 10 * to uboot. 11 * 12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <common.h> 18 #include <malloc.h> 19 #include <fdtdec.h> 20 #include <dwc3-uboot.h> 21 #include <asm/dma-mapping.h> 22 #include <linux/ioport.h> 23 24 #include <linux/usb/ch9.h> 25 #include <linux/usb/gadget.h> 26 27 #include "core.h" 28 #include "gadget.h" 29 #include "io.h" 30 31 #include "linux-compat.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 static LIST_HEAD(dwc3_list); 36 /* -------------------------------------------------------------------------- */ 37 38 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 39 { 40 u32 reg; 41 42 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 43 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 44 reg |= DWC3_GCTL_PRTCAPDIR(mode); 45 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 46 } 47 48 /** 49 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 50 * @dwc: pointer to our context structure 51 */ 52 static int dwc3_core_soft_reset(struct dwc3 *dwc) 53 { 54 u32 reg; 55 56 /* Before Resetting PHY, put Core in Reset */ 57 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 58 reg |= DWC3_GCTL_CORESOFTRESET; 59 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 60 61 /* Assert USB3 PHY reset */ 62 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 63 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 64 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 65 66 /* Assert USB2 PHY reset */ 67 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 68 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 69 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 70 71 mdelay(100); 72 73 /* Clear USB3 PHY reset */ 74 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 75 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 76 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 77 78 /* Clear USB2 PHY reset */ 79 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 80 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 81 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 82 83 mdelay(100); 84 85 /* After PHYs are stable we can take Core out of reset state */ 86 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 87 reg &= ~DWC3_GCTL_CORESOFTRESET; 88 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 89 90 return 0; 91 } 92 93 /** 94 * dwc3_free_one_event_buffer - Frees one event buffer 95 * @dwc: Pointer to our controller context structure 96 * @evt: Pointer to event buffer to be freed 97 */ 98 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 99 struct dwc3_event_buffer *evt) 100 { 101 dma_free_coherent(evt->buf); 102 } 103 104 /** 105 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 106 * @dwc: Pointer to our controller context structure 107 * @length: size of the event buffer 108 * 109 * Returns a pointer to the allocated event buffer structure on success 110 * otherwise ERR_PTR(errno). 111 */ 112 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 113 unsigned length) 114 { 115 struct dwc3_event_buffer *evt; 116 117 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 118 if (!evt) 119 return ERR_PTR(-ENOMEM); 120 121 evt->dwc = dwc; 122 evt->length = length; 123 evt->buf = dma_alloc_coherent(length, 124 (unsigned long *)&evt->dma); 125 if (!evt->buf) 126 return ERR_PTR(-ENOMEM); 127 128 dwc3_flush_cache((uintptr_t)evt->buf, evt->length); 129 130 return evt; 131 } 132 133 /** 134 * dwc3_free_event_buffers - frees all allocated event buffers 135 * @dwc: Pointer to our controller context structure 136 */ 137 static void dwc3_free_event_buffers(struct dwc3 *dwc) 138 { 139 struct dwc3_event_buffer *evt; 140 int i; 141 142 for (i = 0; i < dwc->num_event_buffers; i++) { 143 evt = dwc->ev_buffs[i]; 144 if (evt) 145 dwc3_free_one_event_buffer(dwc, evt); 146 } 147 } 148 149 /** 150 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 151 * @dwc: pointer to our controller context structure 152 * @length: size of event buffer 153 * 154 * Returns 0 on success otherwise negative errno. In the error case, dwc 155 * may contain some buffers allocated but not all which were requested. 156 */ 157 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 158 { 159 int num; 160 int i; 161 162 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 163 dwc->num_event_buffers = num; 164 165 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE, 166 sizeof(*dwc->ev_buffs) * num); 167 if (!dwc->ev_buffs) 168 return -ENOMEM; 169 170 for (i = 0; i < num; i++) { 171 struct dwc3_event_buffer *evt; 172 173 evt = dwc3_alloc_one_event_buffer(dwc, length); 174 if (IS_ERR(evt)) { 175 dev_err(dwc->dev, "can't allocate event buffer\n"); 176 return PTR_ERR(evt); 177 } 178 dwc->ev_buffs[i] = evt; 179 } 180 181 return 0; 182 } 183 184 /** 185 * dwc3_event_buffers_setup - setup our allocated event buffers 186 * @dwc: pointer to our controller context structure 187 * 188 * Returns 0 on success otherwise negative errno. 189 */ 190 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 191 { 192 struct dwc3_event_buffer *evt; 193 int n; 194 195 for (n = 0; n < dwc->num_event_buffers; n++) { 196 evt = dwc->ev_buffs[n]; 197 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 198 evt->buf, (unsigned long long) evt->dma, 199 evt->length); 200 201 evt->lpos = 0; 202 203 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 204 lower_32_bits(evt->dma)); 205 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 206 upper_32_bits(evt->dma)); 207 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 208 DWC3_GEVNTSIZ_SIZE(evt->length)); 209 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 210 } 211 212 return 0; 213 } 214 215 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 216 { 217 struct dwc3_event_buffer *evt; 218 int n; 219 220 for (n = 0; n < dwc->num_event_buffers; n++) { 221 evt = dwc->ev_buffs[n]; 222 223 evt->lpos = 0; 224 225 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 226 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 227 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 228 | DWC3_GEVNTSIZ_SIZE(0)); 229 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 230 } 231 } 232 233 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 234 { 235 if (!dwc->has_hibernation) 236 return 0; 237 238 if (!dwc->nr_scratch) 239 return 0; 240 241 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 242 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 243 if (!dwc->scratchbuf) 244 return -ENOMEM; 245 246 return 0; 247 } 248 249 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 250 { 251 dma_addr_t scratch_addr; 252 u32 param; 253 int ret; 254 255 if (!dwc->has_hibernation) 256 return 0; 257 258 if (!dwc->nr_scratch) 259 return 0; 260 261 scratch_addr = dma_map_single(dwc->scratchbuf, 262 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 263 DMA_BIDIRECTIONAL); 264 if (dma_mapping_error(dwc->dev, scratch_addr)) { 265 dev_err(dwc->dev, "failed to map scratch buffer\n"); 266 ret = -EFAULT; 267 goto err0; 268 } 269 270 dwc->scratch_addr = scratch_addr; 271 272 param = lower_32_bits(scratch_addr); 273 274 ret = dwc3_send_gadget_generic_command(dwc, 275 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 276 if (ret < 0) 277 goto err1; 278 279 param = upper_32_bits(scratch_addr); 280 281 ret = dwc3_send_gadget_generic_command(dwc, 282 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 283 if (ret < 0) 284 goto err1; 285 286 return 0; 287 288 err1: 289 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 290 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 291 292 err0: 293 return ret; 294 } 295 296 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 297 { 298 if (!dwc->has_hibernation) 299 return; 300 301 if (!dwc->nr_scratch) 302 return; 303 304 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch * 305 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 306 kfree(dwc->scratchbuf); 307 } 308 309 static void dwc3_core_num_eps(struct dwc3 *dwc) 310 { 311 struct dwc3_hwparams *parms = &dwc->hwparams; 312 313 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 314 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 315 316 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", 317 dwc->num_in_eps, dwc->num_out_eps); 318 } 319 320 static void dwc3_cache_hwparams(struct dwc3 *dwc) 321 { 322 struct dwc3_hwparams *parms = &dwc->hwparams; 323 324 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 325 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 326 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 327 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 328 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 329 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 330 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 331 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 332 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 333 } 334 335 /** 336 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 337 * @dwc: Pointer to our controller context structure 338 */ 339 static void dwc3_phy_setup(struct dwc3 *dwc) 340 { 341 u32 reg; 342 343 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 344 345 /* 346 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 347 * to '0' during coreConsultant configuration. So default value 348 * will be '0' when the core is reset. Application needs to set it 349 * to '1' after the core initialization is completed. 350 */ 351 if (dwc->revision > DWC3_REVISION_194A) 352 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 353 354 if (dwc->u2ss_inp3_quirk) 355 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 356 357 if (dwc->req_p1p2p3_quirk) 358 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 359 360 if (dwc->del_p1p2p3_quirk) 361 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 362 363 if (dwc->del_phy_power_chg_quirk) 364 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 365 366 if (dwc->lfps_filter_quirk) 367 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 368 369 if (dwc->rx_detect_poll_quirk) 370 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 371 372 if (dwc->tx_de_emphasis_quirk) 373 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 374 375 if (dwc->dis_u3_susphy_quirk) 376 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 377 378 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 379 380 mdelay(100); 381 382 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 383 384 /* 385 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 386 * '0' during coreConsultant configuration. So default value will 387 * be '0' when the core is reset. Application needs to set it to 388 * '1' after the core initialization is completed. 389 */ 390 if (dwc->revision > DWC3_REVISION_194A) 391 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 392 393 if (dwc->dis_u2_susphy_quirk) 394 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 395 396 if (dwc->usb2_phyif_utmi_width == 16) { 397 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 398 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; 399 reg |= DWC3_GUSB2PHYCFG_PHYIF_16BIT; 400 } 401 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 402 403 mdelay(100); 404 } 405 406 /** 407 * dwc3_core_init - Low-level initialization of DWC3 Core 408 * @dwc: Pointer to our controller context structure 409 * 410 * Returns 0 on success otherwise negative errno. 411 */ 412 static int dwc3_core_init(struct dwc3 *dwc) 413 { 414 unsigned long timeout; 415 u32 hwparams4 = dwc->hwparams.hwparams4; 416 u32 reg; 417 int ret; 418 419 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 420 /* This should read as U3 followed by revision number */ 421 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 422 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 423 ret = -ENODEV; 424 goto err0; 425 } 426 dwc->revision = reg; 427 428 /* Handle USB2.0-only core configuration */ 429 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 430 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 431 if (dwc->maximum_speed == USB_SPEED_SUPER) 432 dwc->maximum_speed = USB_SPEED_HIGH; 433 } 434 435 /* issue device SoftReset too */ 436 timeout = 5000; 437 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 438 while (timeout--) { 439 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 440 if (!(reg & DWC3_DCTL_CSFTRST)) 441 break; 442 }; 443 444 if (!timeout) { 445 dev_err(dwc->dev, "Reset Timed Out\n"); 446 ret = -ETIMEDOUT; 447 goto err0; 448 } 449 450 ret = dwc3_core_soft_reset(dwc); 451 if (ret) 452 goto err0; 453 454 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 455 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 456 457 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 458 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 459 /** 460 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 461 * issue which would cause xHCI compliance tests to fail. 462 * 463 * Because of that we cannot enable clock gating on such 464 * configurations. 465 * 466 * Refers to: 467 * 468 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 469 * SOF/ITP Mode Used 470 */ 471 if ((dwc->dr_mode == USB_DR_MODE_HOST || 472 dwc->dr_mode == USB_DR_MODE_OTG) && 473 (dwc->revision >= DWC3_REVISION_210A && 474 dwc->revision <= DWC3_REVISION_250A)) 475 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 476 else 477 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 478 break; 479 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 480 /* enable hibernation here */ 481 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 482 483 /* 484 * REVISIT Enabling this bit so that host-mode hibernation 485 * will work. Device-mode hibernation is not yet implemented. 486 */ 487 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 488 break; 489 default: 490 dev_dbg(dwc->dev, "No power optimization available\n"); 491 } 492 493 /* check if current dwc3 is on simulation board */ 494 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 495 dev_dbg(dwc->dev, "it is on FPGA board\n"); 496 dwc->is_fpga = true; 497 } 498 499 if(dwc->disable_scramble_quirk && !dwc->is_fpga) 500 WARN(true, 501 "disable_scramble cannot be used on non-FPGA builds\n"); 502 503 if (dwc->disable_scramble_quirk && dwc->is_fpga) 504 reg |= DWC3_GCTL_DISSCRAMBLE; 505 else 506 reg &= ~DWC3_GCTL_DISSCRAMBLE; 507 508 if (dwc->u2exit_lfps_quirk) 509 reg |= DWC3_GCTL_U2EXIT_LFPS; 510 511 /* 512 * WORKAROUND: DWC3 revisions <1.90a have a bug 513 * where the device can fail to connect at SuperSpeed 514 * and falls back to high-speed mode which causes 515 * the device to enter a Connect/Disconnect loop 516 */ 517 if (dwc->revision < DWC3_REVISION_190A) 518 reg |= DWC3_GCTL_U2RSTECN; 519 520 dwc3_core_num_eps(dwc); 521 522 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 523 524 dwc3_phy_setup(dwc); 525 526 ret = dwc3_alloc_scratch_buffers(dwc); 527 if (ret) 528 goto err0; 529 530 ret = dwc3_setup_scratch_buffers(dwc); 531 if (ret) 532 goto err1; 533 534 return 0; 535 536 err1: 537 dwc3_free_scratch_buffers(dwc); 538 539 err0: 540 return ret; 541 } 542 543 static void dwc3_core_exit(struct dwc3 *dwc) 544 { 545 dwc3_free_scratch_buffers(dwc); 546 } 547 548 static int dwc3_core_init_mode(struct dwc3 *dwc) 549 { 550 int ret; 551 552 switch (dwc->dr_mode) { 553 case USB_DR_MODE_PERIPHERAL: 554 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 555 ret = dwc3_gadget_init(dwc); 556 if (ret) { 557 dev_err(dev, "failed to initialize gadget\n"); 558 return ret; 559 } 560 break; 561 case USB_DR_MODE_HOST: 562 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 563 ret = dwc3_host_init(dwc); 564 if (ret) { 565 dev_err(dev, "failed to initialize host\n"); 566 return ret; 567 } 568 break; 569 case USB_DR_MODE_OTG: 570 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 571 ret = dwc3_host_init(dwc); 572 if (ret) { 573 dev_err(dev, "failed to initialize host\n"); 574 return ret; 575 } 576 577 ret = dwc3_gadget_init(dwc); 578 if (ret) { 579 dev_err(dev, "failed to initialize gadget\n"); 580 return ret; 581 } 582 break; 583 default: 584 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 585 return -EINVAL; 586 } 587 588 return 0; 589 } 590 591 static void dwc3_core_exit_mode(struct dwc3 *dwc) 592 { 593 switch (dwc->dr_mode) { 594 case USB_DR_MODE_PERIPHERAL: 595 dwc3_gadget_exit(dwc); 596 break; 597 case USB_DR_MODE_HOST: 598 dwc3_host_exit(dwc); 599 break; 600 case USB_DR_MODE_OTG: 601 dwc3_host_exit(dwc); 602 dwc3_gadget_exit(dwc); 603 break; 604 default: 605 /* do nothing */ 606 break; 607 } 608 } 609 610 #define DWC3_ALIGN_MASK (16 - 1) 611 612 /** 613 * dwc3_uboot_init - dwc3 core uboot initialization code 614 * @dwc3_dev: struct dwc3_device containing initialization data 615 * 616 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux 617 * kernel driver). Pointer to dwc3_device should be passed containing 618 * base address and other initialization data. Returns '0' on success and 619 * a negative value on failure. 620 * 621 * Generally called from board_usb_init() implemented in board file. 622 */ 623 int dwc3_uboot_init(struct dwc3_device *dwc3_dev) 624 { 625 struct dwc3 *dwc; 626 struct device *dev = NULL; 627 u8 lpm_nyet_threshold; 628 u8 tx_de_emphasis; 629 u8 hird_threshold; 630 631 int ret; 632 633 void *mem; 634 const void *blob = gd->fdt_blob; 635 int node; 636 637 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 638 if (!mem) 639 return -ENOMEM; 640 641 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 642 dwc->mem = mem; 643 644 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base + 645 DWC3_GLOBALS_REGS_START); 646 647 /* default to highest possible threshold */ 648 lpm_nyet_threshold = 0xff; 649 650 /* default to -3.5dB de-emphasis */ 651 tx_de_emphasis = 1; 652 653 /* 654 * default to assert utmi_sleep_n and use maximum allowed HIRD 655 * threshold value of 0b1100 656 */ 657 hird_threshold = 12; 658 659 dwc->maximum_speed = dwc3_dev->maximum_speed; 660 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum; 661 if (dwc3_dev->lpm_nyet_threshold) 662 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold; 663 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend; 664 if (dwc3_dev->hird_threshold) 665 hird_threshold = dwc3_dev->hird_threshold; 666 667 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize; 668 dwc->dr_mode = dwc3_dev->dr_mode; 669 670 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk; 671 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk; 672 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk; 673 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk; 674 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk; 675 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk; 676 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk; 677 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk; 678 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk; 679 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; 680 681 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk; 682 if (dwc3_dev->tx_de_emphasis) 683 tx_de_emphasis = dwc3_dev->tx_de_emphasis; 684 685 /* default to superspeed if no maximum_speed passed */ 686 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 687 dwc->maximum_speed = USB_SPEED_SUPER; 688 689 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 690 dwc->tx_de_emphasis = tx_de_emphasis; 691 692 dwc->hird_threshold = hird_threshold 693 | (dwc->is_utmi_l1_suspend << 4); 694 695 dwc->index = dwc3_dev->index; 696 697 if (dwc3_dev->usb2_phyif_utmi_width) 698 dwc->usb2_phyif_utmi_width = dwc3_dev->usb2_phyif_utmi_width; 699 700 node = fdt_node_offset_by_compatible(blob, -1, 701 "rockchip,rk3399-xhci"); 702 if (node < 0) 703 debug("%s dwc3 node not found\n", __func__); 704 else 705 dwc->usb2_phyif_utmi_width = 706 fdtdec_get_int(blob, node, "snps,phyif-utmi-bits", -1); 707 708 dwc3_cache_hwparams(dwc); 709 710 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 711 if (ret) { 712 dev_err(dwc->dev, "failed to allocate event buffers\n"); 713 return -ENOMEM; 714 } 715 716 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 717 dwc->dr_mode = USB_DR_MODE_HOST; 718 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 719 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 720 721 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 722 dwc->dr_mode = USB_DR_MODE_OTG; 723 724 ret = dwc3_core_init(dwc); 725 if (ret) { 726 dev_err(dev, "failed to initialize core\n"); 727 goto err0; 728 } 729 730 ret = dwc3_event_buffers_setup(dwc); 731 if (ret) { 732 dev_err(dwc->dev, "failed to setup event buffers\n"); 733 goto err1; 734 } 735 736 ret = dwc3_core_init_mode(dwc); 737 if (ret) 738 goto err2; 739 740 list_add_tail(&dwc->list, &dwc3_list); 741 742 return 0; 743 744 err2: 745 dwc3_event_buffers_cleanup(dwc); 746 747 err1: 748 dwc3_core_exit(dwc); 749 750 err0: 751 dwc3_free_event_buffers(dwc); 752 753 return ret; 754 } 755 756 /** 757 * dwc3_uboot_exit - dwc3 core uboot cleanup code 758 * @index: index of this controller 759 * 760 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc 761 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller 762 * should be passed and should match with the index passed in 763 * dwc3_device during init. 764 * 765 * Generally called from board file. 766 */ 767 void dwc3_uboot_exit(int index) 768 { 769 struct dwc3 *dwc; 770 771 list_for_each_entry(dwc, &dwc3_list, list) { 772 if (dwc->index != index) 773 continue; 774 775 dwc3_core_exit_mode(dwc); 776 dwc3_event_buffers_cleanup(dwc); 777 dwc3_free_event_buffers(dwc); 778 dwc3_core_exit(dwc); 779 list_del(&dwc->list); 780 kfree(dwc->mem); 781 break; 782 } 783 } 784 785 /** 786 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt 787 * @index: index of this controller 788 * 789 * Invokes dwc3 gadget interrupts. 790 * 791 * Generally called from board file. 792 */ 793 void dwc3_uboot_handle_interrupt(int index) 794 { 795 struct dwc3 *dwc = NULL; 796 797 list_for_each_entry(dwc, &dwc3_list, list) { 798 if (dwc->index != index) 799 continue; 800 801 dwc3_gadget_uboot_handle_interrupt(dwc); 802 break; 803 } 804 } 805 806 MODULE_ALIAS("platform:dwc3"); 807 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 808 MODULE_LICENSE("GPL v2"); 809 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 810