1 /* 2 * SFC driver for rockchip 3 * 4 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 5 * Yifeng.zhao, Software Engineering, <zhao0116@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <bouncebuf.h> 12 #include <clk.h> 13 #include <dm.h> 14 #include <dt-structs.h> 15 #include <errno.h> 16 #include <spi.h> 17 #include <linux/errno.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/periph.h> 21 #include <dm/pinctrl.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 struct rockchip_sfc_reg { 26 u32 ctrl; 27 u32 imr; 28 u32 iclr; 29 u32 ftlr; 30 u32 rcvr; 31 u32 ax; 32 u32 abit; 33 u32 isr; 34 u32 fsr; 35 u32 sr; 36 u32 risr; 37 u32 reserved[21]; 38 u32 dmatr; 39 u32 dmaaddr; 40 u32 reserved1[30]; 41 u32 cmd; 42 u32 addr; 43 u32 data; 44 }; 45 check_member(rockchip_sfc_reg, data, 0x108); 46 47 /*SFC_CTRL*/ 48 #define SFC_DATA_WIDTH_SHIFT 12 49 #define SFC_DATA_WIDTH_MASK GENMASK(13, 12) 50 #define SFC_ADDR_WIDTH_SHIFT 10 51 #define SFC_ADDR_WIDTH_MASK GENMASK(11, 10) 52 #define SFC_CMD_WIDTH_SHIFT 8 53 #define SFC_CMD_WIDTH_MASK GENMASK(9, 8) 54 #define SFC_DATA_SHIFT_NEGETIVE BIT(1) 55 56 /*SFC_CMD*/ 57 #define SFC_DUMMY_BITS_SHIFT 8 58 #define SFC_RW_SHIFT 12 59 #define SFC_WR 1 60 #define SFC_RD 0 61 #define SFC_ADDR_BITS_SHIFT 14 62 #define SFC_ADDR_BITS_MASK GENMASK(15, 14) 63 #define SFC_ADDR_0BITS 0 64 #define SFC_ADDR_24BITS 1 65 #define SFC_ADDR_32BITS 2 66 #define SFC_ADDR_XBITS 3 67 #define SFC_TRB_SHIFT (16) 68 #define SFC_TRB_MASK GENMASK(29, 16) 69 70 /* Dma start trigger signal. Auto cleared after write */ 71 #define SFC_DMA_START BIT(0) 72 73 #define SFC_RESET BIT(0) 74 75 /*SFC_FSR*/ 76 #define SFC_RXLV_SHIFT (16) 77 #define SFC_RXLV_MASK GENMASK(20, 16) 78 #define SFC_TXLV_SHIFT (8) 79 #define SFC_TXLV_MASK GENMASK(12, 8) 80 #define SFC_RX_FULL BIT(3) /* rx fifo full */ 81 #define SFC_RX_EMPTY BIT(2) /* rx fifo empty */ 82 #define SFC_TX_EMPTY BIT(1) /* tx fifo empty */ 83 #define SFC_TX_FULL BIT(0) /* tx fifo full */ 84 85 #define SFC_BUSY BIT(0) /* sfc busy flag */ 86 87 /*SFC_RISR*/ 88 #define DMA_FINISH_INT BIT(7) /* dma interrupt */ 89 #define SPI_ERR_INT BIT(6) /* Nspi error interrupt */ 90 #define AHB_ERR_INT BIT(5) /* Ahb bus error interrupt */ 91 #define TRANS_FINISH_INT BIT(4) /* Transfer finish interrupt */ 92 #define TX_EMPTY_INT BIT(3) /* Tx fifo empty interrupt */ 93 #define TX_OF_INT BIT(2) /* Tx fifo overflow interrupt */ 94 #define RX_UF_INT BIT(1) /* Rx fifo underflow interrupt */ 95 #define RX_FULL_INT BIT(0) /* Rx fifo full interrupt */ 96 97 #define SFC_MAX_TRB (512 * 31) 98 99 enum rockchip_sfc_if_type { 100 IF_TYPE_STD, 101 IF_TYPE_DUAL, 102 IF_TYPE_QUAD, 103 }; 104 105 struct rockchip_sfc_platdata { 106 s32 frequency; 107 void *base; 108 }; 109 110 struct rockchip_sfc { 111 struct rockchip_sfc_reg *regbase; 112 struct clk clk; 113 unsigned int max_freq; 114 unsigned int mode; 115 unsigned int speed_hz; 116 u32 cmd; 117 u32 addr; 118 u8 addr_bits; 119 u8 dummy_bits; 120 u8 rw; 121 u32 trb; 122 }; 123 124 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 125 { 126 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 127 struct rockchip_sfc *sfc = dev_get_priv(bus); 128 ofnode subnode; 129 int ret; 130 131 plat->base = dev_read_addr_ptr(bus); 132 ret = clk_get_by_index(bus, 0, &sfc->clk); 133 if (ret < 0) { 134 printf("Could not get clock for %s: %d\n", bus->name, ret); 135 return ret; 136 } 137 138 subnode = dev_read_first_subnode(bus); 139 if (!ofnode_valid(subnode)) { 140 printf("Error: subnode with SPI flash config missing!\n"); 141 return -ENODEV; 142 } 143 144 plat->frequency = ofnode_read_u32_default(subnode, "spi-max-frequency", 145 100000000); 146 147 return 0; 148 } 149 150 static int rockchip_sfc_probe(struct udevice *bus) 151 { 152 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 153 struct rockchip_sfc *sfc = dev_get_priv(bus); 154 155 sfc->regbase = (struct rockchip_sfc_reg *)plat->base; 156 157 return 0; 158 } 159 160 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 161 { 162 struct rockchip_sfc_reg *regs = sfc->regbase; 163 int tbase = get_timer(0); 164 u32 rcvr; 165 int ret = 0; 166 167 writel(SFC_RESET, ®s->rcvr); 168 do { 169 rcvr = readl(®s->rcvr); 170 if (get_timer(tbase) > 1000) { 171 debug("sfc reset timeout\n"); 172 ret = -ETIMEDOUT; 173 break; 174 } 175 udelay(1); 176 } while (rcvr); 177 178 writel(0xFFFFFFFF, ®s->iclr); 179 180 debug("sfc reset\n"); 181 182 return ret; 183 } 184 185 /* The SFC_CTRL register is a global control register, 186 * when the controller is in busy state(SFC_SR), 187 * SFC_CTRL cannot be set. 188 */ 189 static int rockchip_sfc_wait_idle(struct rockchip_sfc *sfc, 190 u32 timeout_ms) 191 { 192 struct rockchip_sfc_reg *regs = sfc->regbase; 193 unsigned long tbase = get_timer(0); 194 u32 sr, fsr; 195 196 while (1) { 197 sr = readl(®s->sr); 198 fsr = readl(®s->fsr); 199 if ((fsr & SFC_TX_EMPTY) && (fsr & SFC_RX_EMPTY) && !(sr & SFC_BUSY)) 200 break; 201 if (get_timer(tbase) > timeout_ms) { 202 printf("waite sfc idle timeout(sr:0x%08x fsr:0x%08x)\n", 203 sr, fsr); 204 rockchip_sfc_reset(sfc); 205 return -ETIMEDOUT; 206 } 207 udelay(100); 208 } 209 210 return 0; 211 } 212 213 static u8 rockchip_sfc_get_if_type(struct rockchip_sfc *sfc) 214 { 215 int type = IF_TYPE_STD; 216 217 if (sfc->rw == SFC_WR) { 218 if (sfc->mode & SPI_TX_QUAD) 219 type = IF_TYPE_QUAD; 220 else if (sfc->mode & SPI_TX_DUAL) 221 type = IF_TYPE_DUAL; 222 else 223 type = IF_TYPE_STD; 224 } else { 225 if (sfc->mode & SPI_RX_QUAD) 226 type = IF_TYPE_QUAD; 227 else if (sfc->mode & SPI_RX_DUAL) 228 type = IF_TYPE_DUAL; 229 else 230 type = IF_TYPE_STD; 231 } 232 233 return type; 234 } 235 236 static void rockchip_sfc_setup_xfer(struct rockchip_sfc *sfc, u32 trb) 237 { 238 struct rockchip_sfc_reg *regs = sfc->regbase; 239 u32 val = 0x02; 240 u8 data_width = IF_TYPE_STD; 241 242 if (sfc->addr_bits & SFC_ADDR_XBITS) 243 data_width = rockchip_sfc_get_if_type(sfc); 244 245 val |= (data_width << SFC_DATA_WIDTH_SHIFT); 246 247 rockchip_sfc_wait_idle(sfc, 10); 248 249 writel(val, ®s->ctrl); 250 251 val = sfc->cmd; 252 val |= trb << SFC_TRB_SHIFT; 253 val |= sfc->rw << SFC_RW_SHIFT; 254 val |= sfc->addr_bits << SFC_ADDR_BITS_SHIFT; 255 val |= sfc->dummy_bits << SFC_DUMMY_BITS_SHIFT; 256 257 writel(val, ®s->cmd); 258 259 if (sfc->addr_bits & SFC_ADDR_XBITS) 260 writel(sfc->addr, ®s->addr); 261 } 262 263 static int rockchip_sfc_dma_xfer(struct rockchip_sfc *sfc, void *buffer, size_t trb) 264 { 265 struct rockchip_sfc_reg *regs = sfc->regbase; 266 struct bounce_buffer bb; 267 unsigned int bb_flags; 268 int timeout = 1000; 269 int ret = 0; 270 int risr; 271 unsigned long tbase; 272 273 if (sfc->rw == SFC_WR) 274 bb_flags = GEN_BB_READ; 275 else 276 bb_flags = GEN_BB_WRITE; 277 278 ret = bounce_buffer_start(&bb, buffer, trb, bb_flags); 279 if (ret) 280 return ret; 281 282 rockchip_sfc_setup_xfer(sfc, bb.len_aligned); 283 284 writel(0xFFFFFFFF, ®s->iclr); 285 writel((unsigned long)bb.bounce_buffer, ®s->dmaaddr); 286 writel(SFC_DMA_START, ®s->dmatr); 287 288 tbase = get_timer(0); 289 do { 290 udelay(1); 291 risr = readl(®s->risr); 292 if (get_timer(tbase) > timeout) { 293 debug("dma timeout\n"); 294 ret = -ETIMEDOUT; 295 break; 296 } 297 } while (!(risr & TRANS_FINISH_INT)); 298 299 writel(0xFFFFFFFF, ®s->iclr); 300 301 bounce_buffer_stop(&bb); 302 303 return ret; 304 } 305 306 static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int rw, 307 u32 timeout) 308 { 309 struct rockchip_sfc_reg *regs = sfc->regbase; 310 unsigned long tbase = get_timer(0); 311 u8 level; 312 u32 fsr; 313 314 do { 315 fsr = readl(®s->fsr); 316 if (rw == SFC_WR) 317 level = (fsr & SFC_TXLV_MASK) >> SFC_TXLV_SHIFT; 318 else 319 level = (fsr & SFC_RXLV_MASK) >> SFC_RXLV_SHIFT; 320 if (get_timer(tbase) > timeout) 321 return -ETIMEDOUT; 322 udelay(1); 323 } while (!level); 324 325 return level; 326 } 327 328 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 329 { 330 struct rockchip_sfc_reg *regs = sfc->regbase; 331 u32 bytes = len & 0x3; 332 u32 words = len >> 2; 333 int tx_level = 0; 334 u32 val = 0; 335 u8 count; 336 337 while (words) { 338 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 339 if (tx_level <= 0) 340 return tx_level; 341 count = min(words, (u32)tx_level); 342 writesl(®s->data, buf, count); 343 buf += count; 344 words -= count; 345 } 346 347 /* handle the last non 4byte aligned bytes */ 348 if (bytes) { 349 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 350 if (tx_level <= 0) 351 return tx_level; 352 memcpy(&val, buf, bytes); 353 writel(val, ®s->data); 354 } 355 356 return 0; 357 } 358 359 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 360 { 361 struct rockchip_sfc_reg *regs = sfc->regbase; 362 u32 bytes = len & 0x3; 363 u32 words = len >> 2; 364 int rx_level = 0; 365 u32 count; 366 u32 val; 367 368 while (words) { 369 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 370 if (rx_level <= 0) 371 return rx_level; 372 count = min(words, (u32)rx_level); 373 readsl(®s->data, buf, count); 374 buf += count; 375 words -= count; 376 } 377 378 /* handle the last non 4 bytes aligned bytes */ 379 if (bytes) { 380 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 381 if (rx_level <= 0) 382 return rx_level; 383 val = readl(®s->data); 384 memcpy(buf, &val, bytes); 385 } 386 387 return 0; 388 } 389 390 static int rockchip_sfc_pio_xfer(struct rockchip_sfc *sfc, void *buf, u32 len) 391 { 392 int ret = 0; 393 394 rockchip_sfc_setup_xfer(sfc, len); 395 396 if (len) { 397 if (sfc->rw == SFC_WR) 398 ret = rockchip_sfc_write_fifo(sfc, (u32 *)buf, len); 399 else 400 ret = rockchip_sfc_read_fifo(sfc, (u32 *)buf, len); 401 } 402 403 return ret; 404 } 405 406 static int rockchip_sfc_read(struct rockchip_sfc *sfc, u32 offset, 407 void *buf, size_t len) 408 { 409 u32 dma_trans; 410 u32 trb; 411 u8 bytes; 412 int ret; 413 414 if (len >= ARCH_DMA_MINALIGN) { 415 bytes = len & (ARCH_DMA_MINALIGN - 1); 416 dma_trans = len - bytes; 417 } else { 418 dma_trans = 0; 419 bytes = len; 420 } 421 422 while (dma_trans) { 423 trb = min_t(size_t, dma_trans, SFC_MAX_TRB); 424 ret = rockchip_sfc_dma_xfer(sfc, buf, trb); 425 if (ret < 0) 426 return ret; 427 dma_trans -= trb; 428 sfc->addr += trb; 429 buf += trb; 430 } 431 432 /* 433 * transfer the last non dma anligned byte by pio mode 434 */ 435 if (bytes) 436 ret = rockchip_sfc_pio_xfer(sfc, buf, bytes); 437 438 return 0; 439 } 440 441 static int rockchip_sfc_write(struct rockchip_sfc *sfc, u32 offset, 442 void *buf, size_t len) 443 { 444 445 if (len > SFC_MAX_TRB) { 446 printf("out of the max sfc trb"); 447 return -EINVAL; 448 } 449 450 if (len && !(len & (ARCH_DMA_MINALIGN - 1))) 451 return rockchip_sfc_dma_xfer(sfc, buf, len); 452 else 453 return rockchip_sfc_pio_xfer(sfc, buf,len); 454 455 return 0; 456 } 457 458 static int rockchip_sfc_do_xfer(struct rockchip_sfc *sfc, void *buf, size_t len) 459 { 460 461 if (sfc->rw) 462 return rockchip_sfc_write(sfc, sfc->addr, buf, len); 463 else 464 return rockchip_sfc_read(sfc, sfc->addr, buf, len); 465 } 466 467 static int rockchip_sfc_xfer(struct udevice *dev, unsigned int bitlen, 468 const void *dout, void *din, unsigned long flags) 469 { 470 struct udevice *bus = dev->parent; 471 struct rockchip_sfc *sfc = dev_get_priv(bus); 472 int len = bitlen >> 3; 473 u8 *pcmd = (u8 *)dout; 474 void *data_buf; 475 int ret = 0; 476 477 if (flags & SPI_XFER_BEGIN) { 478 sfc->cmd = pcmd[0]; 479 if (len >= 4) { 480 sfc->addr_bits = SFC_ADDR_24BITS; 481 sfc->dummy_bits = (len - 4) << 3; 482 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 483 } else { 484 sfc->addr_bits = 0; 485 sfc->dummy_bits = 0; 486 sfc->addr = 0; 487 } 488 } 489 490 if (flags & SPI_XFER_END) { 491 492 if (din) { 493 sfc->rw = SFC_RD; 494 data_buf = din; 495 } else { 496 sfc->rw = SFC_WR; 497 data_buf = (void *)dout; 498 } 499 500 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 501 len = 0; 502 data_buf = NULL; 503 } 504 505 ret = rockchip_sfc_do_xfer(sfc, data_buf, len); 506 } 507 508 return ret; 509 } 510 511 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 512 { 513 struct rockchip_sfc *sfc = dev_get_priv(bus); 514 515 if (speed > sfc->max_freq) 516 speed = sfc->max_freq; 517 518 sfc->speed_hz = speed; 519 520 return 0; 521 } 522 523 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 524 { 525 struct rockchip_sfc *sfc = dev_get_priv(bus); 526 527 sfc->mode = mode; 528 529 return 0; 530 } 531 532 static const struct dm_spi_ops rockchip_sfc_ops = { 533 .xfer = rockchip_sfc_xfer, 534 .set_speed = rockchip_sfc_set_speed, 535 .set_mode = rockchip_sfc_set_mode, 536 }; 537 538 static const struct udevice_id rockchip_sfc_ids[] = { 539 { .compatible = "rockchip,sfc" }, 540 { } 541 }; 542 543 U_BOOT_DRIVER(rockchip_sfc_driver) = { 544 .name = "rockchip_sfc", 545 .id = UCLASS_SPI, 546 .of_match = rockchip_sfc_ids, 547 .ops = &rockchip_sfc_ops, 548 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 549 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc_platdata), 550 .priv_auto_alloc_size = sizeof(struct rockchip_sfc), 551 .probe = rockchip_sfc_probe, 552 }; 553