1 /* 2 * SFC driver for rockchip 3 * 4 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 5 * Yifeng.zhao, Software Engineering, <zhao0116@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <bouncebuf.h> 12 #include <clk.h> 13 #include <dm.h> 14 #include <dt-structs.h> 15 #include <errno.h> 16 #include <spi.h> 17 #include <linux/errno.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/periph.h> 21 #include <dm/pinctrl.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #ifdef SFC_DEBUG 26 #define SFC_DBG printf 27 #else 28 #define SFC_DBG(args...) 29 #endif 30 31 struct rockchip_sfc_reg { 32 u32 ctrl; 33 u32 imr; 34 u32 iclr; 35 u32 ftlr; 36 u32 rcvr; 37 u32 ax; 38 u32 abit; 39 u32 isr; 40 u32 fsr; 41 u32 sr; 42 u32 risr; 43 u32 reserved[21]; 44 u32 dmatr; 45 u32 dmaaddr; 46 u32 reserved1[30]; 47 u32 cmd; 48 u32 addr; 49 u32 data; 50 }; 51 52 check_member(rockchip_sfc_reg, data, 0x108); 53 54 /*SFC_CTRL*/ 55 #define SFC_DATA_WIDTH_SHIFT 12 56 #define SFC_DATA_WIDTH_MASK GENMASK(13, 12) 57 #define SFC_ADDR_WIDTH_SHIFT 10 58 #define SFC_ADDR_WIDTH_MASK GENMASK(11, 10) 59 #define SFC_CMD_WIDTH_SHIFT 8 60 #define SFC_CMD_WIDTH_MASK GENMASK(9, 8) 61 #define SFC_DATA_SHIFT_NEGETIVE BIT(1) 62 63 /*SFC_CMD*/ 64 #define SFC_DUMMY_BITS_SHIFT 8 65 #define SFC_RW_SHIFT 12 66 #define SFC_WR 1 67 #define SFC_RD 0 68 #define SFC_ADDR_BITS_SHIFT 14 69 #define SFC_ADDR_BITS_MASK GENMASK(15, 14) 70 #define SFC_ADDR_0BITS 0 71 #define SFC_ADDR_24BITS 1 72 #define SFC_ADDR_32BITS 2 73 #define SFC_ADDR_XBITS 3 74 #define SFC_TRB_SHIFT (16) 75 #define SFC_TRB_MASK GENMASK(29, 16) 76 77 /* Dma start trigger signal. Auto cleared after write */ 78 #define SFC_DMA_START BIT(0) 79 80 #define SFC_RESET BIT(0) 81 82 /*SFC_FSR*/ 83 #define SFC_RXLV_SHIFT (16) 84 #define SFC_RXLV_MASK GENMASK(20, 16) 85 #define SFC_TXLV_SHIFT (8) 86 #define SFC_TXLV_MASK GENMASK(12, 8) 87 #define SFC_RX_FULL BIT(3) /* rx fifo full */ 88 #define SFC_RX_EMPTY BIT(2) /* rx fifo empty */ 89 #define SFC_TX_EMPTY BIT(1) /* tx fifo empty */ 90 #define SFC_TX_FULL BIT(0) /* tx fifo full */ 91 92 #define SFC_BUSY BIT(0) /* sfc busy flag */ 93 94 /*SFC_RISR*/ 95 #define DMA_FINISH_INT BIT(7) /* dma interrupt */ 96 #define SPI_ERR_INT BIT(6) /* Nspi error interrupt */ 97 #define AHB_ERR_INT BIT(5) /* Ahb bus error interrupt */ 98 #define TRANS_FINISH_INT BIT(4) /* Transfer finish interrupt */ 99 #define TX_EMPTY_INT BIT(3) /* Tx fifo empty interrupt */ 100 #define TX_OF_INT BIT(2) /* Tx fifo overflow interrupt */ 101 #define RX_UF_INT BIT(1) /* Rx fifo underflow interrupt */ 102 #define RX_FULL_INT BIT(0) /* Rx fifo full interrupt */ 103 104 #define SFC_MAX_TRB (512 * 31) 105 106 #define SFC_MAX_RATE (150 * 1000 * 1000) 107 #define SFC_DEFAULT_RATE (80 * 1000 * 1000) 108 #define SFC_MIN_RATE (10 * 1000 * 1000) 109 110 enum rockchip_sfc_if_type { 111 IF_TYPE_STD, 112 IF_TYPE_DUAL, 113 IF_TYPE_QUAD, 114 }; 115 116 struct rockchip_sfc_platdata { 117 s32 frequency; 118 void *base; 119 }; 120 121 struct rockchip_sfc { 122 struct rockchip_sfc_reg *regbase; 123 struct clk clk; 124 unsigned int max_freq; 125 unsigned int mode; 126 unsigned int speed_hz; 127 u32 cmd; 128 u32 addr; 129 u8 addr_bits; 130 u8 dummy_bits; 131 u8 rw; 132 u32 trb; 133 }; 134 135 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 136 { 137 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 138 struct rockchip_sfc *sfc = dev_get_priv(bus); 139 ofnode subnode; 140 int ret; 141 142 plat->base = dev_read_addr_ptr(bus); 143 ret = clk_get_by_index(bus, 0, &sfc->clk); 144 if (ret < 0) { 145 printf("Could not get clock for %s: %d\n", bus->name, ret); 146 return ret; 147 } 148 149 subnode = dev_read_first_subnode(bus); 150 if (!ofnode_valid(subnode)) { 151 printf("Error: subnode with SPI flash config missing!\n"); 152 return -ENODEV; 153 } 154 155 plat->frequency = ofnode_read_u32_default(subnode, "spi-max-frequency", 156 100000000); 157 if (plat->frequency > SFC_MAX_RATE || plat->frequency < SFC_MIN_RATE) 158 plat->frequency = SFC_DEFAULT_RATE; 159 sfc->max_freq = plat->frequency; 160 161 return 0; 162 } 163 164 static int rockchip_sfc_probe(struct udevice *bus) 165 { 166 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 167 struct rockchip_sfc *sfc = dev_get_priv(bus); 168 struct dm_spi_bus *dm_spi_bus; 169 170 dm_spi_bus = bus->uclass_priv; 171 dm_spi_bus->max_hz = plat->frequency; 172 sfc->regbase = (struct rockchip_sfc_reg *)plat->base; 173 174 return 0; 175 } 176 177 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 178 { 179 struct rockchip_sfc_reg *regs = sfc->regbase; 180 int tbase = get_timer(0); 181 u32 rcvr; 182 int ret = 0; 183 184 writel(SFC_RESET, ®s->rcvr); 185 do { 186 rcvr = readl(®s->rcvr); 187 if (get_timer(tbase) > 1000) { 188 debug("sfc reset timeout\n"); 189 ret = -ETIMEDOUT; 190 break; 191 } 192 udelay(1); 193 } while (rcvr); 194 195 writel(0xFFFFFFFF, ®s->iclr); 196 197 debug("sfc reset\n"); 198 199 return ret; 200 } 201 202 /* The SFC_CTRL register is a global control register, 203 * when the controller is in busy state(SFC_SR), 204 * SFC_CTRL cannot be set. 205 */ 206 static int rockchip_sfc_wait_idle(struct rockchip_sfc *sfc, 207 u32 timeout_ms) 208 { 209 struct rockchip_sfc_reg *regs = sfc->regbase; 210 unsigned long tbase = get_timer(0); 211 u32 sr, fsr; 212 213 while (1) { 214 sr = readl(®s->sr); 215 fsr = readl(®s->fsr); 216 if ((fsr & SFC_TX_EMPTY) && 217 (fsr & SFC_RX_EMPTY) && 218 !(sr & SFC_BUSY)) 219 break; 220 if (get_timer(tbase) > timeout_ms) { 221 printf("waite sfc idle timeout(sr:0x%08x fsr:0x%08x)\n", 222 sr, fsr); 223 rockchip_sfc_reset(sfc); 224 return -ETIMEDOUT; 225 } 226 udelay(100); 227 } 228 229 return 0; 230 } 231 232 static u8 rockchip_sfc_get_if_type(struct rockchip_sfc *sfc) 233 { 234 int type = IF_TYPE_STD; 235 236 if (sfc->rw == SFC_WR) { 237 if (sfc->mode & SPI_TX_QUAD) 238 type = IF_TYPE_QUAD; 239 else if (sfc->mode & SPI_TX_DUAL) 240 type = IF_TYPE_DUAL; 241 else 242 type = IF_TYPE_STD; 243 } else { 244 if (sfc->mode & SPI_RX_QUAD) 245 type = IF_TYPE_QUAD; 246 else if (sfc->mode & SPI_RX_DUAL) 247 type = IF_TYPE_DUAL; 248 else 249 type = IF_TYPE_STD; 250 } 251 252 return type; 253 } 254 255 static void rockchip_sfc_setup_xfer(struct rockchip_sfc *sfc, u32 trb) 256 { 257 struct rockchip_sfc_reg *regs = sfc->regbase; 258 u32 val = 0x02; 259 u8 data_width = IF_TYPE_STD; 260 261 SFC_DBG("--- sfc.addr_bit %x\n", sfc->addr_bits); 262 263 if (sfc->addr_bits == SFC_ADDR_24BITS || 264 sfc->addr_bits == SFC_ADDR_32BITS) 265 data_width = rockchip_sfc_get_if_type(sfc); 266 267 val |= (data_width << SFC_DATA_WIDTH_SHIFT); 268 269 rockchip_sfc_wait_idle(sfc, 10); 270 271 SFC_DBG("--- sfc.ctrl %x\n", val); 272 writel(val, ®s->ctrl); 273 274 val = sfc->cmd; 275 val |= trb << SFC_TRB_SHIFT; 276 val |= sfc->rw << SFC_RW_SHIFT; 277 val |= sfc->addr_bits << SFC_ADDR_BITS_SHIFT; 278 val |= sfc->dummy_bits << SFC_DUMMY_BITS_SHIFT; 279 280 SFC_DBG("--- sfc.cmd %x\n", val); 281 writel(val, ®s->cmd); 282 283 if (sfc->addr_bits & SFC_ADDR_XBITS) { 284 SFC_DBG("--- sfc.addr %x\n", sfc->addr); 285 writel(sfc->addr, ®s->addr); 286 } 287 } 288 289 static int rockchip_sfc_dma_xfer(struct rockchip_sfc *sfc, void *buffer, size_t trb) 290 { 291 struct rockchip_sfc_reg *regs = sfc->regbase; 292 struct bounce_buffer bb; 293 unsigned int bb_flags; 294 int timeout = 1000; 295 int ret = 0; 296 int risr; 297 unsigned long tbase; 298 299 if (sfc->rw == SFC_WR) 300 bb_flags = GEN_BB_READ; 301 else 302 bb_flags = GEN_BB_WRITE; 303 304 ret = bounce_buffer_start(&bb, buffer, trb, bb_flags); 305 if (ret) 306 return ret; 307 308 rockchip_sfc_setup_xfer(sfc, bb.len_aligned); 309 310 writel(0xFFFFFFFF, ®s->iclr); 311 writel((unsigned long)bb.bounce_buffer, ®s->dmaaddr); 312 writel(SFC_DMA_START, ®s->dmatr); 313 314 tbase = get_timer(0); 315 do { 316 udelay(1); 317 risr = readl(®s->risr); 318 if (get_timer(tbase) > timeout) { 319 debug("dma timeout\n"); 320 ret = -ETIMEDOUT; 321 break; 322 } 323 } while (!(risr & TRANS_FINISH_INT)); 324 325 writel(0xFFFFFFFF, ®s->iclr); 326 327 bounce_buffer_stop(&bb); 328 329 return ret; 330 } 331 332 static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int rw, 333 u32 timeout) 334 { 335 struct rockchip_sfc_reg *regs = sfc->regbase; 336 unsigned long tbase = get_timer(0); 337 u8 level; 338 u32 fsr; 339 340 do { 341 fsr = readl(®s->fsr); 342 if (rw == SFC_WR) 343 level = (fsr & SFC_TXLV_MASK) >> SFC_TXLV_SHIFT; 344 else 345 level = (fsr & SFC_RXLV_MASK) >> SFC_RXLV_SHIFT; 346 if (get_timer(tbase) > timeout) 347 return -ETIMEDOUT; 348 udelay(1); 349 } while (!level); 350 351 return level; 352 } 353 354 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 355 { 356 struct rockchip_sfc_reg *regs = sfc->regbase; 357 u32 bytes = len & 0x3; 358 u32 words = len >> 2; 359 int tx_level = 0; 360 u32 val = 0; 361 u8 count; 362 363 while (words) { 364 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 365 if (tx_level <= 0) 366 return tx_level; 367 count = min(words, (u32)tx_level); 368 writesl(®s->data, buf, count); 369 buf += count; 370 words -= count; 371 } 372 373 /* handle the last non 4byte aligned bytes */ 374 if (bytes) { 375 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 376 if (tx_level <= 0) 377 return tx_level; 378 memcpy(&val, buf, bytes); 379 writel(val, ®s->data); 380 } 381 382 return 0; 383 } 384 385 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 386 { 387 struct rockchip_sfc_reg *regs = sfc->regbase; 388 u32 bytes = len & 0x3; 389 u32 words = len >> 2; 390 int rx_level = 0; 391 u32 count; 392 u32 val; 393 394 while (words) { 395 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 396 if (rx_level <= 0) 397 return rx_level; 398 count = min(words, (u32)rx_level); 399 readsl(®s->data, buf, count); 400 buf += count; 401 words -= count; 402 } 403 404 /* handle the last non 4 bytes aligned bytes */ 405 if (bytes) { 406 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 407 if (rx_level <= 0) 408 return rx_level; 409 val = readl(®s->data); 410 memcpy(buf, &val, bytes); 411 } 412 413 return 0; 414 } 415 416 static int rockchip_sfc_pio_xfer(struct rockchip_sfc *sfc, void *buf, u32 len) 417 { 418 int ret = 0; 419 420 rockchip_sfc_setup_xfer(sfc, len); 421 422 if (len) { 423 if (sfc->rw == SFC_WR) 424 ret = rockchip_sfc_write_fifo(sfc, (u32 *)buf, len); 425 else 426 ret = rockchip_sfc_read_fifo(sfc, (u32 *)buf, len); 427 } 428 429 return ret; 430 } 431 432 static int rockchip_sfc_read(struct rockchip_sfc *sfc, u32 offset, 433 void *buf, size_t len) 434 { 435 u32 dma_trans; 436 u32 trb; 437 u8 bytes; 438 int ret; 439 440 if (len >= ARCH_DMA_MINALIGN) { 441 bytes = len & (ARCH_DMA_MINALIGN - 1); 442 dma_trans = len - bytes; 443 } else { 444 dma_trans = 0; 445 bytes = len; 446 } 447 448 while (dma_trans) { 449 trb = min_t(size_t, dma_trans, SFC_MAX_TRB); 450 ret = rockchip_sfc_dma_xfer(sfc, buf, trb); 451 if (ret < 0) 452 return ret; 453 dma_trans -= trb; 454 sfc->addr += trb; 455 buf += trb; 456 } 457 458 /* 459 * transfer the last non dma anligned byte by pio mode 460 */ 461 if (bytes) 462 ret = rockchip_sfc_pio_xfer(sfc, buf, bytes); 463 464 return 0; 465 } 466 467 static int rockchip_sfc_write(struct rockchip_sfc *sfc, u32 offset, 468 void *buf, size_t len) 469 { 470 if (len > SFC_MAX_TRB) { 471 printf("out of the max sfc trb"); 472 return -EINVAL; 473 } 474 475 if (len && !(len & (ARCH_DMA_MINALIGN - 1))) 476 return rockchip_sfc_dma_xfer(sfc, buf, len); 477 else 478 return rockchip_sfc_pio_xfer(sfc, buf, len); 479 480 return 0; 481 } 482 483 static int rockchip_sfc_do_xfer(struct rockchip_sfc *sfc, void *buf, size_t len) 484 { 485 if (sfc->rw) 486 return rockchip_sfc_write(sfc, sfc->addr, buf, len); 487 else 488 return rockchip_sfc_read(sfc, sfc->addr, buf, len); 489 } 490 491 static int rockchip_sfc_xfer(struct udevice *dev, unsigned int bitlen, 492 const void *dout, void *din, unsigned long flags) 493 { 494 struct udevice *bus = dev->parent; 495 struct rockchip_sfc *sfc = dev_get_priv(bus); 496 int len = bitlen >> 3; 497 u8 *pcmd = (u8 *)dout; 498 void *data_buf; 499 int ret = 0; 500 501 if (flags & SPI_XFER_BEGIN) { 502 sfc->cmd = pcmd[0]; 503 switch (len) { 504 case 6: /* Nor >16MB 0x6b dummy op */ 505 sfc->addr_bits = SFC_ADDR_32BITS; 506 sfc->dummy_bits = 8; 507 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 508 break; 509 case 5: /* Nor <=16MB 0x6b dummy op, Nor >16MB no dummy op */ 510 if (sfc->cmd == 0x6b) { 511 sfc->addr_bits = SFC_ADDR_24BITS; 512 sfc->dummy_bits = 8; 513 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 514 } else { 515 sfc->addr_bits = SFC_ADDR_32BITS; 516 sfc->dummy_bits = 0; 517 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 518 } 519 break; 520 case 4: /* Nand erase and read, Nor <=16MB no dummy op */ 521 sfc->addr_bits = SFC_ADDR_24BITS; 522 sfc->dummy_bits = 0; 523 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 524 break; 525 case 3: /* Nand prog, */ 526 sfc->addr_bits = SFC_ADDR_XBITS; 527 sfc->dummy_bits = 0; 528 sfc->addr = pcmd[2] | pcmd[1] << 8; 529 break; 530 case 2: /* Nand read/write feature */ 531 sfc->addr_bits = SFC_ADDR_XBITS; 532 sfc->dummy_bits = 0; 533 sfc->addr = pcmd[1]; 534 break; 535 default: /* Nand/Nor Read/Write status */ 536 sfc->addr_bits = SFC_ADDR_0BITS; 537 sfc->dummy_bits = 0; 538 sfc->addr = 0; 539 break; 540 } 541 SFC_DBG("%s %d %x %d %d %x\n", __func__, len, sfc->cmd, sfc->addr_bits, 542 sfc->dummy_bits, sfc->addr); 543 } 544 if (flags & SPI_XFER_END) { 545 if (din) { 546 sfc->rw = SFC_RD; 547 data_buf = din; 548 } else { 549 sfc->rw = SFC_WR; 550 data_buf = (void *)dout; 551 } 552 553 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 554 len = 0; 555 data_buf = NULL; 556 } 557 558 ret = rockchip_sfc_do_xfer(sfc, data_buf, len); 559 } 560 561 return ret; 562 } 563 564 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 565 { 566 struct rockchip_sfc *sfc = dev_get_priv(bus); 567 568 if (speed > sfc->max_freq) 569 speed = sfc->max_freq; 570 571 sfc->speed_hz = speed; 572 clk_set_rate(&sfc->clk, sfc->speed_hz); 573 SFC_DBG("%s clk= %ld\n", __func__, clk_get_rate(&sfc->clk)); 574 575 return 0; 576 } 577 578 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 579 { 580 struct rockchip_sfc *sfc = dev_get_priv(bus); 581 582 sfc->mode = mode; 583 584 return 0; 585 } 586 587 static const struct dm_spi_ops rockchip_sfc_ops = { 588 .xfer = rockchip_sfc_xfer, 589 .set_speed = rockchip_sfc_set_speed, 590 .set_mode = rockchip_sfc_set_mode, 591 }; 592 593 static const struct udevice_id rockchip_sfc_ids[] = { 594 { .compatible = "rockchip,sfc" }, 595 { } 596 }; 597 598 U_BOOT_DRIVER(rockchip_sfc_driver) = { 599 .name = "rockchip_sfc", 600 .id = UCLASS_SPI, 601 .of_match = rockchip_sfc_ids, 602 .ops = &rockchip_sfc_ops, 603 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 604 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc_platdata), 605 .priv_auto_alloc_size = sizeof(struct rockchip_sfc), 606 .probe = rockchip_sfc_probe, 607 }; 608