1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Serial Flash Controller Driver 4 * 5 * Copyright (c) 2017-2021, Rockchip Inc. 6 * Author: Shawn Lin <shawn.lin@rock-chips.com> 7 * Chris Morgan <macromorgan@hotmail.com> 8 * Jon Lin <Jon.lin@rock-chips.com> 9 */ 10 11 #include <asm/io.h> 12 #include <bouncebuf.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <linux/bitops.h> 16 #include <linux/delay.h> 17 #include <linux/iopoll.h> 18 #include <spi.h> 19 #include <spi-mem.h> 20 21 /* System control */ 22 #define SFC_CTRL 0x0 23 #define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) 24 #define SFC_CTRL_CMD_BITS_SHIFT 8 25 #define SFC_CTRL_ADDR_BITS_SHIFT 10 26 #define SFC_CTRL_DATA_BITS_SHIFT 12 27 28 /* Interrupt mask */ 29 #define SFC_IMR 0x4 30 #define SFC_IMR_RX_FULL BIT(0) 31 #define SFC_IMR_RX_UFLOW BIT(1) 32 #define SFC_IMR_TX_OFLOW BIT(2) 33 #define SFC_IMR_TX_EMPTY BIT(3) 34 #define SFC_IMR_TRAN_FINISH BIT(4) 35 #define SFC_IMR_BUS_ERR BIT(5) 36 #define SFC_IMR_NSPI_ERR BIT(6) 37 #define SFC_IMR_DMA BIT(7) 38 39 /* Interrupt clear */ 40 #define SFC_ICLR 0x8 41 #define SFC_ICLR_RX_FULL BIT(0) 42 #define SFC_ICLR_RX_UFLOW BIT(1) 43 #define SFC_ICLR_TX_OFLOW BIT(2) 44 #define SFC_ICLR_TX_EMPTY BIT(3) 45 #define SFC_ICLR_TRAN_FINISH BIT(4) 46 #define SFC_ICLR_BUS_ERR BIT(5) 47 #define SFC_ICLR_NSPI_ERR BIT(6) 48 #define SFC_ICLR_DMA BIT(7) 49 50 /* FIFO threshold level */ 51 #define SFC_FTLR 0xc 52 #define SFC_FTLR_TX_SHIFT 0 53 #define SFC_FTLR_TX_MASK 0x1f 54 #define SFC_FTLR_RX_SHIFT 8 55 #define SFC_FTLR_RX_MASK 0x1f 56 57 /* Reset FSM and FIFO */ 58 #define SFC_RCVR 0x10 59 #define SFC_RCVR_RESET BIT(0) 60 61 /* Enhanced mode */ 62 #define SFC_AX 0x14 63 64 /* Address Bit number */ 65 #define SFC_ABIT 0x18 66 67 /* Interrupt status */ 68 #define SFC_ISR 0x1c 69 #define SFC_ISR_RX_FULL_SHIFT BIT(0) 70 #define SFC_ISR_RX_UFLOW_SHIFT BIT(1) 71 #define SFC_ISR_TX_OFLOW_SHIFT BIT(2) 72 #define SFC_ISR_TX_EMPTY_SHIFT BIT(3) 73 #define SFC_ISR_TX_FINISH_SHIFT BIT(4) 74 #define SFC_ISR_BUS_ERR_SHIFT BIT(5) 75 #define SFC_ISR_NSPI_ERR_SHIFT BIT(6) 76 #define SFC_ISR_DMA_SHIFT BIT(7) 77 78 /* FIFO status */ 79 #define SFC_FSR 0x20 80 #define SFC_FSR_TX_IS_FULL BIT(0) 81 #define SFC_FSR_TX_IS_EMPTY BIT(1) 82 #define SFC_FSR_RX_IS_EMPTY BIT(2) 83 #define SFC_FSR_RX_IS_FULL BIT(3) 84 #define SFC_FSR_TXLV_MASK GENMASK(12, 8) 85 #define SFC_FSR_TXLV_SHIFT 8 86 #define SFC_FSR_RXLV_MASK GENMASK(20, 16) 87 #define SFC_FSR_RXLV_SHIFT 16 88 89 /* FSM status */ 90 #define SFC_SR 0x24 91 #define SFC_SR_IS_IDLE 0x0 92 #define SFC_SR_IS_BUSY 0x1 93 94 /* Raw interrupt status */ 95 #define SFC_RISR 0x28 96 #define SFC_RISR_RX_FULL BIT(0) 97 #define SFC_RISR_RX_UNDERFLOW BIT(1) 98 #define SFC_RISR_TX_OVERFLOW BIT(2) 99 #define SFC_RISR_TX_EMPTY BIT(3) 100 #define SFC_RISR_TRAN_FINISH BIT(4) 101 #define SFC_RISR_BUS_ERR BIT(5) 102 #define SFC_RISR_NSPI_ERR BIT(6) 103 #define SFC_RISR_DMA BIT(7) 104 105 /* Version */ 106 #define SFC_VER 0x2C 107 #define SFC_VER_3 0x3 108 #define SFC_VER_4 0x4 109 #define SFC_VER_5 0x5 110 #define SFC_VER_6 0x6 111 112 /* Delay line controller resiter */ 113 #define SFC_DLL_CTRL0 0x3C 114 #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) 115 #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU 116 #define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU 117 118 /* Master trigger */ 119 #define SFC_DMA_TRIGGER 0x80 120 #define SFC_DMA_TRIGGER_START 1 121 122 /* Src or Dst addr for master */ 123 #define SFC_DMA_ADDR 0x84 124 125 /* Length control register extension 32GB */ 126 #define SFC_LEN_CTRL 0x88 127 #define SFC_LEN_CTRL_TRB_SEL 1 128 #define SFC_LEN_EXT 0x8C 129 130 /* Command */ 131 #define SFC_CMD 0x100 132 #define SFC_CMD_IDX_SHIFT 0 133 #define SFC_CMD_DUMMY_SHIFT 8 134 #define SFC_CMD_DIR_SHIFT 12 135 #define SFC_CMD_DIR_RD 0 136 #define SFC_CMD_DIR_WR 1 137 #define SFC_CMD_ADDR_SHIFT 14 138 #define SFC_CMD_ADDR_0BITS 0 139 #define SFC_CMD_ADDR_24BITS 1 140 #define SFC_CMD_ADDR_32BITS 2 141 #define SFC_CMD_ADDR_XBITS 3 142 #define SFC_CMD_TRAN_BYTES_SHIFT 16 143 #define SFC_CMD_CS_SHIFT 30 144 145 /* Address */ 146 #define SFC_ADDR 0x104 147 148 /* Data */ 149 #define SFC_DATA 0x108 150 151 /* The controller and documentation reports that it supports up to 4 CS 152 * devices (0-3), however I have only been able to test a single CS (CS 0) 153 * due to the configuration of my device. 154 */ 155 #define SFC_MAX_CHIPSELECT_NUM 4 156 157 /* The SFC can transfer max 16KB - 1 at one time 158 * we set it to 15.5KB here for alignment. 159 */ 160 #define SFC_MAX_IOSIZE_VER3 (512 * 31) 161 162 #define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU) 163 164 /* DMA is only enabled for large data transmission */ 165 #define SFC_DMA_TRANS_THRETHOLD (0x40) 166 167 /* Maximum clock values from datasheet suggest keeping clock value under 168 * 150MHz. No minimum or average value is suggested. 169 */ 170 #define SFC_MAX_SPEED (150 * 1000 * 1000) 171 #define SFC_DLL_THRESHOLD_RATE (50 * 1000 * 1000) 172 173 #define SFC_DLL_TRANING_STEP 10 /* Training step */ 174 #define SFC_DLL_TRANING_VALID_WINDOW 80 /* Training Valid DLL winbow */ 175 176 struct rockchip_sfc { 177 struct udevice *dev; 178 void __iomem *regbase; 179 struct clk hclk; 180 struct clk clk; 181 u32 max_freq; 182 u32 speed; 183 bool use_dma; 184 u32 max_iosize; 185 u16 version; 186 187 u32 last_async_size; 188 u32 async; 189 u32 dll_cells; 190 u32 max_dll_cells; 191 }; 192 193 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 194 { 195 int err; 196 u32 status; 197 198 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); 199 200 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, 201 !(status & SFC_RCVR_RESET), 202 1000000); 203 if (err) 204 printf("SFC reset never finished\n"); 205 206 /* Still need to clear the masked interrupt from RISR */ 207 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 208 209 return err; 210 } 211 212 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 213 { 214 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); 215 } 216 217 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) 218 { 219 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 220 return SFC_MAX_IOSIZE_VER4; 221 222 return SFC_MAX_IOSIZE_VER3; 223 } 224 225 static u32 rockchip_sfc_get_max_dll_cells(struct rockchip_sfc *sfc) 226 { 227 switch (rockchip_sfc_get_version(sfc)) { 228 case SFC_VER_6: 229 case SFC_VER_5: 230 return SFC_DLL_CTRL0_DLL_MAX_VER5; 231 case SFC_VER_4: 232 return SFC_DLL_CTRL0_DLL_MAX_VER4; 233 default: 234 return 0; 235 } 236 } 237 238 static __maybe_unused void rockchip_sfc_set_delay_lines(struct rockchip_sfc *sfc, u16 cells) 239 { 240 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc); 241 u32 val = 0; 242 243 if (cells > cell_max) 244 cells = cell_max; 245 246 if (cells) 247 val = SFC_DLL_CTRL0_SCLK_SMP_DLL | cells; 248 249 writel(val, sfc->regbase + SFC_DLL_CTRL0); 250 } 251 252 static int rockchip_sfc_init(struct rockchip_sfc *sfc) 253 { 254 writel(0, sfc->regbase + SFC_CTRL); 255 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 256 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); 257 258 return 0; 259 } 260 261 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 262 { 263 struct rockchip_sfc *sfc = dev_get_platdata(bus); 264 265 sfc->regbase = dev_read_addr_ptr(bus); 266 if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma")) 267 sfc->use_dma = false; 268 else 269 sfc->use_dma = true; 270 #if CONFIG_IS_ENABLED(CLK) 271 int ret; 272 273 ret = clk_get_by_index(bus, 0, &sfc->clk); 274 if (ret < 0) { 275 printf("Could not get clock for %s: %d\n", bus->name, ret); 276 return ret; 277 } 278 279 ret = clk_get_by_index(bus, 1, &sfc->hclk); 280 if (ret < 0) { 281 printf("Could not get ahb clock for %s: %d\n", bus->name, ret); 282 return ret; 283 } 284 #endif 285 286 return 0; 287 } 288 289 static int rockchip_sfc_probe(struct udevice *bus) 290 { 291 struct rockchip_sfc *sfc = dev_get_platdata(bus); 292 int ret; 293 294 #if CONFIG_IS_ENABLED(CLK) 295 ret = clk_enable(&sfc->hclk); 296 if (ret) 297 dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); 298 299 ret = clk_enable(&sfc->clk); 300 if (ret) 301 dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); 302 #endif 303 304 ret = rockchip_sfc_init(sfc); 305 if (ret) 306 goto err_init; 307 308 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); 309 sfc->version = rockchip_sfc_get_version(sfc); 310 sfc->max_freq = SFC_MAX_SPEED; 311 sfc->dev = bus; 312 313 return 0; 314 315 err_init: 316 #if CONFIG_IS_ENABLED(CLK) 317 clk_disable(&sfc->clk); 318 clk_disable(&sfc->hclk); 319 #endif 320 321 return ret; 322 } 323 324 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 325 { 326 int ret = 0; 327 u32 status; 328 329 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 330 status & SFC_FSR_TXLV_MASK, 331 timeout_us); 332 if (ret) { 333 dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); 334 335 return -ETIMEDOUT; 336 } 337 338 return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; 339 } 340 341 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 342 { 343 int ret = 0; 344 u32 status; 345 346 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 347 status & SFC_FSR_RXLV_MASK, 348 timeout_us); 349 if (ret) { 350 dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); 351 352 return -ETIMEDOUT; 353 } 354 355 return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; 356 } 357 358 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) 359 { 360 if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { 361 /* 362 * SFC not support output DUMMY cycles right after CMD cycles, so 363 * treat it as ADDR cycles. 364 */ 365 op->addr.nbytes = op->dummy.nbytes; 366 op->addr.buswidth = op->dummy.buswidth; 367 op->addr.val = 0xFFFFFFFFF; 368 369 op->dummy.nbytes = 0; 370 } 371 } 372 373 static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout) 374 { 375 unsigned long tbase; 376 377 /* Wait for the DMA interrupt status */ 378 tbase = get_timer(0); 379 while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) { 380 if (get_timer(tbase) > timeout) { 381 printf("dma timeout\n"); 382 rockchip_sfc_reset(sfc); 383 384 return -ETIMEDOUT; 385 } 386 387 udelay(1); 388 } 389 390 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 391 392 return 0; 393 } 394 395 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, 396 struct spi_slave *mem, 397 const struct spi_mem_op *op, 398 u32 len) 399 { 400 struct dm_spi_slave_platdata *plat = dev_get_platdata(sfc->dev); 401 u32 ctrl = 0, cmd = 0; 402 403 /* set CMD */ 404 cmd = op->cmd.opcode; 405 ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); 406 407 /* set ADDR */ 408 if (op->addr.nbytes) { 409 if (op->addr.nbytes == 4) { 410 cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; 411 } else if (op->addr.nbytes == 3) { 412 cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; 413 } else { 414 cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; 415 writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); 416 } 417 418 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); 419 } 420 421 /* set DUMMY */ 422 if (op->dummy.nbytes) { 423 if (op->dummy.buswidth == 4) 424 cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; 425 else if (op->dummy.buswidth == 2) 426 cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; 427 else 428 cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; 429 } 430 431 /* set DATA */ 432 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ 433 writel(len, sfc->regbase + SFC_LEN_EXT); 434 else 435 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; 436 if (len) { 437 if (op->data.dir == SPI_MEM_DATA_OUT) 438 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 439 440 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); 441 } 442 if (!len && op->addr.nbytes) 443 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 444 445 /* set the Controller */ 446 ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; 447 cmd |= plat->cs << SFC_CMD_CS_SHIFT; 448 449 dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", 450 op->addr.nbytes, op->addr.buswidth, 451 op->dummy.nbytes, op->dummy.buswidth); 452 dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", 453 ctrl, cmd, op->addr.val, len); 454 455 writel(ctrl, sfc->regbase + SFC_CTRL); 456 writel(cmd, sfc->regbase + SFC_CMD); 457 if (op->addr.nbytes) 458 writel(op->addr.val, sfc->regbase + SFC_ADDR); 459 460 return 0; 461 } 462 463 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) 464 { 465 u8 bytes = len & 0x3; 466 u32 dwords; 467 int tx_level; 468 u32 write_words; 469 u32 tmp = 0; 470 471 dwords = len >> 2; 472 while (dwords) { 473 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 474 if (tx_level < 0) 475 return tx_level; 476 write_words = min_t(u32, tx_level, dwords); 477 writesl(sfc->regbase + SFC_DATA, buf, write_words); 478 buf += write_words << 2; 479 dwords -= write_words; 480 } 481 482 /* write the rest non word aligned bytes */ 483 if (bytes) { 484 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 485 if (tx_level < 0) 486 return tx_level; 487 memcpy(&tmp, buf, bytes); 488 writel(tmp, sfc->regbase + SFC_DATA); 489 } 490 491 return len; 492 } 493 494 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) 495 { 496 u8 bytes = len & 0x3; 497 u32 dwords; 498 u8 read_words; 499 int rx_level; 500 int tmp; 501 502 /* word aligned access only */ 503 dwords = len >> 2; 504 while (dwords) { 505 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 506 if (rx_level < 0) 507 return rx_level; 508 read_words = min_t(u32, rx_level, dwords); 509 readsl(sfc->regbase + SFC_DATA, buf, read_words); 510 buf += read_words << 2; 511 dwords -= read_words; 512 } 513 514 /* read the rest non word aligned bytes */ 515 if (bytes) { 516 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 517 if (rx_level < 0) 518 return rx_level; 519 tmp = readl(sfc->regbase + SFC_DATA); 520 memcpy(buf, &tmp, bytes); 521 } 522 523 return len; 524 } 525 526 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) 527 { 528 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 529 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); 530 writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); 531 532 return len; 533 } 534 535 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, 536 const struct spi_mem_op *op, u32 len) 537 { 538 dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); 539 540 if (op->data.dir == SPI_MEM_DATA_OUT) 541 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); 542 else 543 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); 544 } 545 546 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, 547 const struct spi_mem_op *op, u32 len) 548 { 549 struct bounce_buffer bb; 550 unsigned int bb_flags; 551 void *dma_buf; 552 int ret; 553 554 dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); 555 556 if (op->data.dir == SPI_MEM_DATA_OUT) { 557 dma_buf = (void *)op->data.buf.out; 558 bb_flags = GEN_BB_READ; 559 } else { 560 dma_buf = (void *)op->data.buf.in; 561 bb_flags = GEN_BB_WRITE; 562 } 563 564 ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags); 565 if (ret) 566 return ret; 567 568 ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len); 569 rockchip_sfc_wait_for_dma_finished(sfc, len * 10); 570 bounce_buffer_stop(&bb); 571 572 return ret; 573 } 574 575 static int rockchip_sfc_xfer_data_dma_async(struct rockchip_sfc *sfc, 576 const struct spi_mem_op *op, u32 len) 577 { 578 void *dma_buf; 579 580 if (op->data.dir == SPI_MEM_DATA_OUT) 581 dma_buf = (void *)op->data.buf.out; 582 else 583 dma_buf = (void *)op->data.buf.in; 584 585 dev_dbg(sfc->dev, "xfer_dma_async len=%x %p\n", len, dma_buf); 586 587 flush_dcache_range((unsigned long)dma_buf, 588 (unsigned long)dma_buf + len); 589 590 rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)dma_buf, len); 591 sfc->last_async_size = len; 592 593 return 0; 594 } 595 596 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) 597 { 598 int ret = 0; 599 u32 status; 600 601 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, 602 !(status & SFC_SR_IS_BUSY), 603 timeout_us); 604 if (ret) { 605 dev_err(sfc->dev, "wait sfc idle timeout\n"); 606 rockchip_sfc_reset(sfc); 607 608 ret = -EIO; 609 } 610 611 return ret; 612 } 613 614 static int rockchip_sfc_exec_op(struct spi_slave *mem, 615 const struct spi_mem_op *op) 616 { 617 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 618 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 619 int ret; 620 621 /* Wait for last async transfer finished */ 622 if (sfc->last_async_size) { 623 rockchip_sfc_wait_for_dma_finished(sfc, sfc->last_async_size); 624 sfc->last_async_size = 0; 625 } 626 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 627 rockchip_sfc_xfer_setup(sfc, mem, op, len); 628 if (len) { 629 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) { 630 if (mem->mode & SPI_DMA_PREPARE) 631 return rockchip_sfc_xfer_data_dma_async(sfc, op, len); 632 ret = rockchip_sfc_xfer_data_dma(sfc, op, len); 633 } else { 634 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 635 } 636 637 if (ret != len) { 638 dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); 639 640 return -EIO; 641 } 642 } 643 644 return rockchip_sfc_xfer_done(sfc, 100000); 645 } 646 647 static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op) 648 { 649 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 650 651 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); 652 653 return 0; 654 } 655 656 #if CONFIG_IS_ENABLED(CLK) 657 static int rockchip_sfc_exec_op_bypass(struct rockchip_sfc *sfc, 658 struct spi_slave *mem, 659 const struct spi_mem_op *op) 660 { 661 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 662 u32 ret; 663 664 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 665 rockchip_sfc_xfer_setup(sfc, mem, op, len); 666 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 667 if (ret != len) { 668 dev_err(sfc->dev, "xfer data failed ret %d\n", ret); 669 670 return -EIO; 671 } 672 673 return rockchip_sfc_xfer_done(sfc, 100000); 674 } 675 676 static void rockchip_sfc_delay_lines_tuning(struct rockchip_sfc *sfc, struct spi_slave *mem) 677 { 678 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1), 679 SPI_MEM_OP_NO_ADDR, 680 SPI_MEM_OP_NO_DUMMY, 681 SPI_MEM_OP_DATA_IN(3, NULL, 1)); 682 u8 id[3], id_temp[3]; 683 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc); 684 u16 right, left = 0; 685 u16 step = SFC_DLL_TRANING_STEP; 686 bool dll_valid = false; 687 688 clk_set_rate(&sfc->clk, SFC_DLL_THRESHOLD_RATE); 689 op.data.buf.in = &id; 690 rockchip_sfc_exec_op_bypass(sfc, mem, &op); 691 if ((0xFF == id[0] && 0xFF == id[1]) || 692 (0x00 == id[0] && 0x00 == id[1])) { 693 dev_dbg(sfc->dev, "no dev, dll by pass\n"); 694 clk_set_rate(&sfc->clk, sfc->speed); 695 696 return; 697 } 698 699 clk_set_rate(&sfc->clk, sfc->speed); 700 op.data.buf.in = &id_temp; 701 for (right = 0; right <= cell_max; right += step) { 702 int ret; 703 704 rockchip_sfc_set_delay_lines(sfc, right); 705 rockchip_sfc_exec_op_bypass(sfc, mem, &op); 706 dev_dbg(sfc->dev, "dll read flash id:%x %x %x\n", 707 id_temp[0], id_temp[1], id_temp[2]); 708 709 ret = memcmp(&id, &id_temp, 3); 710 if (dll_valid && ret) { 711 right -= step; 712 713 break; 714 } 715 if (!dll_valid && !ret) 716 left = right; 717 718 if (!ret) 719 dll_valid = true; 720 721 /* Add cell_max to loop */ 722 if (right == cell_max) 723 break; 724 if (right + step > cell_max) 725 right = cell_max - step; 726 } 727 728 if (dll_valid && (right - left) >= SFC_DLL_TRANING_VALID_WINDOW) { 729 if (left == 0 && right < cell_max) 730 sfc->dll_cells = left + (right - left) * 2 / 5; 731 else 732 sfc->dll_cells = left + (right - left) / 2; 733 } else { 734 sfc->dll_cells = 0; 735 } 736 737 if (sfc->dll_cells) { 738 dev_dbg(sfc->dev, "%d %d %d dll training success in %dMHz max_cells=%u sfc_ver=%d\n", 739 left, right, sfc->dll_cells, sfc->speed, 740 rockchip_sfc_get_max_dll_cells(sfc), rockchip_sfc_get_version(sfc)); 741 rockchip_sfc_set_delay_lines(sfc, (u16)sfc->dll_cells); 742 } else { 743 dev_err(sfc->dev, "%d %d dll training failed in %dMHz, reduce the speed\n", 744 left, right, sfc->speed); 745 rockchip_sfc_set_delay_lines(sfc, 0); 746 clk_set_rate(&sfc->clk, SFC_DLL_THRESHOLD_RATE); 747 sfc->speed = clk_get_rate(&sfc->clk); 748 } 749 } 750 751 #endif 752 753 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 754 { 755 struct rockchip_sfc *sfc = dev_get_platdata(bus); 756 757 if (speed > sfc->max_freq) 758 speed = sfc->max_freq; 759 760 if (speed == sfc->speed) 761 return 0; 762 763 #if CONFIG_IS_ENABLED(CLK) 764 int ret = clk_set_rate(&sfc->clk, speed); 765 766 if (ret < 0) { 767 dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", 768 speed); 769 return ret; 770 } 771 sfc->speed = speed; 772 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) { 773 if (clk_get_rate(&sfc->clk) > SFC_DLL_THRESHOLD_RATE) 774 rockchip_sfc_delay_lines_tuning(sfc, NULL); 775 else 776 rockchip_sfc_set_delay_lines(sfc, 0); 777 } 778 779 dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n", 780 sfc->speed, clk_get_rate(&sfc->clk)); 781 #else 782 dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); 783 #endif 784 return 0; 785 } 786 787 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 788 { 789 return 0; 790 } 791 792 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { 793 .adjust_op_size = rockchip_sfc_adjust_op_size, 794 .exec_op = rockchip_sfc_exec_op, 795 }; 796 797 static const struct dm_spi_ops rockchip_sfc_ops = { 798 .mem_ops = &rockchip_sfc_mem_ops, 799 .set_speed = rockchip_sfc_set_speed, 800 .set_mode = rockchip_sfc_set_mode, 801 }; 802 803 static const struct udevice_id rockchip_sfc_ids[] = { 804 { .compatible = "rockchip,sfc"}, 805 {}, 806 }; 807 808 U_BOOT_DRIVER(rockchip_sfc_driver) = { 809 .name = "rockchip_sfc", 810 .id = UCLASS_SPI, 811 .of_match = rockchip_sfc_ids, 812 .ops = &rockchip_sfc_ops, 813 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 814 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc), 815 .probe = rockchip_sfc_probe, 816 }; 817