1 /* 2 * SFC driver for rockchip 3 * 4 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 5 * Yifeng.zhao, Software Engineering, <zhao0116@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <bouncebuf.h> 12 #include <clk.h> 13 #include <dm.h> 14 #include <dt-structs.h> 15 #include <errno.h> 16 #include <spi.h> 17 #include <linux/errno.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/periph.h> 21 #include <dm/pinctrl.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #ifdef SFC_DEBUG 26 #define SFC_DBG printf 27 #else 28 #define SFC_DBG(args...) 29 #endif 30 31 struct rockchip_sfc_reg { 32 u32 ctrl; 33 u32 imr; 34 u32 iclr; 35 u32 ftlr; 36 u32 rcvr; 37 u32 ax; 38 u32 abit; 39 u32 isr; 40 u32 fsr; 41 u32 sr; 42 u32 risr; 43 u32 ver; 44 u32 reserved[20]; 45 u32 dmatr; 46 u32 dmaaddr; 47 u32 len_ctrl; 48 u32 len_ext; 49 u32 reserved1[28]; 50 u32 cmd; 51 u32 addr; 52 u32 data; 53 }; 54 55 check_member(rockchip_sfc_reg, data, 0x108); 56 57 /*SFC_CTRL*/ 58 #define SFC_DATA_WIDTH_SHIFT 12 59 #define SFC_DATA_WIDTH_MASK GENMASK(13, 12) 60 #define SFC_ADDR_WIDTH_SHIFT 10 61 #define SFC_ADDR_WIDTH_MASK GENMASK(11, 10) 62 #define SFC_CMD_WIDTH_SHIFT 8 63 #define SFC_CMD_WIDTH_MASK GENMASK(9, 8) 64 #define SFC_DATA_SHIFT_NEGETIVE BIT(1) 65 66 /*SFC_CMD*/ 67 #define SFC_DUMMY_BITS_SHIFT 8 68 #define SFC_RW_SHIFT 12 69 #define SFC_WR 1 70 #define SFC_RD 0 71 #define SFC_ADDR_BITS_SHIFT 14 72 #define SFC_ADDR_BITS_MASK GENMASK(15, 14) 73 #define SFC_ADDR_0BITS 0 74 #define SFC_ADDR_24BITS 1 75 #define SFC_ADDR_32BITS 2 76 #define SFC_ADDR_XBITS 3 77 #define SFC_TRB_SHIFT (16) 78 #define SFC_TRB_MASK GENMASK(29, 16) 79 80 /* Dma start trigger signal. Auto cleared after write */ 81 #define SFC_DMA_START BIT(0) 82 83 #define SFC_RESET BIT(0) 84 85 /*SFC_FSR*/ 86 #define SFC_RXLV_SHIFT (16) 87 #define SFC_RXLV_MASK GENMASK(20, 16) 88 #define SFC_TXLV_SHIFT (8) 89 #define SFC_TXLV_MASK GENMASK(12, 8) 90 #define SFC_RX_FULL BIT(3) /* rx fifo full */ 91 #define SFC_RX_EMPTY BIT(2) /* rx fifo empty */ 92 #define SFC_TX_EMPTY BIT(1) /* tx fifo empty */ 93 #define SFC_TX_FULL BIT(0) /* tx fifo full */ 94 95 #define SFC_BUSY BIT(0) /* sfc busy flag */ 96 97 /*SFC_RISR*/ 98 #define DMA_FINISH_INT BIT(7) /* dma interrupt */ 99 #define SPI_ERR_INT BIT(6) /* Nspi error interrupt */ 100 #define AHB_ERR_INT BIT(5) /* Ahb bus error interrupt */ 101 #define TRANS_FINISH_INT BIT(4) /* Transfer finish interrupt */ 102 #define TX_EMPTY_INT BIT(3) /* Tx fifo empty interrupt */ 103 #define TX_OF_INT BIT(2) /* Tx fifo overflow interrupt */ 104 #define RX_UF_INT BIT(1) /* Rx fifo underflow interrupt */ 105 #define RX_FULL_INT BIT(0) /* Rx fifo full interrupt */ 106 107 #define SFC_MAX_TRB_VER3 (512 * 31) 108 #define SFC_MAX_TRB_VER4 (0xFFFFFFFF) 109 110 #define SFC_MAX_RATE (100 * 1000 * 1000) 111 #define SFC_DEFAULT_RATE (80 * 1000 * 1000) 112 #define SFC_MIN_RATE (10 * 1000 * 1000) 113 114 #define SFC_VER_3 0x3 115 #define SFC_VER_4 0x4 116 117 enum rockchip_sfc_if_type { 118 IF_TYPE_STD, 119 IF_TYPE_DUAL, 120 IF_TYPE_QUAD, 121 }; 122 123 struct rockchip_sfc_platdata { 124 s32 frequency; 125 void *base; 126 }; 127 128 struct rockchip_sfc { 129 struct rockchip_sfc_reg *regbase; 130 struct clk clk; 131 unsigned int max_freq; 132 unsigned int mode; 133 unsigned int speed_hz; 134 u32 max_iosize; 135 bool prepare; 136 u32 last_prepare_size; 137 u32 cmd; 138 u32 addr; 139 u8 addr_bits; 140 u8 addr_xbits_ext; 141 u8 dummy_bits; 142 u8 rw; 143 u32 trb; 144 }; 145 146 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 147 { 148 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 149 150 plat->base = dev_read_addr_ptr(bus); 151 #if CONFIG_IS_ENABLED(CLK) 152 struct rockchip_sfc *sfc = dev_get_priv(bus); 153 int ret; 154 155 ret = clk_get_by_index(bus, 0, &sfc->clk); 156 if (ret < 0) { 157 printf("Could not get clock for %s: %d\n", bus->name, ret); 158 return ret; 159 } 160 #endif 161 162 return 0; 163 } 164 165 u32 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 166 { 167 struct rockchip_sfc_reg *regs = sfc->regbase; 168 169 return (u32)(readl(®s->ver) & 0xFFFF); 170 } 171 172 static int rockchip_sfc_probe(struct udevice *bus) 173 { 174 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 175 struct rockchip_sfc *sfc = dev_get_priv(bus); 176 struct rockchip_sfc_reg *regs; 177 struct dm_spi_bus *dm_spi_bus; 178 179 dm_spi_bus = bus->uclass_priv; 180 dm_spi_bus->max_hz = plat->frequency; 181 sfc->regbase = (struct rockchip_sfc_reg *)plat->base; 182 sfc->max_freq = SFC_MAX_RATE; 183 sfc->speed_hz = SFC_DEFAULT_RATE; 184 #if CONFIG_IS_ENABLED(CLK) 185 clk_set_rate(&sfc->clk, sfc->speed_hz); 186 #endif 187 regs = sfc->regbase; 188 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) { 189 sfc->max_iosize = SFC_MAX_TRB_VER4; 190 writel(1, ®s->len_ctrl); 191 } else { 192 sfc->max_iosize = SFC_MAX_TRB_VER3; 193 } 194 195 return 0; 196 } 197 198 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 199 { 200 struct rockchip_sfc_reg *regs = sfc->regbase; 201 int tbase = get_timer(0); 202 u32 rcvr; 203 int ret = 0; 204 205 writel(SFC_RESET, ®s->rcvr); 206 do { 207 rcvr = readl(®s->rcvr); 208 if (get_timer(tbase) > 1000) { 209 debug("sfc reset timeout\n"); 210 ret = -ETIMEDOUT; 211 break; 212 } 213 udelay(1); 214 } while (rcvr); 215 216 writel(0xFFFFFFFF, ®s->iclr); 217 218 debug("sfc reset\n"); 219 220 return ret; 221 } 222 223 static int rockchip_sfc_dma_xfer_wait_finished(struct rockchip_sfc *sfc) 224 { 225 struct rockchip_sfc_reg *regs = sfc->regbase; 226 int timeout = sfc->last_prepare_size * 10; 227 unsigned long tbase; 228 int ret = 0; 229 int risr; 230 231 tbase = get_timer(0); 232 do { 233 udelay(1); 234 risr = readl(®s->risr); 235 if (get_timer(tbase) > timeout) { 236 debug("dma timeout\n"); 237 ret = -ETIMEDOUT; 238 break; 239 } 240 } while (!(risr & TRANS_FINISH_INT)); 241 sfc->last_prepare_size = 0; 242 243 return ret; 244 } 245 246 /* The SFC_CTRL register is a global control register, 247 * when the controller is in busy state(SFC_SR), 248 * SFC_CTRL cannot be set. 249 */ 250 static int rockchip_sfc_wait_idle(struct rockchip_sfc *sfc, 251 u32 timeout_ms) 252 { 253 struct rockchip_sfc_reg *regs = sfc->regbase; 254 unsigned long tbase = get_timer(0); 255 u32 sr, fsr; 256 257 if (sfc->last_prepare_size && rockchip_sfc_dma_xfer_wait_finished(sfc)) 258 return -ETIMEDOUT; 259 260 while (1) { 261 sr = readl(®s->sr); 262 fsr = readl(®s->fsr); 263 if ((fsr & SFC_TX_EMPTY) && 264 (fsr & SFC_RX_EMPTY) && 265 !(sr & SFC_BUSY)) 266 break; 267 if (get_timer(tbase) > timeout_ms) { 268 printf("waite sfc idle timeout(sr:0x%08x fsr:0x%08x)\n", 269 sr, fsr); 270 rockchip_sfc_reset(sfc); 271 return -ETIMEDOUT; 272 } 273 udelay(100); 274 } 275 276 return 0; 277 } 278 279 static u8 rockchip_sfc_get_if_type(struct rockchip_sfc *sfc) 280 { 281 int type = IF_TYPE_STD; 282 283 if (sfc->rw == SFC_WR) { 284 if (sfc->mode & SPI_TX_QUAD) 285 type = IF_TYPE_QUAD; 286 else if (sfc->mode & SPI_TX_DUAL) 287 type = IF_TYPE_DUAL; 288 else 289 type = IF_TYPE_STD; 290 } else { 291 if (sfc->mode & SPI_RX_QUAD) 292 type = IF_TYPE_QUAD; 293 else if (sfc->mode & SPI_RX_DUAL) 294 type = IF_TYPE_DUAL; 295 else 296 type = IF_TYPE_STD; 297 } 298 299 return type; 300 } 301 302 static void rockchip_sfc_setup_xfer(struct rockchip_sfc *sfc, u32 trb) 303 { 304 struct rockchip_sfc_reg *regs = sfc->regbase; 305 u32 val; 306 u8 data_width = IF_TYPE_STD; 307 308 rockchip_sfc_wait_idle(sfc, 10); 309 310 if (sfc->addr_bits == SFC_ADDR_24BITS || 311 sfc->addr_bits == SFC_ADDR_32BITS) 312 data_width = rockchip_sfc_get_if_type(sfc); 313 314 SFC_DBG("--- sfc.addr_bit %x\n", sfc->addr_bits); 315 if (sfc->addr_bits == SFC_ADDR_XBITS) 316 writel(sfc->addr_xbits_ext - 1, ®s->abit); 317 318 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) { 319 SFC_DBG("--- sfc.len_ext %x\n", trb); 320 writel(trb, ®s->len_ext); 321 } 322 323 val = 0x02; 324 val |= (data_width << SFC_DATA_WIDTH_SHIFT); 325 326 SFC_DBG("--- sfc.ctrl %x\n", val); 327 writel(val, ®s->ctrl); 328 329 val = sfc->cmd; 330 val |= (trb & 0x3fff) << SFC_TRB_SHIFT; 331 val |= sfc->rw << SFC_RW_SHIFT; 332 val |= sfc->addr_bits << SFC_ADDR_BITS_SHIFT; 333 val |= sfc->dummy_bits << SFC_DUMMY_BITS_SHIFT; 334 335 SFC_DBG("--- sfc.cmd %x\n", val); 336 writel(val, ®s->cmd); 337 338 if (sfc->addr_bits & SFC_ADDR_XBITS) { 339 SFC_DBG("--- sfc.addr %x\n", sfc->addr); 340 writel(sfc->addr, ®s->addr); 341 } 342 } 343 344 static int rockchip_sfc_dma_xfer(struct rockchip_sfc *sfc, void *buffer, 345 size_t trb) 346 { 347 struct rockchip_sfc_reg *regs = sfc->regbase; 348 struct bounce_buffer bb; 349 unsigned int bb_flags; 350 int timeout = trb * 1000; 351 int ret = 0; 352 int risr; 353 unsigned long tbase; 354 355 if (sfc->rw == SFC_WR) 356 bb_flags = GEN_BB_READ; 357 else 358 bb_flags = GEN_BB_WRITE; 359 360 ret = bounce_buffer_start(&bb, buffer, trb, bb_flags); 361 if (ret) 362 return ret; 363 364 rockchip_sfc_setup_xfer(sfc, bb.len_aligned); 365 366 writel(0xFFFFFFFF, ®s->iclr); 367 writel((unsigned long)bb.bounce_buffer, ®s->dmaaddr); 368 writel(SFC_DMA_START, ®s->dmatr); 369 370 tbase = get_timer(0); 371 do { 372 udelay(1); 373 risr = readl(®s->risr); 374 if (get_timer(tbase) > timeout) { 375 debug("dma timeout\n"); 376 ret = -ETIMEDOUT; 377 break; 378 } 379 } while (!(risr & TRANS_FINISH_INT)); 380 381 writel(0xFFFFFFFF, ®s->iclr); 382 383 bounce_buffer_stop(&bb); 384 385 return ret; 386 } 387 388 static int rockchip_sfc_dma_xfer_prepare(struct rockchip_sfc *sfc, 389 void *buffer, size_t trb) 390 { 391 struct rockchip_sfc_reg *regs = sfc->regbase; 392 393 SFC_DBG("sfc_dma_xfer_prepar enter\n"); 394 395 rockchip_sfc_setup_xfer(sfc, trb); 396 sfc->last_prepare_size = trb; 397 398 flush_dcache_range((unsigned long)buffer, 399 (unsigned long)buffer + trb); 400 401 writel(0xFFFFFFFF, ®s->iclr); 402 writel((unsigned long)buffer, ®s->dmaaddr); 403 writel(SFC_DMA_START, ®s->dmatr); 404 405 return 0; 406 } 407 408 static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int rw, 409 u32 timeout) 410 { 411 struct rockchip_sfc_reg *regs = sfc->regbase; 412 unsigned long tbase = get_timer(0); 413 u8 level; 414 u32 fsr; 415 416 do { 417 fsr = readl(®s->fsr); 418 if (rw == SFC_WR) 419 level = (fsr & SFC_TXLV_MASK) >> SFC_TXLV_SHIFT; 420 else 421 level = (fsr & SFC_RXLV_MASK) >> SFC_RXLV_SHIFT; 422 if (get_timer(tbase) > timeout) 423 return -ETIMEDOUT; 424 udelay(1); 425 } while (!level); 426 427 return level; 428 } 429 430 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 431 { 432 struct rockchip_sfc_reg *regs = sfc->regbase; 433 u32 bytes = len & 0x3; 434 u32 words = len >> 2; 435 int tx_level = 0; 436 u32 val = 0; 437 u8 count; 438 439 while (words) { 440 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 441 if (tx_level <= 0) 442 return tx_level; 443 count = min(words, (u32)tx_level); 444 writesl(®s->data, buf, count); 445 buf += count; 446 words -= count; 447 } 448 449 /* handle the last non 4byte aligned bytes */ 450 if (bytes) { 451 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 452 if (tx_level <= 0) 453 return tx_level; 454 memcpy(&val, buf, bytes); 455 writel(val, ®s->data); 456 } 457 458 return 0; 459 } 460 461 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 462 { 463 struct rockchip_sfc_reg *regs = sfc->regbase; 464 u32 bytes = len & 0x3; 465 u32 words = len >> 2; 466 int rx_level = 0; 467 u32 count; 468 u32 val; 469 470 while (words) { 471 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 472 if (rx_level <= 0) 473 return rx_level; 474 count = min(words, (u32)rx_level); 475 readsl(®s->data, buf, count); 476 buf += count; 477 words -= count; 478 } 479 480 /* handle the last non 4 bytes aligned bytes */ 481 if (bytes) { 482 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 483 if (rx_level <= 0) 484 return rx_level; 485 val = readl(®s->data); 486 memcpy(buf, &val, bytes); 487 } 488 489 return 0; 490 } 491 492 static int rockchip_sfc_pio_xfer(struct rockchip_sfc *sfc, void *buf, u32 len) 493 { 494 int ret = 0; 495 496 rockchip_sfc_setup_xfer(sfc, len); 497 498 if (len) { 499 if (sfc->rw == SFC_WR) 500 ret = rockchip_sfc_write_fifo(sfc, (u32 *)buf, len); 501 else 502 ret = rockchip_sfc_read_fifo(sfc, (u32 *)buf, len); 503 } 504 505 return ret; 506 } 507 508 static int rockchip_sfc_read(struct rockchip_sfc *sfc, u32 offset, 509 void *buf, size_t len) 510 { 511 u32 dma_trans; 512 u32 trb; 513 u8 bytes; 514 int ret; 515 516 if (len >= ARCH_DMA_MINALIGN) { 517 bytes = len & (ARCH_DMA_MINALIGN - 1); 518 dma_trans = len - bytes; 519 } else { 520 dma_trans = 0; 521 bytes = len; 522 } 523 524 while (dma_trans) { 525 trb = min_t(size_t, dma_trans, sfc->max_iosize); 526 if (sfc->prepare) 527 ret = rockchip_sfc_dma_xfer_prepare(sfc, buf, len); 528 else 529 ret = rockchip_sfc_dma_xfer(sfc, buf, trb); 530 if (ret < 0) 531 return ret; 532 dma_trans -= trb; 533 sfc->addr += trb; 534 buf += trb; 535 } 536 537 /* 538 * transfer the last non dma anligned byte by pio mode 539 */ 540 if (bytes) 541 ret = rockchip_sfc_pio_xfer(sfc, buf, bytes); 542 543 return 0; 544 } 545 546 static int rockchip_sfc_write(struct rockchip_sfc *sfc, u32 offset, 547 void *buf, size_t len) 548 { 549 if (len > sfc->max_iosize) { 550 printf("out of the max sfc trb"); 551 return -EINVAL; 552 } 553 554 if (len && !(len & (ARCH_DMA_MINALIGN - 1))) 555 return rockchip_sfc_dma_xfer(sfc, buf, len); 556 else 557 return rockchip_sfc_pio_xfer(sfc, buf, len); 558 559 return 0; 560 } 561 562 static int rockchip_sfc_do_xfer(struct rockchip_sfc *sfc, void *buf, size_t len) 563 { 564 if (sfc->rw) 565 return rockchip_sfc_write(sfc, sfc->addr, buf, len); 566 else 567 return rockchip_sfc_read(sfc, sfc->addr, buf, len); 568 } 569 570 static int rockchip_sfc_xfer(struct udevice *dev, unsigned int bitlen, 571 const void *dout, void *din, unsigned long flags) 572 { 573 struct udevice *bus = dev->parent; 574 struct rockchip_sfc *sfc = dev_get_priv(bus); 575 int len = bitlen >> 3; 576 u8 *pcmd = (u8 *)dout; 577 void *data_buf; 578 int ret = 0; 579 580 if (flags & SPI_XFER_BEGIN) { 581 sfc->cmd = pcmd[0]; 582 switch (len) { 583 case 6: /* Nor >16MB 0x6b dummy op */ 584 sfc->addr_bits = SFC_ADDR_32BITS; 585 sfc->dummy_bits = 8; 586 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 587 break; 588 case 5: /* Nor <=16MB 0x6b dummy op, Nor >16MB no dummy op */ 589 if (sfc->cmd == 0x6b) { 590 sfc->addr_bits = SFC_ADDR_24BITS; 591 sfc->dummy_bits = 8; 592 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 593 } else { 594 sfc->addr_bits = SFC_ADDR_32BITS; 595 sfc->dummy_bits = 0; 596 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 597 } 598 break; 599 case 4: /* Nand erase and read, Nor <=16MB no dummy op */ 600 sfc->addr_bits = SFC_ADDR_24BITS; 601 sfc->dummy_bits = 0; 602 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 603 break; 604 case 3: /* Nand prog, */ 605 sfc->addr_bits = SFC_ADDR_XBITS; 606 sfc->addr_xbits_ext = 16; 607 sfc->dummy_bits = 0; 608 sfc->addr = pcmd[2] | pcmd[1] << 8; 609 break; 610 case 2: /* Nand read/write feature */ 611 sfc->addr_bits = SFC_ADDR_XBITS; 612 sfc->addr_xbits_ext = 8; 613 sfc->dummy_bits = 0; 614 sfc->addr = pcmd[1]; 615 break; 616 default: /* Nand/Nor Read/Write status */ 617 sfc->addr_bits = SFC_ADDR_0BITS; 618 sfc->dummy_bits = 0; 619 sfc->addr = 0; 620 break; 621 } 622 SFC_DBG("%s %d %x %d %d %x\n", __func__, len, sfc->cmd, 623 sfc->addr_bits, sfc->dummy_bits, sfc->addr); 624 } 625 if (flags & SPI_XFER_END) { 626 if (din) { 627 sfc->rw = SFC_RD; 628 data_buf = din; 629 } else { 630 sfc->rw = SFC_WR; 631 data_buf = (void *)dout; 632 } 633 634 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 635 len = 0; 636 data_buf = NULL; 637 } 638 639 sfc->prepare = flags & SPI_XFER_PREPARE ? true : false; 640 641 if (sfc->cmd == 0x9f && len == 4) { 642 /* SPI Nand read id */ 643 sfc->addr_bits = SFC_ADDR_XBITS; 644 sfc->addr_xbits_ext = 8; 645 sfc->dummy_bits = 0; 646 sfc->addr = 0; 647 ((u8 *)data_buf)[0] = 0xff; 648 ret = rockchip_sfc_do_xfer(sfc, &((u8 *)data_buf)[1], 3); 649 } else { 650 ret = rockchip_sfc_do_xfer(sfc, data_buf, len); 651 } 652 } 653 654 return ret; 655 } 656 657 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 658 { 659 struct rockchip_sfc *sfc = dev_get_priv(bus); 660 661 if (speed > sfc->max_freq) 662 speed = sfc->max_freq; 663 664 sfc->speed_hz = speed; 665 #if CONFIG_IS_ENABLED(CLK) 666 clk_set_rate(&sfc->clk, sfc->speed_hz); 667 SFC_DBG("%s clk= %ld\n", __func__, clk_get_rate(&sfc->clk)); 668 #endif 669 return 0; 670 } 671 672 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 673 { 674 struct rockchip_sfc *sfc = dev_get_priv(bus); 675 676 sfc->mode = mode; 677 678 return 0; 679 } 680 681 static const struct dm_spi_ops rockchip_sfc_ops = { 682 .xfer = rockchip_sfc_xfer, 683 .set_speed = rockchip_sfc_set_speed, 684 .set_mode = rockchip_sfc_set_mode, 685 }; 686 687 static const struct udevice_id rockchip_sfc_ids[] = { 688 { .compatible = "rockchip,sfc" }, 689 { } 690 }; 691 692 U_BOOT_DRIVER(rockchip_sfc_driver) = { 693 .name = "rockchip_sfc", 694 .id = UCLASS_SPI, 695 .of_match = rockchip_sfc_ids, 696 .ops = &rockchip_sfc_ops, 697 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 698 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc_platdata), 699 .priv_auto_alloc_size = sizeof(struct rockchip_sfc), 700 .probe = rockchip_sfc_probe, 701 }; 702