1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Serial Flash Controller Driver 4 * 5 * Copyright (c) 2017-2021, Rockchip Inc. 6 * Author: Shawn Lin <shawn.lin@rock-chips.com> 7 * Chris Morgan <macromorgan@hotmail.com> 8 * Jon Lin <Jon.lin@rock-chips.com> 9 */ 10 11 #include <asm/io.h> 12 #include <bouncebuf.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <linux/bitops.h> 16 #include <linux/delay.h> 17 #include <linux/iopoll.h> 18 #include <spi.h> 19 #include <spi-mem.h> 20 21 /* System control */ 22 #define SFC_CTRL 0x0 23 #define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) 24 #define SFC_CTRL_CMD_BITS_SHIFT 8 25 #define SFC_CTRL_ADDR_BITS_SHIFT 10 26 #define SFC_CTRL_DATA_BITS_SHIFT 12 27 28 /* Interrupt mask */ 29 #define SFC_IMR 0x4 30 #define SFC_IMR_RX_FULL BIT(0) 31 #define SFC_IMR_RX_UFLOW BIT(1) 32 #define SFC_IMR_TX_OFLOW BIT(2) 33 #define SFC_IMR_TX_EMPTY BIT(3) 34 #define SFC_IMR_TRAN_FINISH BIT(4) 35 #define SFC_IMR_BUS_ERR BIT(5) 36 #define SFC_IMR_NSPI_ERR BIT(6) 37 #define SFC_IMR_DMA BIT(7) 38 39 /* Interrupt clear */ 40 #define SFC_ICLR 0x8 41 #define SFC_ICLR_RX_FULL BIT(0) 42 #define SFC_ICLR_RX_UFLOW BIT(1) 43 #define SFC_ICLR_TX_OFLOW BIT(2) 44 #define SFC_ICLR_TX_EMPTY BIT(3) 45 #define SFC_ICLR_TRAN_FINISH BIT(4) 46 #define SFC_ICLR_BUS_ERR BIT(5) 47 #define SFC_ICLR_NSPI_ERR BIT(6) 48 #define SFC_ICLR_DMA BIT(7) 49 50 /* FIFO threshold level */ 51 #define SFC_FTLR 0xc 52 #define SFC_FTLR_TX_SHIFT 0 53 #define SFC_FTLR_TX_MASK 0x1f 54 #define SFC_FTLR_RX_SHIFT 8 55 #define SFC_FTLR_RX_MASK 0x1f 56 57 /* Reset FSM and FIFO */ 58 #define SFC_RCVR 0x10 59 #define SFC_RCVR_RESET BIT(0) 60 61 /* Enhanced mode */ 62 #define SFC_AX 0x14 63 64 /* Address Bit number */ 65 #define SFC_ABIT 0x18 66 67 /* Interrupt status */ 68 #define SFC_ISR 0x1c 69 #define SFC_ISR_RX_FULL_SHIFT BIT(0) 70 #define SFC_ISR_RX_UFLOW_SHIFT BIT(1) 71 #define SFC_ISR_TX_OFLOW_SHIFT BIT(2) 72 #define SFC_ISR_TX_EMPTY_SHIFT BIT(3) 73 #define SFC_ISR_TX_FINISH_SHIFT BIT(4) 74 #define SFC_ISR_BUS_ERR_SHIFT BIT(5) 75 #define SFC_ISR_NSPI_ERR_SHIFT BIT(6) 76 #define SFC_ISR_DMA_SHIFT BIT(7) 77 78 /* FIFO status */ 79 #define SFC_FSR 0x20 80 #define SFC_FSR_TX_IS_FULL BIT(0) 81 #define SFC_FSR_TX_IS_EMPTY BIT(1) 82 #define SFC_FSR_RX_IS_EMPTY BIT(2) 83 #define SFC_FSR_RX_IS_FULL BIT(3) 84 #define SFC_FSR_TXLV_MASK GENMASK(12, 8) 85 #define SFC_FSR_TXLV_SHIFT 8 86 #define SFC_FSR_RXLV_MASK GENMASK(20, 16) 87 #define SFC_FSR_RXLV_SHIFT 16 88 89 /* FSM status */ 90 #define SFC_SR 0x24 91 #define SFC_SR_IS_IDLE 0x0 92 #define SFC_SR_IS_BUSY 0x1 93 94 /* Raw interrupt status */ 95 #define SFC_RISR 0x28 96 #define SFC_RISR_RX_FULL BIT(0) 97 #define SFC_RISR_RX_UNDERFLOW BIT(1) 98 #define SFC_RISR_TX_OVERFLOW BIT(2) 99 #define SFC_RISR_TX_EMPTY BIT(3) 100 #define SFC_RISR_TRAN_FINISH BIT(4) 101 #define SFC_RISR_BUS_ERR BIT(5) 102 #define SFC_RISR_NSPI_ERR BIT(6) 103 #define SFC_RISR_DMA BIT(7) 104 105 /* Version */ 106 #define SFC_VER 0x2C 107 #define SFC_VER_3 0x3 108 #define SFC_VER_4 0x4 109 #define SFC_VER_5 0x5 110 #define SFC_VER_6 0x6 111 #define SFC_VER_8 0x8 112 113 /* Delay line controller resiter */ 114 #define SFC_DLL_CTRL0 0x3C 115 #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) 116 #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU 117 #define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU 118 119 /* Master trigger */ 120 #define SFC_DMA_TRIGGER 0x80 121 #define SFC_DMA_TRIGGER_START 1 122 123 /* Src or Dst addr for master */ 124 #define SFC_DMA_ADDR 0x84 125 126 /* Length control register extension 32GB */ 127 #define SFC_LEN_CTRL 0x88 128 #define SFC_LEN_CTRL_TRB_SEL 1 129 #define SFC_LEN_EXT 0x8C 130 131 /* Command */ 132 #define SFC_CMD 0x100 133 #define SFC_CMD_IDX_SHIFT 0 134 #define SFC_CMD_DUMMY_SHIFT 8 135 #define SFC_CMD_DIR_SHIFT 12 136 #define SFC_CMD_DIR_RD 0 137 #define SFC_CMD_DIR_WR 1 138 #define SFC_CMD_ADDR_SHIFT 14 139 #define SFC_CMD_ADDR_0BITS 0 140 #define SFC_CMD_ADDR_24BITS 1 141 #define SFC_CMD_ADDR_32BITS 2 142 #define SFC_CMD_ADDR_XBITS 3 143 #define SFC_CMD_TRAN_BYTES_SHIFT 16 144 #define SFC_CMD_CS_SHIFT 30 145 146 /* Address */ 147 #define SFC_ADDR 0x104 148 149 /* Data */ 150 #define SFC_DATA 0x108 151 152 /* The controller and documentation reports that it supports up to 4 CS 153 * devices (0-3), however I have only been able to test a single CS (CS 0) 154 * due to the configuration of my device. 155 */ 156 #define SFC_MAX_CHIPSELECT_NUM 4 157 158 /* The SFC can transfer max 16KB - 1 at one time 159 * we set it to 15.5KB here for alignment. 160 */ 161 #define SFC_MAX_IOSIZE_VER3 (512 * 31) 162 163 #define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU) 164 165 /* DMA is only enabled for large data transmission */ 166 #define SFC_DMA_TRANS_THRETHOLD (0x40) 167 168 /* Maximum clock values from datasheet suggest keeping clock value under 169 * 150MHz. No minimum or average value is suggested. 170 */ 171 #define SFC_MAX_SPEED (150 * 1000 * 1000) 172 #define SFC_DLL_THRESHOLD_RATE (50 * 1000 * 1000) 173 174 #define SFC_DLL_TRANING_STEP 10 /* Training step */ 175 #define SFC_DLL_TRANING_VALID_WINDOW 80 /* Training Valid DLL winbow */ 176 177 struct rockchip_sfc { 178 struct udevice *dev; 179 void __iomem *regbase; 180 struct clk hclk; 181 struct clk clk; 182 u32 max_freq; 183 u32 speed; 184 bool use_dma; 185 u32 max_iosize; 186 u16 version; 187 188 u32 last_async_size; 189 u32 async; 190 u32 dll_cells; 191 u32 max_dll_cells; 192 }; 193 194 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 195 { 196 int err; 197 u32 status; 198 199 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); 200 201 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, 202 !(status & SFC_RCVR_RESET), 203 1000000); 204 if (err) 205 printf("SFC reset never finished\n"); 206 207 /* Still need to clear the masked interrupt from RISR */ 208 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 209 210 return err; 211 } 212 213 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 214 { 215 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); 216 } 217 218 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) 219 { 220 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 221 return SFC_MAX_IOSIZE_VER4; 222 223 return SFC_MAX_IOSIZE_VER3; 224 } 225 226 static u32 rockchip_sfc_get_max_dll_cells(struct rockchip_sfc *sfc) 227 { 228 switch (rockchip_sfc_get_version(sfc)) { 229 case SFC_VER_8: 230 case SFC_VER_6: 231 case SFC_VER_5: 232 return SFC_DLL_CTRL0_DLL_MAX_VER5; 233 case SFC_VER_4: 234 return SFC_DLL_CTRL0_DLL_MAX_VER4; 235 default: 236 return 0; 237 } 238 } 239 240 static __maybe_unused void rockchip_sfc_set_delay_lines(struct rockchip_sfc *sfc, u16 cells) 241 { 242 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc); 243 u32 val = 0; 244 245 if (cells > cell_max) 246 cells = cell_max; 247 248 if (cells) 249 val = SFC_DLL_CTRL0_SCLK_SMP_DLL | cells; 250 251 writel(val, sfc->regbase + SFC_DLL_CTRL0); 252 } 253 254 static int rockchip_sfc_init(struct rockchip_sfc *sfc) 255 { 256 writel(0, sfc->regbase + SFC_CTRL); 257 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 258 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); 259 260 return 0; 261 } 262 263 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 264 { 265 struct rockchip_sfc *sfc = dev_get_platdata(bus); 266 267 sfc->regbase = dev_read_addr_ptr(bus); 268 if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma")) 269 sfc->use_dma = false; 270 else 271 sfc->use_dma = true; 272 #if CONFIG_IS_ENABLED(CLK) 273 int ret; 274 275 ret = clk_get_by_index(bus, 0, &sfc->clk); 276 if (ret < 0) { 277 printf("Could not get clock for %s: %d\n", bus->name, ret); 278 return ret; 279 } 280 281 ret = clk_get_by_index(bus, 1, &sfc->hclk); 282 if (ret < 0) { 283 printf("Could not get ahb clock for %s: %d\n", bus->name, ret); 284 return ret; 285 } 286 #endif 287 288 return 0; 289 } 290 291 static int rockchip_sfc_probe(struct udevice *bus) 292 { 293 struct rockchip_sfc *sfc = dev_get_platdata(bus); 294 int ret; 295 296 #if CONFIG_IS_ENABLED(CLK) 297 ret = clk_enable(&sfc->hclk); 298 if (ret) 299 dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); 300 301 ret = clk_enable(&sfc->clk); 302 if (ret) 303 dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); 304 #endif 305 306 ret = rockchip_sfc_init(sfc); 307 if (ret) 308 goto err_init; 309 310 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); 311 sfc->version = rockchip_sfc_get_version(sfc); 312 sfc->max_freq = SFC_MAX_SPEED; 313 sfc->dev = bus; 314 315 return 0; 316 317 err_init: 318 #if CONFIG_IS_ENABLED(CLK) 319 clk_disable(&sfc->clk); 320 clk_disable(&sfc->hclk); 321 #endif 322 323 return ret; 324 } 325 326 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 327 { 328 int ret = 0; 329 u32 status; 330 331 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 332 status & SFC_FSR_TXLV_MASK, 333 timeout_us); 334 if (ret) { 335 dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); 336 337 return -ETIMEDOUT; 338 } 339 340 return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; 341 } 342 343 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 344 { 345 int ret = 0; 346 u32 status; 347 348 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 349 status & SFC_FSR_RXLV_MASK, 350 timeout_us); 351 if (ret) { 352 dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); 353 354 return -ETIMEDOUT; 355 } 356 357 return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; 358 } 359 360 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) 361 { 362 if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { 363 /* 364 * SFC not support output DUMMY cycles right after CMD cycles, so 365 * treat it as ADDR cycles. 366 */ 367 op->addr.nbytes = op->dummy.nbytes; 368 op->addr.buswidth = op->dummy.buswidth; 369 op->addr.val = 0xFFFFFFFFF; 370 371 op->dummy.nbytes = 0; 372 } 373 } 374 375 static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout) 376 { 377 unsigned long tbase; 378 379 /* Wait for the DMA interrupt status */ 380 tbase = get_timer(0); 381 while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) { 382 if (get_timer(tbase) > timeout) { 383 printf("dma timeout\n"); 384 rockchip_sfc_reset(sfc); 385 386 return -ETIMEDOUT; 387 } 388 389 udelay(1); 390 } 391 392 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 393 394 return 0; 395 } 396 397 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, 398 struct spi_slave *mem, 399 const struct spi_mem_op *op, 400 u32 len) 401 { 402 struct dm_spi_slave_platdata *plat = dev_get_platdata(sfc->dev); 403 u32 ctrl = 0, cmd = 0; 404 405 /* set CMD */ 406 cmd = op->cmd.opcode; 407 ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); 408 409 /* set ADDR */ 410 if (op->addr.nbytes) { 411 if (op->addr.nbytes == 4) { 412 cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; 413 } else if (op->addr.nbytes == 3) { 414 cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; 415 } else { 416 cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; 417 writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); 418 } 419 420 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); 421 } 422 423 /* set DUMMY */ 424 if (op->dummy.nbytes) { 425 if (op->dummy.buswidth == 4) 426 cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; 427 else if (op->dummy.buswidth == 2) 428 cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; 429 else 430 cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; 431 } 432 433 /* set DATA */ 434 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ 435 writel(len, sfc->regbase + SFC_LEN_EXT); 436 else 437 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; 438 if (len) { 439 if (op->data.dir == SPI_MEM_DATA_OUT) 440 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 441 442 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); 443 } 444 if (!len && op->addr.nbytes) 445 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 446 447 /* set the Controller */ 448 ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; 449 cmd |= plat->cs << SFC_CMD_CS_SHIFT; 450 451 dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", 452 op->addr.nbytes, op->addr.buswidth, 453 op->dummy.nbytes, op->dummy.buswidth); 454 dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", 455 ctrl, cmd, op->addr.val, len); 456 457 writel(ctrl, sfc->regbase + SFC_CTRL); 458 writel(cmd, sfc->regbase + SFC_CMD); 459 if (op->addr.nbytes) 460 writel(op->addr.val, sfc->regbase + SFC_ADDR); 461 462 return 0; 463 } 464 465 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) 466 { 467 u8 bytes = len & 0x3; 468 u32 dwords; 469 int tx_level; 470 u32 write_words; 471 u32 tmp = 0; 472 473 dwords = len >> 2; 474 while (dwords) { 475 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 476 if (tx_level < 0) 477 return tx_level; 478 write_words = min_t(u32, tx_level, dwords); 479 writesl(sfc->regbase + SFC_DATA, buf, write_words); 480 buf += write_words << 2; 481 dwords -= write_words; 482 } 483 484 /* write the rest non word aligned bytes */ 485 if (bytes) { 486 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 487 if (tx_level < 0) 488 return tx_level; 489 memcpy(&tmp, buf, bytes); 490 writel(tmp, sfc->regbase + SFC_DATA); 491 } 492 493 return len; 494 } 495 496 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) 497 { 498 u8 bytes = len & 0x3; 499 u32 dwords; 500 u8 read_words; 501 int rx_level; 502 int tmp; 503 504 /* word aligned access only */ 505 dwords = len >> 2; 506 while (dwords) { 507 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 508 if (rx_level < 0) 509 return rx_level; 510 read_words = min_t(u32, rx_level, dwords); 511 readsl(sfc->regbase + SFC_DATA, buf, read_words); 512 buf += read_words << 2; 513 dwords -= read_words; 514 } 515 516 /* read the rest non word aligned bytes */ 517 if (bytes) { 518 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 519 if (rx_level < 0) 520 return rx_level; 521 tmp = readl(sfc->regbase + SFC_DATA); 522 memcpy(buf, &tmp, bytes); 523 } 524 525 return len; 526 } 527 528 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) 529 { 530 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 531 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); 532 writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); 533 534 return len; 535 } 536 537 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, 538 const struct spi_mem_op *op, u32 len) 539 { 540 dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); 541 542 if (op->data.dir == SPI_MEM_DATA_OUT) 543 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); 544 else 545 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); 546 } 547 548 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, 549 const struct spi_mem_op *op, u32 len) 550 { 551 struct bounce_buffer bb; 552 unsigned int bb_flags; 553 void *dma_buf; 554 int ret; 555 556 dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); 557 558 if (op->data.dir == SPI_MEM_DATA_OUT) { 559 dma_buf = (void *)op->data.buf.out; 560 bb_flags = GEN_BB_READ; 561 } else { 562 dma_buf = (void *)op->data.buf.in; 563 bb_flags = GEN_BB_WRITE; 564 } 565 566 ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags); 567 if (ret) 568 return ret; 569 570 ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len); 571 rockchip_sfc_wait_for_dma_finished(sfc, len * 10); 572 bounce_buffer_stop(&bb); 573 574 return ret; 575 } 576 577 static int rockchip_sfc_xfer_data_dma_async(struct rockchip_sfc *sfc, 578 const struct spi_mem_op *op, u32 len) 579 { 580 void *dma_buf; 581 582 if (op->data.dir == SPI_MEM_DATA_OUT) { 583 dma_buf = (void *)op->data.buf.out; 584 flush_dcache_range((unsigned long)dma_buf, 585 (unsigned long)dma_buf + len); 586 } else { 587 dma_buf = (void *)op->data.buf.in; 588 } 589 590 dev_dbg(sfc->dev, "xfer_dma_async len=%x %p\n", len, dma_buf); 591 592 rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)dma_buf, len); 593 sfc->last_async_size = len; 594 595 return 0; 596 } 597 598 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) 599 { 600 int ret = 0; 601 u32 status; 602 603 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, 604 !(status & SFC_SR_IS_BUSY), 605 timeout_us); 606 if (ret) { 607 dev_err(sfc->dev, "wait sfc idle timeout\n"); 608 rockchip_sfc_reset(sfc); 609 610 ret = -EIO; 611 } 612 613 return ret; 614 } 615 616 static int rockchip_sfc_exec_op(struct spi_slave *mem, 617 const struct spi_mem_op *op) 618 { 619 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 620 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 621 int ret; 622 623 /* Wait for last async transfer finished */ 624 if (sfc->last_async_size) { 625 rockchip_sfc_wait_for_dma_finished(sfc, sfc->last_async_size); 626 sfc->last_async_size = 0; 627 } 628 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 629 rockchip_sfc_xfer_setup(sfc, mem, op, len); 630 if (len) { 631 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) { 632 if (mem->mode & SPI_DMA_PREPARE) 633 return rockchip_sfc_xfer_data_dma_async(sfc, op, len); 634 ret = rockchip_sfc_xfer_data_dma(sfc, op, len); 635 } else { 636 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 637 } 638 639 if (ret != len) { 640 dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); 641 642 return -EIO; 643 } 644 } 645 646 return rockchip_sfc_xfer_done(sfc, 100000); 647 } 648 649 static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op) 650 { 651 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 652 653 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); 654 655 return 0; 656 } 657 658 #if CONFIG_IS_ENABLED(CLK) 659 static int rockchip_sfc_exec_op_bypass(struct rockchip_sfc *sfc, 660 struct spi_slave *mem, 661 const struct spi_mem_op *op) 662 { 663 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 664 u32 ret; 665 666 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 667 rockchip_sfc_xfer_setup(sfc, mem, op, len); 668 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 669 if (ret != len) { 670 dev_err(sfc->dev, "xfer data failed ret %d\n", ret); 671 672 return -EIO; 673 } 674 675 return rockchip_sfc_xfer_done(sfc, 100000); 676 } 677 678 static void rockchip_sfc_delay_lines_tuning(struct rockchip_sfc *sfc, struct spi_slave *mem) 679 { 680 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1), 681 SPI_MEM_OP_NO_ADDR, 682 SPI_MEM_OP_NO_DUMMY, 683 SPI_MEM_OP_DATA_IN(3, NULL, 1)); 684 u8 id[3], id_temp[3]; 685 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc); 686 u16 right, left = 0; 687 u16 step = SFC_DLL_TRANING_STEP; 688 bool dll_valid = false; 689 690 clk_set_rate(&sfc->clk, SFC_DLL_THRESHOLD_RATE); 691 op.data.buf.in = &id; 692 rockchip_sfc_exec_op_bypass(sfc, mem, &op); 693 if ((0xFF == id[0] && 0xFF == id[1]) || 694 (0x00 == id[0] && 0x00 == id[1])) { 695 dev_dbg(sfc->dev, "no dev, dll by pass\n"); 696 clk_set_rate(&sfc->clk, sfc->speed); 697 698 return; 699 } 700 701 clk_set_rate(&sfc->clk, sfc->speed); 702 op.data.buf.in = &id_temp; 703 for (right = 0; right <= cell_max; right += step) { 704 int ret; 705 706 rockchip_sfc_set_delay_lines(sfc, right); 707 rockchip_sfc_exec_op_bypass(sfc, mem, &op); 708 dev_dbg(sfc->dev, "dll read flash id:%x %x %x\n", 709 id_temp[0], id_temp[1], id_temp[2]); 710 711 ret = memcmp(&id, &id_temp, 3); 712 if (dll_valid && ret) { 713 right -= step; 714 715 break; 716 } 717 if (!dll_valid && !ret) 718 left = right; 719 720 if (!ret) 721 dll_valid = true; 722 723 /* Add cell_max to loop */ 724 if (right == cell_max) 725 break; 726 if (right + step > cell_max) 727 right = cell_max - step; 728 } 729 730 if (dll_valid && (right - left) >= SFC_DLL_TRANING_VALID_WINDOW) { 731 if (left == 0 && right < cell_max) 732 sfc->dll_cells = left + (right - left) * 2 / 5; 733 else 734 sfc->dll_cells = left + (right - left) / 2; 735 } else { 736 sfc->dll_cells = 0; 737 } 738 739 if (sfc->dll_cells) { 740 dev_dbg(sfc->dev, "%d %d %d dll training success in %dMHz max_cells=%u sfc_ver=%d\n", 741 left, right, sfc->dll_cells, sfc->speed, 742 rockchip_sfc_get_max_dll_cells(sfc), rockchip_sfc_get_version(sfc)); 743 rockchip_sfc_set_delay_lines(sfc, (u16)sfc->dll_cells); 744 } else { 745 dev_err(sfc->dev, "%d %d dll training failed in %dMHz, reduce the speed\n", 746 left, right, sfc->speed); 747 rockchip_sfc_set_delay_lines(sfc, 0); 748 clk_set_rate(&sfc->clk, SFC_DLL_THRESHOLD_RATE); 749 sfc->speed = clk_get_rate(&sfc->clk); 750 } 751 } 752 753 #endif 754 755 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 756 { 757 struct rockchip_sfc *sfc = dev_get_platdata(bus); 758 759 if (speed > sfc->max_freq) 760 speed = sfc->max_freq; 761 762 if (speed == sfc->speed) 763 return 0; 764 765 #if CONFIG_IS_ENABLED(CLK) 766 int ret = clk_set_rate(&sfc->clk, speed); 767 768 if (ret < 0) { 769 dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", 770 speed); 771 return ret; 772 } 773 sfc->speed = speed; 774 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) { 775 if (clk_get_rate(&sfc->clk) > SFC_DLL_THRESHOLD_RATE) 776 rockchip_sfc_delay_lines_tuning(sfc, NULL); 777 else 778 rockchip_sfc_set_delay_lines(sfc, 0); 779 } 780 781 dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n", 782 sfc->speed, clk_get_rate(&sfc->clk)); 783 #else 784 dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); 785 #endif 786 return 0; 787 } 788 789 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 790 { 791 return 0; 792 } 793 794 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { 795 .adjust_op_size = rockchip_sfc_adjust_op_size, 796 .exec_op = rockchip_sfc_exec_op, 797 }; 798 799 static const struct dm_spi_ops rockchip_sfc_ops = { 800 .mem_ops = &rockchip_sfc_mem_ops, 801 .set_speed = rockchip_sfc_set_speed, 802 .set_mode = rockchip_sfc_set_mode, 803 }; 804 805 static const struct udevice_id rockchip_sfc_ids[] = { 806 { .compatible = "rockchip,sfc"}, 807 {}, 808 }; 809 810 U_BOOT_DRIVER(rockchip_sfc_driver) = { 811 .name = "rockchip_sfc", 812 .id = UCLASS_SPI, 813 .of_match = rockchip_sfc_ids, 814 .ops = &rockchip_sfc_ops, 815 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 816 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc), 817 .probe = rockchip_sfc_probe, 818 }; 819