1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Serial Flash Controller Driver 4 * 5 * Copyright (c) 2017-2021, Rockchip Inc. 6 * Author: Shawn Lin <shawn.lin@rock-chips.com> 7 * Chris Morgan <macromorgan@hotmail.com> 8 * Jon Lin <Jon.lin@rock-chips.com> 9 */ 10 11 #include <asm/io.h> 12 #include <bouncebuf.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <linux/bitops.h> 16 #include <linux/delay.h> 17 #include <linux/iopoll.h> 18 #include <spi.h> 19 #include <spi-mem.h> 20 #include <asm/gpio.h> 21 22 /* System control */ 23 #define SFC_CTRL 0x0 24 #define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) 25 #define SFC_CTRL_CMD_BITS_SHIFT 8 26 #define SFC_CTRL_ADDR_BITS_SHIFT 10 27 #define SFC_CTRL_DATA_BITS_SHIFT 12 28 29 /* Interrupt mask */ 30 #define SFC_IMR 0x4 31 #define SFC_IMR_RX_FULL BIT(0) 32 #define SFC_IMR_RX_UFLOW BIT(1) 33 #define SFC_IMR_TX_OFLOW BIT(2) 34 #define SFC_IMR_TX_EMPTY BIT(3) 35 #define SFC_IMR_TRAN_FINISH BIT(4) 36 #define SFC_IMR_BUS_ERR BIT(5) 37 #define SFC_IMR_NSPI_ERR BIT(6) 38 #define SFC_IMR_DMA BIT(7) 39 40 /* Interrupt clear */ 41 #define SFC_ICLR 0x8 42 #define SFC_ICLR_RX_FULL BIT(0) 43 #define SFC_ICLR_RX_UFLOW BIT(1) 44 #define SFC_ICLR_TX_OFLOW BIT(2) 45 #define SFC_ICLR_TX_EMPTY BIT(3) 46 #define SFC_ICLR_TRAN_FINISH BIT(4) 47 #define SFC_ICLR_BUS_ERR BIT(5) 48 #define SFC_ICLR_NSPI_ERR BIT(6) 49 #define SFC_ICLR_DMA BIT(7) 50 51 /* FIFO threshold level */ 52 #define SFC_FTLR 0xc 53 #define SFC_FTLR_TX_SHIFT 0 54 #define SFC_FTLR_TX_MASK 0x1f 55 #define SFC_FTLR_RX_SHIFT 8 56 #define SFC_FTLR_RX_MASK 0x1f 57 58 /* Reset FSM and FIFO */ 59 #define SFC_RCVR 0x10 60 #define SFC_RCVR_RESET BIT(0) 61 62 /* Enhanced mode */ 63 #define SFC_AX 0x14 64 65 /* Address Bit number */ 66 #define SFC_ABIT 0x18 67 68 /* Interrupt status */ 69 #define SFC_ISR 0x1c 70 #define SFC_ISR_RX_FULL_SHIFT BIT(0) 71 #define SFC_ISR_RX_UFLOW_SHIFT BIT(1) 72 #define SFC_ISR_TX_OFLOW_SHIFT BIT(2) 73 #define SFC_ISR_TX_EMPTY_SHIFT BIT(3) 74 #define SFC_ISR_TX_FINISH_SHIFT BIT(4) 75 #define SFC_ISR_BUS_ERR_SHIFT BIT(5) 76 #define SFC_ISR_NSPI_ERR_SHIFT BIT(6) 77 #define SFC_ISR_DMA_SHIFT BIT(7) 78 79 /* FIFO status */ 80 #define SFC_FSR 0x20 81 #define SFC_FSR_TX_IS_FULL BIT(0) 82 #define SFC_FSR_TX_IS_EMPTY BIT(1) 83 #define SFC_FSR_RX_IS_EMPTY BIT(2) 84 #define SFC_FSR_RX_IS_FULL BIT(3) 85 #define SFC_FSR_TXLV_MASK GENMASK(13, 8) 86 #define SFC_FSR_TXLV_SHIFT 8 87 #define SFC_FSR_RXLV_MASK GENMASK(20, 16) 88 #define SFC_FSR_RXLV_SHIFT 16 89 90 /* FSM status */ 91 #define SFC_SR 0x24 92 #define SFC_SR_IS_IDLE 0x0 93 #define SFC_SR_IS_BUSY 0x1 94 95 /* Raw interrupt status */ 96 #define SFC_RISR 0x28 97 #define SFC_RISR_RX_FULL BIT(0) 98 #define SFC_RISR_RX_UNDERFLOW BIT(1) 99 #define SFC_RISR_TX_OVERFLOW BIT(2) 100 #define SFC_RISR_TX_EMPTY BIT(3) 101 #define SFC_RISR_TRAN_FINISH BIT(4) 102 #define SFC_RISR_BUS_ERR BIT(5) 103 #define SFC_RISR_NSPI_ERR BIT(6) 104 #define SFC_RISR_DMA BIT(7) 105 106 /* Version */ 107 #define SFC_VER 0x2C 108 #define SFC_VER_3 0x3 109 #define SFC_VER_4 0x4 110 #define SFC_VER_5 0x5 111 #define SFC_VER_6 0x6 112 #define SFC_VER_8 0x8 113 #define SFC_VER_9 0x9 114 115 /* Ext ctrl */ 116 #define SFC_EXT_CTRL 0x34 117 #define SFC_SCLK_X2_BYPASS BIT(24) 118 119 /* Delay line controller resiter */ 120 #define SFC_DLL_CTRL0 0x3C 121 #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) 122 #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU 123 #define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU 124 125 /* Master trigger */ 126 #define SFC_DMA_TRIGGER 0x80 127 #define SFC_DMA_TRIGGER_START 1 128 129 /* Src or Dst addr for master */ 130 #define SFC_DMA_ADDR 0x84 131 132 /* Length control register extension 32GB */ 133 #define SFC_LEN_CTRL 0x88 134 #define SFC_LEN_CTRL_TRB_SEL 1 135 #define SFC_LEN_EXT 0x8C 136 137 /* Command */ 138 #define SFC_CMD 0x100 139 #define SFC_CMD_IDX_SHIFT 0 140 #define SFC_CMD_DUMMY_SHIFT 8 141 #define SFC_CMD_DIR_SHIFT 12 142 #define SFC_CMD_DIR_RD 0 143 #define SFC_CMD_DIR_WR 1 144 #define SFC_CMD_ADDR_SHIFT 14 145 #define SFC_CMD_ADDR_0BITS 0 146 #define SFC_CMD_ADDR_24BITS 1 147 #define SFC_CMD_ADDR_32BITS 2 148 #define SFC_CMD_ADDR_XBITS 3 149 #define SFC_CMD_TRAN_BYTES_SHIFT 16 150 #define SFC_CMD_CS_SHIFT 30 151 152 /* Address */ 153 #define SFC_ADDR 0x104 154 155 /* Data */ 156 #define SFC_DATA 0x108 157 158 #define SFC_CS1_REG_OFFSET 0x200 159 160 #define SFC_MAX_CHIPSELECT_NUM 2 161 162 /* The SFC can transfer max 16KB - 1 at one time 163 * we set it to 15.5KB here for alignment. 164 */ 165 #define SFC_MAX_IOSIZE_VER3 (512 * 31) 166 167 #define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU) 168 169 /* DMA is only enabled for large data transmission */ 170 #define SFC_DMA_TRANS_THRETHOLD (0x40) 171 172 /* Maximum clock values from datasheet suggest keeping clock value under 173 * 150MHz. No minimum or average value is suggested. 174 */ 175 #define SFC_MAX_SPEED (150 * 1000 * 1000) 176 #define SFC_DLL_THRESHOLD_RATE (50 * 1000 * 1000) 177 178 #define SFC_DLL_TRANING_STEP 10 /* Training step */ 179 #define SFC_DLL_TRANING_VALID_WINDOW 80 /* Training Valid DLL winbow */ 180 181 struct rockchip_sfc { 182 struct udevice *dev; 183 void __iomem *regbase; 184 struct clk hclk; 185 struct clk clk; 186 u32 max_freq; 187 u32 cur_speed; 188 u32 cur_real_speed; 189 u32 speed[SFC_MAX_CHIPSELECT_NUM]; 190 bool use_dma; 191 bool sclk_x2_bypass; 192 u32 max_iosize; 193 u16 version; 194 195 u32 last_async_size; 196 u32 async; 197 u32 dll_cells[SFC_MAX_CHIPSELECT_NUM]; 198 u32 max_dll_cells; 199 200 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) 201 struct gpio_desc cs_gpios[SFC_MAX_CHIPSELECT_NUM]; 202 #endif 203 }; 204 205 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 206 { 207 int err; 208 u32 status; 209 210 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); 211 212 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, 213 !(status & SFC_RCVR_RESET), 214 1000000); 215 if (err) 216 dev_err(sfc->dev, "SFC reset never finished\n"); 217 218 /* Still need to clear the masked interrupt from RISR */ 219 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 220 221 dev_dbg(sfc->dev, "reset\n"); 222 223 return err; 224 } 225 226 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 227 { 228 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); 229 } 230 231 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) 232 { 233 if (sfc->version >= SFC_VER_4) 234 return SFC_MAX_IOSIZE_VER4; 235 236 return SFC_MAX_IOSIZE_VER3; 237 } 238 239 static u32 rockchip_sfc_get_max_dll_cells(struct rockchip_sfc *sfc) 240 { 241 if (sfc->version > SFC_VER_4) 242 return SFC_DLL_CTRL0_DLL_MAX_VER5; 243 else if (sfc->version == SFC_VER_4) 244 return SFC_DLL_CTRL0_DLL_MAX_VER4; 245 else 246 return 0; 247 } 248 249 static __maybe_unused void rockchip_sfc_set_delay_lines(struct rockchip_sfc *sfc, u16 cells, u8 cs) 250 { 251 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc); 252 u32 val = 0; 253 254 if (cells > cell_max) 255 cells = cell_max; 256 257 if (cells) 258 val = SFC_DLL_CTRL0_SCLK_SMP_DLL | cells; 259 260 writel(val, sfc->regbase + cs * SFC_CS1_REG_OFFSET + SFC_DLL_CTRL0); 261 } 262 263 #if CONFIG_IS_ENABLED(CLK) 264 static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, unsigned long speed) 265 { 266 if (sfc->version < SFC_VER_8|| sfc->sclk_x2_bypass) 267 return clk_set_rate(&sfc->clk, speed); 268 else 269 return clk_set_rate(&sfc->clk, speed * 2); 270 } 271 272 static unsigned long rockchip_sfc_clk_get_rate(struct rockchip_sfc *sfc) 273 { 274 if (sfc->version < SFC_VER_8 || sfc->sclk_x2_bypass) 275 return clk_get_rate(&sfc->clk); 276 else 277 return clk_get_rate(&sfc->clk) / 2; 278 } 279 #endif 280 281 static int rockchip_sfc_init(struct rockchip_sfc *sfc) 282 { 283 u32 reg; 284 285 #if defined(CONFIG_SPL_BUILD) 286 printf("sfc cmd=%02xH(6BH-x4)\n", readl(sfc->regbase + SFC_CMD) & 0xFF); 287 #endif 288 writel(0, sfc->regbase + SFC_CTRL); 289 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 290 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); 291 if (rockchip_sfc_get_version(sfc) > SFC_VER_8 && sfc->sclk_x2_bypass) { 292 reg = readl(sfc->regbase + SFC_EXT_CTRL); 293 reg |= SFC_SCLK_X2_BYPASS; 294 writel(reg, sfc->regbase + SFC_EXT_CTRL); 295 } 296 297 return 0; 298 } 299 300 static int rockchip_cs_setup(struct udevice *bus) 301 { 302 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) 303 struct rockchip_sfc *sfc = dev_get_platdata(bus); 304 int ret; 305 int i; 306 307 ret = gpio_request_list_by_name(bus, "sfc-cs-gpios", sfc->cs_gpios, 308 ARRAY_SIZE(sfc->cs_gpios), 0); 309 if (ret < 0) { 310 pr_err("Can't get %s gpios! Error: %d\n", bus->name, ret); 311 return ret; 312 } 313 314 for (i = 0; i < ARRAY_SIZE(sfc->cs_gpios); i++) { 315 if (!dm_gpio_is_valid(&sfc->cs_gpios[i])) 316 continue; 317 318 ret = dm_gpio_set_dir_flags(&sfc->cs_gpios[i], 319 GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); 320 if (ret) { 321 dev_err(bus, "Setting cs %d error, ret=%d\n", i, ret); 322 return ret; 323 } 324 } 325 #endif 326 return 0; 327 } 328 329 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 330 { 331 struct rockchip_sfc *sfc = dev_get_platdata(bus); 332 333 sfc->regbase = dev_read_addr_ptr(bus); 334 if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma")) 335 sfc->use_dma = false; 336 else 337 sfc->use_dma = true; 338 sfc->sclk_x2_bypass = ofnode_read_bool(dev_ofnode(bus), "rockchip,sclk-x2-bypass"); 339 #if CONFIG_IS_ENABLED(CLK) 340 int ret; 341 342 ret = clk_get_by_index(bus, 0, &sfc->clk); 343 if (ret < 0) { 344 printf("Could not get clock for %s: %d\n", bus->name, ret); 345 return ret; 346 } 347 348 ret = clk_get_by_index(bus, 1, &sfc->hclk); 349 if (ret < 0) { 350 printf("Could not get ahb clock for %s: %d\n", bus->name, ret); 351 return ret; 352 } 353 #endif 354 355 rockchip_cs_setup(bus); 356 357 return 0; 358 } 359 360 static int rockchip_sfc_probe(struct udevice *bus) 361 { 362 struct rockchip_sfc *sfc = dev_get_platdata(bus); 363 int ret; 364 365 #if CONFIG_IS_ENABLED(CLK) 366 ret = clk_enable(&sfc->hclk); 367 if (ret) 368 dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); 369 370 ret = clk_enable(&sfc->clk); 371 if (ret) 372 dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); 373 #endif 374 /* Initial the version at the first */ 375 sfc->version = rockchip_sfc_get_version(sfc); 376 if (sfc->version == SFC_VER_9) 377 sfc->version = SFC_VER_6; 378 379 ret = rockchip_sfc_init(sfc); 380 if (ret) 381 goto err_init; 382 383 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); 384 sfc->max_freq = SFC_MAX_SPEED; 385 sfc->dev = bus; 386 387 return 0; 388 389 err_init: 390 #if CONFIG_IS_ENABLED(CLK) 391 clk_disable(&sfc->clk); 392 clk_disable(&sfc->hclk); 393 #endif 394 395 return ret; 396 } 397 398 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 399 { 400 int ret = 0; 401 u32 status; 402 403 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 404 status & SFC_FSR_TXLV_MASK, 405 timeout_us); 406 if (ret) { 407 dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); 408 409 return -ETIMEDOUT; 410 } 411 412 return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; 413 } 414 415 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 416 { 417 int ret = 0; 418 u32 status; 419 420 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 421 status & SFC_FSR_RXLV_MASK, 422 timeout_us); 423 if (ret) { 424 dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); 425 426 return -ETIMEDOUT; 427 } 428 429 return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; 430 } 431 432 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) 433 { 434 if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { 435 /* 436 * SFC not support output DUMMY cycles right after CMD cycles, so 437 * treat it as ADDR cycles. 438 */ 439 op->addr.nbytes = op->dummy.nbytes; 440 op->addr.buswidth = op->dummy.buswidth; 441 op->addr.val = 0xFFFFFFFFF; 442 443 op->dummy.nbytes = 0; 444 } 445 } 446 447 static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout) 448 { 449 unsigned long tbase; 450 451 /* Wait for the DMA interrupt status */ 452 tbase = get_timer(0); 453 while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) { 454 if (get_timer(tbase) > timeout) { 455 printf("dma timeout\n"); 456 rockchip_sfc_reset(sfc); 457 458 return -ETIMEDOUT; 459 } 460 461 udelay(1); 462 } 463 464 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 465 466 return 0; 467 } 468 469 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, 470 struct spi_slave *mem, 471 const struct spi_mem_op *op, 472 u32 len) 473 { 474 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(mem->dev); 475 u32 ctrl = 0, cmd = 0; 476 477 /* set CMD */ 478 cmd = op->cmd.opcode; 479 ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); 480 481 /* set ADDR */ 482 if (op->addr.nbytes) { 483 if (op->addr.nbytes == 4) { 484 cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; 485 } else if (op->addr.nbytes == 3) { 486 cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; 487 } else { 488 cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; 489 writel(op->addr.nbytes * 8 - 1, sfc->regbase + plat->cs * SFC_CS1_REG_OFFSET + SFC_ABIT); 490 } 491 492 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); 493 } 494 495 /* set DUMMY */ 496 if (op->dummy.nbytes) { 497 if (op->dummy.buswidth == 4) 498 cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; 499 else if (op->dummy.buswidth == 2) 500 cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; 501 else 502 cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; 503 } 504 505 /* set DATA */ 506 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ 507 writel(len, sfc->regbase + SFC_LEN_EXT); 508 else 509 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; 510 if (len) { 511 if (op->data.dir == SPI_MEM_DATA_OUT) 512 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 513 514 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); 515 } 516 if (!len && op->addr.nbytes) 517 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 518 519 /* set the Controller */ 520 ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; 521 cmd |= plat->cs << SFC_CMD_CS_SHIFT; 522 523 dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", 524 op->addr.nbytes, op->addr.buswidth, 525 op->dummy.nbytes, op->dummy.buswidth); 526 dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x cs=%x\n", 527 ctrl, cmd, op->addr.val, len, plat->cs); 528 529 writel(ctrl, sfc->regbase + plat->cs * SFC_CS1_REG_OFFSET + SFC_CTRL); 530 writel(cmd, sfc->regbase + SFC_CMD); 531 if (op->addr.nbytes) 532 writel(op->addr.val, sfc->regbase + SFC_ADDR); 533 534 return 0; 535 } 536 537 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) 538 { 539 u8 bytes = len & 0x3; 540 u32 dwords; 541 int tx_level; 542 u32 write_words; 543 u32 tmp = 0; 544 545 dwords = len >> 2; 546 while (dwords) { 547 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 548 if (tx_level < 0) 549 return tx_level; 550 write_words = min_t(u32, tx_level, dwords); 551 writesl(sfc->regbase + SFC_DATA, buf, write_words); 552 buf += write_words << 2; 553 dwords -= write_words; 554 } 555 556 /* write the rest non word aligned bytes */ 557 if (bytes) { 558 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 559 if (tx_level < 0) 560 return tx_level; 561 memcpy(&tmp, buf, bytes); 562 writel(tmp, sfc->regbase + SFC_DATA); 563 } 564 565 return len; 566 } 567 568 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) 569 { 570 u8 bytes = len & 0x3; 571 u32 dwords; 572 u8 read_words; 573 int rx_level; 574 int tmp; 575 576 /* word aligned access only */ 577 dwords = len >> 2; 578 while (dwords) { 579 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 580 if (rx_level < 0) 581 return rx_level; 582 read_words = min_t(u32, rx_level, dwords); 583 readsl(sfc->regbase + SFC_DATA, buf, read_words); 584 buf += read_words << 2; 585 dwords -= read_words; 586 } 587 588 /* read the rest non word aligned bytes */ 589 if (bytes) { 590 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 591 if (rx_level < 0) 592 return rx_level; 593 tmp = readl(sfc->regbase + SFC_DATA); 594 memcpy(buf, &tmp, bytes); 595 } 596 597 return len; 598 } 599 600 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) 601 { 602 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 603 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); 604 writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); 605 606 return len; 607 } 608 609 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, 610 const struct spi_mem_op *op, u32 len) 611 { 612 dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); 613 614 if (op->data.dir == SPI_MEM_DATA_OUT) 615 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); 616 else 617 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); 618 } 619 620 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, 621 const struct spi_mem_op *op, u32 len) 622 { 623 struct bounce_buffer bb; 624 unsigned int bb_flags; 625 void *dma_buf; 626 int ret; 627 628 dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); 629 630 if (op->data.dir == SPI_MEM_DATA_OUT) { 631 dma_buf = (void *)op->data.buf.out; 632 bb_flags = GEN_BB_READ; 633 } else { 634 dma_buf = (void *)op->data.buf.in; 635 bb_flags = GEN_BB_WRITE; 636 } 637 638 ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags); 639 if (ret) 640 return ret; 641 642 ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len); 643 rockchip_sfc_wait_for_dma_finished(sfc, len * 10); 644 bounce_buffer_stop(&bb); 645 646 return ret; 647 } 648 649 static int rockchip_sfc_xfer_data_dma_async(struct rockchip_sfc *sfc, 650 const struct spi_mem_op *op, u32 len) 651 { 652 void *dma_buf; 653 654 if (op->data.dir == SPI_MEM_DATA_OUT) { 655 dma_buf = (void *)op->data.buf.out; 656 flush_dcache_range((unsigned long)dma_buf, 657 (unsigned long)dma_buf + len); 658 } else { 659 dma_buf = (void *)op->data.buf.in; 660 } 661 662 dev_dbg(sfc->dev, "xfer_dma_async len=%x %p\n", len, dma_buf); 663 664 rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)dma_buf, len); 665 sfc->last_async_size = len; 666 667 return 0; 668 } 669 670 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) 671 { 672 int ret = 0; 673 u32 status; 674 675 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, 676 !(status & SFC_SR_IS_BUSY), 677 timeout_us); 678 if (ret) { 679 dev_err(sfc->dev, "wait sfc idle timeout\n"); 680 rockchip_sfc_reset(sfc); 681 682 ret = -EIO; 683 } 684 685 return ret; 686 } 687 688 static int rockchip_spi_set_cs(struct rockchip_sfc *sfc, struct spi_slave *mem, bool enable) 689 { 690 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) 691 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(mem->dev); 692 u32 cs = plat->cs; 693 694 if (!dm_gpio_is_valid(&sfc->cs_gpios[cs])) 695 return 0; 696 697 debug("%s %d %x\n", __func__, cs, enable); 698 dm_gpio_set_value(&sfc->cs_gpios[cs], enable); 699 #endif 700 return 0; 701 } 702 703 #if CONFIG_IS_ENABLED(CLK) 704 static int rockchip_sfc_exec_op_bypass(struct rockchip_sfc *sfc, 705 struct spi_slave *mem, 706 const struct spi_mem_op *op) 707 { 708 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 709 u32 ret; 710 711 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 712 rockchip_spi_set_cs(sfc, mem, true); 713 rockchip_sfc_xfer_setup(sfc, mem, op, len); 714 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 715 if (ret != len) { 716 dev_err(sfc->dev, "xfer data failed ret %d\n", ret); 717 718 return -EIO; 719 } 720 721 ret = rockchip_sfc_xfer_done(sfc, 100000); 722 rockchip_spi_set_cs(sfc, mem, false); 723 724 return ret; 725 } 726 727 static void rockchip_sfc_delay_lines_tuning(struct rockchip_sfc *sfc, struct spi_slave *mem) 728 { 729 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(mem->dev); 730 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1), 731 SPI_MEM_OP_NO_ADDR, 732 SPI_MEM_OP_NO_DUMMY, 733 SPI_MEM_OP_DATA_IN(3, NULL, 1)); 734 u8 id[3], id_temp[3]; 735 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc); 736 u16 right, left = 0; 737 u16 step = SFC_DLL_TRANING_STEP; 738 bool dll_valid = false; 739 u8 cs = plat->cs; 740 741 rockchip_sfc_clk_set_rate(sfc, SFC_DLL_THRESHOLD_RATE); 742 op.data.buf.in = &id; 743 rockchip_sfc_exec_op_bypass(sfc, mem, &op); 744 if ((0xFF == id[0] && 0xFF == id[1]) || 745 (0x00 == id[0] && 0x00 == id[1])) { 746 dev_dbg(sfc->dev, "no dev, dll by pass\n"); 747 rockchip_sfc_clk_set_rate(sfc, sfc->speed[cs]); 748 sfc->speed[cs] = SFC_DLL_THRESHOLD_RATE; 749 750 return; 751 } 752 753 rockchip_sfc_clk_set_rate(sfc, sfc->speed[cs]); 754 op.data.buf.in = &id_temp; 755 for (right = 0; right <= cell_max; right += step) { 756 int ret; 757 758 rockchip_sfc_set_delay_lines(sfc, right, cs); 759 rockchip_sfc_exec_op_bypass(sfc, mem, &op); 760 dev_dbg(sfc->dev, "dll read flash id:%x %x %x\n", 761 id_temp[0], id_temp[1], id_temp[2]); 762 763 ret = memcmp(&id, &id_temp, 3); 764 if (dll_valid && ret) { 765 right -= step; 766 767 break; 768 } 769 if (!dll_valid && !ret) 770 left = right; 771 772 if (!ret) 773 dll_valid = true; 774 775 /* Add cell_max to loop */ 776 if (right == cell_max) 777 break; 778 if (right + step > cell_max) 779 right = cell_max - step; 780 } 781 782 if (dll_valid && (right - left) >= SFC_DLL_TRANING_VALID_WINDOW) { 783 if (left == 0 && right < cell_max) 784 sfc->dll_cells[cs] = left + (right - left) * 2 / 5; 785 else 786 sfc->dll_cells[cs] = left + (right - left) / 2; 787 } else { 788 sfc->dll_cells[cs] = 0; 789 } 790 791 if (sfc->dll_cells[cs]) { 792 dev_dbg(sfc->dev, "%d %d %d dll training success in %dMHz max_cells=%u sfc_ver=%d\n", 793 left, right, sfc->dll_cells[cs], sfc->speed[cs], 794 rockchip_sfc_get_max_dll_cells(sfc), rockchip_sfc_get_version(sfc)); 795 rockchip_sfc_set_delay_lines(sfc, (u16)sfc->dll_cells[cs], cs); 796 } else { 797 dev_err(sfc->dev, "%d %d dll training failed in %dMHz, reduce the speed\n", 798 left, right, sfc->speed[cs]); 799 rockchip_sfc_set_delay_lines(sfc, 0, cs); 800 rockchip_sfc_clk_set_rate(sfc, SFC_DLL_THRESHOLD_RATE); 801 sfc->cur_speed = SFC_DLL_THRESHOLD_RATE; 802 sfc->cur_real_speed = rockchip_sfc_clk_get_rate(sfc); 803 sfc->speed[cs] = SFC_DLL_THRESHOLD_RATE; 804 } 805 } 806 807 #endif 808 809 static int rockchip_sfc_exec_op(struct spi_slave *mem, 810 const struct spi_mem_op *op) 811 { 812 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 813 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(mem->dev); 814 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 815 int ret; 816 817 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4 && 818 sfc->cur_speed != sfc->speed[plat->cs]) { 819 sfc->speed[plat->cs] = sfc->cur_speed; 820 #if CONFIG_IS_ENABLED(CLK) 821 if (sfc->cur_real_speed > SFC_DLL_THRESHOLD_RATE) 822 rockchip_sfc_delay_lines_tuning(sfc, mem); 823 else 824 #endif 825 rockchip_sfc_set_delay_lines(sfc, 0, plat->cs); 826 } 827 828 /* Wait for last async transfer finished */ 829 if (sfc->last_async_size) { 830 rockchip_sfc_wait_for_dma_finished(sfc, sfc->last_async_size); 831 sfc->last_async_size = 0; 832 } 833 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 834 rockchip_spi_set_cs(sfc, mem, true); 835 rockchip_sfc_xfer_setup(sfc, mem, op, len); 836 if (len) { 837 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) { 838 if (mem->mode & SPI_DMA_PREPARE) 839 return rockchip_sfc_xfer_data_dma_async(sfc, op, len); 840 ret = rockchip_sfc_xfer_data_dma(sfc, op, len); 841 } else { 842 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 843 } 844 845 if (ret != len) { 846 dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); 847 848 return -EIO; 849 } 850 } 851 852 ret = rockchip_sfc_xfer_done(sfc, 100000); 853 rockchip_spi_set_cs(sfc, mem, false); 854 855 return ret; 856 } 857 858 static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op) 859 { 860 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 861 862 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); 863 864 return 0; 865 } 866 867 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 868 { 869 struct rockchip_sfc *sfc = dev_get_platdata(bus); 870 871 if (speed > sfc->max_freq) 872 speed = sfc->max_freq; 873 874 if (speed == sfc->cur_speed) 875 return 0; 876 877 #if CONFIG_IS_ENABLED(CLK) 878 int ret = rockchip_sfc_clk_set_rate(sfc, speed); 879 880 if (ret < 0) { 881 dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", 882 speed); 883 return ret; 884 } 885 sfc->cur_speed = speed; 886 sfc->cur_real_speed = rockchip_sfc_clk_get_rate(sfc); 887 888 dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%dHz\n", 889 sfc->cur_speed, sfc->cur_real_speed); 890 #else 891 dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); 892 #endif 893 return 0; 894 } 895 896 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 897 { 898 return 0; 899 } 900 901 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { 902 .adjust_op_size = rockchip_sfc_adjust_op_size, 903 .exec_op = rockchip_sfc_exec_op, 904 }; 905 906 static const struct dm_spi_ops rockchip_sfc_ops = { 907 .mem_ops = &rockchip_sfc_mem_ops, 908 .set_speed = rockchip_sfc_set_speed, 909 .set_mode = rockchip_sfc_set_mode, 910 }; 911 912 static const struct udevice_id rockchip_sfc_ids[] = { 913 { .compatible = "rockchip,fspi"}, 914 { .compatible = "rockchip,sfc"}, 915 {}, 916 }; 917 918 U_BOOT_DRIVER(rockchip_sfc_driver) = { 919 .name = "rockchip_sfc", 920 .id = UCLASS_SPI, 921 .of_match = rockchip_sfc_ids, 922 .ops = &rockchip_sfc_ops, 923 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 924 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc), 925 .probe = rockchip_sfc_probe, 926 }; 927