1 /* 2 * SFC driver for rockchip 3 * 4 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 5 * Yifeng.zhao, Software Engineering, <zhao0116@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <bouncebuf.h> 12 #include <clk.h> 13 #include <dm.h> 14 #include <dt-structs.h> 15 #include <errno.h> 16 #include <spi.h> 17 #include <linux/errno.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/periph.h> 21 #include <dm/pinctrl.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #ifdef SFC_DEBUG 26 #define SFC_DBG printf 27 #else 28 #define SFC_DBG(args...) 29 #endif 30 31 struct rockchip_sfc_reg { 32 u32 ctrl; 33 u32 imr; 34 u32 iclr; 35 u32 ftlr; 36 u32 rcvr; 37 u32 ax; 38 u32 abit; 39 u32 isr; 40 u32 fsr; 41 u32 sr; 42 u32 risr; 43 u32 reserved[21]; 44 u32 dmatr; 45 u32 dmaaddr; 46 u32 reserved1[30]; 47 u32 cmd; 48 u32 addr; 49 u32 data; 50 }; 51 52 check_member(rockchip_sfc_reg, data, 0x108); 53 54 /*SFC_CTRL*/ 55 #define SFC_DATA_WIDTH_SHIFT 12 56 #define SFC_DATA_WIDTH_MASK GENMASK(13, 12) 57 #define SFC_ADDR_WIDTH_SHIFT 10 58 #define SFC_ADDR_WIDTH_MASK GENMASK(11, 10) 59 #define SFC_CMD_WIDTH_SHIFT 8 60 #define SFC_CMD_WIDTH_MASK GENMASK(9, 8) 61 #define SFC_DATA_SHIFT_NEGETIVE BIT(1) 62 63 /*SFC_CMD*/ 64 #define SFC_DUMMY_BITS_SHIFT 8 65 #define SFC_RW_SHIFT 12 66 #define SFC_WR 1 67 #define SFC_RD 0 68 #define SFC_ADDR_BITS_SHIFT 14 69 #define SFC_ADDR_BITS_MASK GENMASK(15, 14) 70 #define SFC_ADDR_0BITS 0 71 #define SFC_ADDR_24BITS 1 72 #define SFC_ADDR_32BITS 2 73 #define SFC_ADDR_XBITS 3 74 #define SFC_TRB_SHIFT (16) 75 #define SFC_TRB_MASK GENMASK(29, 16) 76 77 /* Dma start trigger signal. Auto cleared after write */ 78 #define SFC_DMA_START BIT(0) 79 80 #define SFC_RESET BIT(0) 81 82 /*SFC_FSR*/ 83 #define SFC_RXLV_SHIFT (16) 84 #define SFC_RXLV_MASK GENMASK(20, 16) 85 #define SFC_TXLV_SHIFT (8) 86 #define SFC_TXLV_MASK GENMASK(12, 8) 87 #define SFC_RX_FULL BIT(3) /* rx fifo full */ 88 #define SFC_RX_EMPTY BIT(2) /* rx fifo empty */ 89 #define SFC_TX_EMPTY BIT(1) /* tx fifo empty */ 90 #define SFC_TX_FULL BIT(0) /* tx fifo full */ 91 92 #define SFC_BUSY BIT(0) /* sfc busy flag */ 93 94 /*SFC_RISR*/ 95 #define DMA_FINISH_INT BIT(7) /* dma interrupt */ 96 #define SPI_ERR_INT BIT(6) /* Nspi error interrupt */ 97 #define AHB_ERR_INT BIT(5) /* Ahb bus error interrupt */ 98 #define TRANS_FINISH_INT BIT(4) /* Transfer finish interrupt */ 99 #define TX_EMPTY_INT BIT(3) /* Tx fifo empty interrupt */ 100 #define TX_OF_INT BIT(2) /* Tx fifo overflow interrupt */ 101 #define RX_UF_INT BIT(1) /* Rx fifo underflow interrupt */ 102 #define RX_FULL_INT BIT(0) /* Rx fifo full interrupt */ 103 104 #define SFC_MAX_TRB (512 * 31) 105 106 #define SFC_MAX_RATE (150 * 1000 * 1000) 107 #define SFC_DEFAULT_RATE (80 * 1000 * 1000) 108 #define SFC_MIN_RATE (10 * 1000 * 1000) 109 110 enum rockchip_sfc_if_type { 111 IF_TYPE_STD, 112 IF_TYPE_DUAL, 113 IF_TYPE_QUAD, 114 }; 115 116 struct rockchip_sfc_platdata { 117 s32 frequency; 118 void *base; 119 }; 120 121 struct rockchip_sfc { 122 struct rockchip_sfc_reg *regbase; 123 struct clk clk; 124 unsigned int max_freq; 125 unsigned int mode; 126 unsigned int speed_hz; 127 u32 cmd; 128 u32 addr; 129 u8 addr_bits; 130 u8 addr_xbits_ext; 131 u8 dummy_bits; 132 u8 rw; 133 u32 trb; 134 }; 135 136 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 137 { 138 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 139 struct rockchip_sfc *sfc = dev_get_priv(bus); 140 int ret; 141 142 plat->base = dev_read_addr_ptr(bus); 143 ret = clk_get_by_index(bus, 0, &sfc->clk); 144 if (ret < 0) { 145 printf("Could not get clock for %s: %d\n", bus->name, ret); 146 return ret; 147 } 148 149 return 0; 150 } 151 152 static int rockchip_sfc_probe(struct udevice *bus) 153 { 154 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 155 struct rockchip_sfc *sfc = dev_get_priv(bus); 156 struct dm_spi_bus *dm_spi_bus; 157 158 dm_spi_bus = bus->uclass_priv; 159 dm_spi_bus->max_hz = plat->frequency; 160 sfc->regbase = (struct rockchip_sfc_reg *)plat->base; 161 sfc->max_freq = SFC_MAX_RATE; 162 sfc->speed_hz = SFC_DEFAULT_RATE; 163 clk_set_rate(&sfc->clk, sfc->speed_hz); 164 165 return 0; 166 } 167 168 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 169 { 170 struct rockchip_sfc_reg *regs = sfc->regbase; 171 int tbase = get_timer(0); 172 u32 rcvr; 173 int ret = 0; 174 175 writel(SFC_RESET, ®s->rcvr); 176 do { 177 rcvr = readl(®s->rcvr); 178 if (get_timer(tbase) > 1000) { 179 debug("sfc reset timeout\n"); 180 ret = -ETIMEDOUT; 181 break; 182 } 183 udelay(1); 184 } while (rcvr); 185 186 writel(0xFFFFFFFF, ®s->iclr); 187 188 debug("sfc reset\n"); 189 190 return ret; 191 } 192 193 /* The SFC_CTRL register is a global control register, 194 * when the controller is in busy state(SFC_SR), 195 * SFC_CTRL cannot be set. 196 */ 197 static int rockchip_sfc_wait_idle(struct rockchip_sfc *sfc, 198 u32 timeout_ms) 199 { 200 struct rockchip_sfc_reg *regs = sfc->regbase; 201 unsigned long tbase = get_timer(0); 202 u32 sr, fsr; 203 204 while (1) { 205 sr = readl(®s->sr); 206 fsr = readl(®s->fsr); 207 if ((fsr & SFC_TX_EMPTY) && 208 (fsr & SFC_RX_EMPTY) && 209 !(sr & SFC_BUSY)) 210 break; 211 if (get_timer(tbase) > timeout_ms) { 212 printf("waite sfc idle timeout(sr:0x%08x fsr:0x%08x)\n", 213 sr, fsr); 214 rockchip_sfc_reset(sfc); 215 return -ETIMEDOUT; 216 } 217 udelay(100); 218 } 219 220 return 0; 221 } 222 223 static u8 rockchip_sfc_get_if_type(struct rockchip_sfc *sfc) 224 { 225 int type = IF_TYPE_STD; 226 227 if (sfc->rw == SFC_WR) { 228 if (sfc->mode & SPI_TX_QUAD) 229 type = IF_TYPE_QUAD; 230 else if (sfc->mode & SPI_TX_DUAL) 231 type = IF_TYPE_DUAL; 232 else 233 type = IF_TYPE_STD; 234 } else { 235 if (sfc->mode & SPI_RX_QUAD) 236 type = IF_TYPE_QUAD; 237 else if (sfc->mode & SPI_RX_DUAL) 238 type = IF_TYPE_DUAL; 239 else 240 type = IF_TYPE_STD; 241 } 242 243 return type; 244 } 245 246 static void rockchip_sfc_setup_xfer(struct rockchip_sfc *sfc, u32 trb) 247 { 248 struct rockchip_sfc_reg *regs = sfc->regbase; 249 u32 val = 0x02; 250 u8 data_width = IF_TYPE_STD; 251 252 SFC_DBG("--- sfc.addr_bit %x\n", sfc->addr_bits); 253 254 if (sfc->addr_bits == SFC_ADDR_24BITS || 255 sfc->addr_bits == SFC_ADDR_32BITS) 256 data_width = rockchip_sfc_get_if_type(sfc); 257 258 if (sfc->addr_bits == SFC_ADDR_XBITS) 259 writel(sfc->addr_xbits_ext - 1, ®s->abit); 260 261 val |= (data_width << SFC_DATA_WIDTH_SHIFT); 262 263 rockchip_sfc_wait_idle(sfc, 10); 264 265 SFC_DBG("--- sfc.ctrl %x\n", val); 266 writel(val, ®s->ctrl); 267 268 val = sfc->cmd; 269 val |= trb << SFC_TRB_SHIFT; 270 val |= sfc->rw << SFC_RW_SHIFT; 271 val |= sfc->addr_bits << SFC_ADDR_BITS_SHIFT; 272 val |= sfc->dummy_bits << SFC_DUMMY_BITS_SHIFT; 273 274 SFC_DBG("--- sfc.cmd %x\n", val); 275 writel(val, ®s->cmd); 276 277 if (sfc->addr_bits & SFC_ADDR_XBITS) { 278 SFC_DBG("--- sfc.addr %x\n", sfc->addr); 279 writel(sfc->addr, ®s->addr); 280 } 281 } 282 283 static int rockchip_sfc_dma_xfer(struct rockchip_sfc *sfc, void *buffer, size_t trb) 284 { 285 struct rockchip_sfc_reg *regs = sfc->regbase; 286 struct bounce_buffer bb; 287 unsigned int bb_flags; 288 int timeout = 1000; 289 int ret = 0; 290 int risr; 291 unsigned long tbase; 292 293 if (sfc->rw == SFC_WR) 294 bb_flags = GEN_BB_READ; 295 else 296 bb_flags = GEN_BB_WRITE; 297 298 ret = bounce_buffer_start(&bb, buffer, trb, bb_flags); 299 if (ret) 300 return ret; 301 302 rockchip_sfc_setup_xfer(sfc, bb.len_aligned); 303 304 writel(0xFFFFFFFF, ®s->iclr); 305 writel((unsigned long)bb.bounce_buffer, ®s->dmaaddr); 306 writel(SFC_DMA_START, ®s->dmatr); 307 308 tbase = get_timer(0); 309 do { 310 udelay(1); 311 risr = readl(®s->risr); 312 if (get_timer(tbase) > timeout) { 313 debug("dma timeout\n"); 314 ret = -ETIMEDOUT; 315 break; 316 } 317 } while (!(risr & TRANS_FINISH_INT)); 318 319 writel(0xFFFFFFFF, ®s->iclr); 320 321 bounce_buffer_stop(&bb); 322 323 return ret; 324 } 325 326 static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int rw, 327 u32 timeout) 328 { 329 struct rockchip_sfc_reg *regs = sfc->regbase; 330 unsigned long tbase = get_timer(0); 331 u8 level; 332 u32 fsr; 333 334 do { 335 fsr = readl(®s->fsr); 336 if (rw == SFC_WR) 337 level = (fsr & SFC_TXLV_MASK) >> SFC_TXLV_SHIFT; 338 else 339 level = (fsr & SFC_RXLV_MASK) >> SFC_RXLV_SHIFT; 340 if (get_timer(tbase) > timeout) 341 return -ETIMEDOUT; 342 udelay(1); 343 } while (!level); 344 345 return level; 346 } 347 348 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 349 { 350 struct rockchip_sfc_reg *regs = sfc->regbase; 351 u32 bytes = len & 0x3; 352 u32 words = len >> 2; 353 int tx_level = 0; 354 u32 val = 0; 355 u8 count; 356 357 while (words) { 358 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 359 if (tx_level <= 0) 360 return tx_level; 361 count = min(words, (u32)tx_level); 362 writesl(®s->data, buf, count); 363 buf += count; 364 words -= count; 365 } 366 367 /* handle the last non 4byte aligned bytes */ 368 if (bytes) { 369 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 370 if (tx_level <= 0) 371 return tx_level; 372 memcpy(&val, buf, bytes); 373 writel(val, ®s->data); 374 } 375 376 return 0; 377 } 378 379 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 380 { 381 struct rockchip_sfc_reg *regs = sfc->regbase; 382 u32 bytes = len & 0x3; 383 u32 words = len >> 2; 384 int rx_level = 0; 385 u32 count; 386 u32 val; 387 388 while (words) { 389 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 390 if (rx_level <= 0) 391 return rx_level; 392 count = min(words, (u32)rx_level); 393 readsl(®s->data, buf, count); 394 buf += count; 395 words -= count; 396 } 397 398 /* handle the last non 4 bytes aligned bytes */ 399 if (bytes) { 400 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 401 if (rx_level <= 0) 402 return rx_level; 403 val = readl(®s->data); 404 memcpy(buf, &val, bytes); 405 } 406 407 return 0; 408 } 409 410 static int rockchip_sfc_pio_xfer(struct rockchip_sfc *sfc, void *buf, u32 len) 411 { 412 int ret = 0; 413 414 rockchip_sfc_setup_xfer(sfc, len); 415 416 if (len) { 417 if (sfc->rw == SFC_WR) 418 ret = rockchip_sfc_write_fifo(sfc, (u32 *)buf, len); 419 else 420 ret = rockchip_sfc_read_fifo(sfc, (u32 *)buf, len); 421 } 422 423 return ret; 424 } 425 426 static int rockchip_sfc_read(struct rockchip_sfc *sfc, u32 offset, 427 void *buf, size_t len) 428 { 429 u32 dma_trans; 430 u32 trb; 431 u8 bytes; 432 int ret; 433 434 if (len >= ARCH_DMA_MINALIGN) { 435 bytes = len & (ARCH_DMA_MINALIGN - 1); 436 dma_trans = len - bytes; 437 } else { 438 dma_trans = 0; 439 bytes = len; 440 } 441 442 while (dma_trans) { 443 trb = min_t(size_t, dma_trans, SFC_MAX_TRB); 444 ret = rockchip_sfc_dma_xfer(sfc, buf, trb); 445 if (ret < 0) 446 return ret; 447 dma_trans -= trb; 448 sfc->addr += trb; 449 buf += trb; 450 } 451 452 /* 453 * transfer the last non dma anligned byte by pio mode 454 */ 455 if (bytes) 456 ret = rockchip_sfc_pio_xfer(sfc, buf, bytes); 457 458 return 0; 459 } 460 461 static int rockchip_sfc_write(struct rockchip_sfc *sfc, u32 offset, 462 void *buf, size_t len) 463 { 464 if (len > SFC_MAX_TRB) { 465 printf("out of the max sfc trb"); 466 return -EINVAL; 467 } 468 469 if (len && !(len & (ARCH_DMA_MINALIGN - 1))) 470 return rockchip_sfc_dma_xfer(sfc, buf, len); 471 else 472 return rockchip_sfc_pio_xfer(sfc, buf, len); 473 474 return 0; 475 } 476 477 static int rockchip_sfc_do_xfer(struct rockchip_sfc *sfc, void *buf, size_t len) 478 { 479 if (sfc->rw) 480 return rockchip_sfc_write(sfc, sfc->addr, buf, len); 481 else 482 return rockchip_sfc_read(sfc, sfc->addr, buf, len); 483 } 484 485 static int rockchip_sfc_xfer(struct udevice *dev, unsigned int bitlen, 486 const void *dout, void *din, unsigned long flags) 487 { 488 struct udevice *bus = dev->parent; 489 struct rockchip_sfc *sfc = dev_get_priv(bus); 490 int len = bitlen >> 3; 491 u8 *pcmd = (u8 *)dout; 492 void *data_buf; 493 int ret = 0; 494 495 if (flags & SPI_XFER_BEGIN) { 496 sfc->cmd = pcmd[0]; 497 switch (len) { 498 case 6: /* Nor >16MB 0x6b dummy op */ 499 sfc->addr_bits = SFC_ADDR_32BITS; 500 sfc->dummy_bits = 8; 501 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 502 break; 503 case 5: /* Nor <=16MB 0x6b dummy op, Nor >16MB no dummy op */ 504 if (sfc->cmd == 0x6b) { 505 sfc->addr_bits = SFC_ADDR_24BITS; 506 sfc->dummy_bits = 8; 507 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 508 } else { 509 sfc->addr_bits = SFC_ADDR_32BITS; 510 sfc->dummy_bits = 0; 511 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 512 } 513 break; 514 case 4: /* Nand erase and read, Nor <=16MB no dummy op */ 515 sfc->addr_bits = SFC_ADDR_24BITS; 516 sfc->dummy_bits = 0; 517 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 518 break; 519 case 3: /* Nand prog, */ 520 sfc->addr_bits = SFC_ADDR_XBITS; 521 sfc->addr_xbits_ext = 16; 522 sfc->dummy_bits = 0; 523 sfc->addr = pcmd[2] | pcmd[1] << 8; 524 break; 525 case 2: /* Nand read/write feature */ 526 sfc->addr_bits = SFC_ADDR_XBITS; 527 sfc->addr_xbits_ext = 8; 528 sfc->dummy_bits = 0; 529 sfc->addr = pcmd[1]; 530 break; 531 default: /* Nand/Nor Read/Write status */ 532 sfc->addr_bits = SFC_ADDR_0BITS; 533 sfc->dummy_bits = 0; 534 sfc->addr = 0; 535 break; 536 } 537 SFC_DBG("%s %d %x %d %d %x\n", __func__, len, sfc->cmd, sfc->addr_bits, 538 sfc->dummy_bits, sfc->addr); 539 } 540 if (flags & SPI_XFER_END) { 541 if (din) { 542 sfc->rw = SFC_RD; 543 data_buf = din; 544 } else { 545 sfc->rw = SFC_WR; 546 data_buf = (void *)dout; 547 } 548 549 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 550 len = 0; 551 data_buf = NULL; 552 } 553 554 if (sfc->cmd == 0x9f && len == 4) { 555 /* SPI Nand read id */ 556 sfc->addr_bits = SFC_ADDR_XBITS; 557 sfc->addr_xbits_ext = 8; 558 sfc->dummy_bits = 0; 559 sfc->addr = 0; 560 ((u8 *)data_buf)[0] = 0xff; 561 ret = rockchip_sfc_do_xfer(sfc, &((u8 *)data_buf)[1], 3); 562 } else { 563 ret = rockchip_sfc_do_xfer(sfc, data_buf, len); 564 } 565 } 566 567 return ret; 568 } 569 570 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 571 { 572 struct rockchip_sfc *sfc = dev_get_priv(bus); 573 574 if (speed > sfc->max_freq) 575 speed = sfc->max_freq; 576 577 sfc->speed_hz = speed; 578 clk_set_rate(&sfc->clk, sfc->speed_hz); 579 SFC_DBG("%s clk= %ld\n", __func__, clk_get_rate(&sfc->clk)); 580 581 return 0; 582 } 583 584 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 585 { 586 struct rockchip_sfc *sfc = dev_get_priv(bus); 587 588 sfc->mode = mode; 589 590 return 0; 591 } 592 593 static const struct dm_spi_ops rockchip_sfc_ops = { 594 .xfer = rockchip_sfc_xfer, 595 .set_speed = rockchip_sfc_set_speed, 596 .set_mode = rockchip_sfc_set_mode, 597 }; 598 599 static const struct udevice_id rockchip_sfc_ids[] = { 600 { .compatible = "rockchip,sfc" }, 601 { } 602 }; 603 604 U_BOOT_DRIVER(rockchip_sfc_driver) = { 605 .name = "rockchip_sfc", 606 .id = UCLASS_SPI, 607 .of_match = rockchip_sfc_ids, 608 .ops = &rockchip_sfc_ops, 609 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 610 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc_platdata), 611 .priv_auto_alloc_size = sizeof(struct rockchip_sfc), 612 .probe = rockchip_sfc_probe, 613 }; 614