1 /* 2 * SFC driver for rockchip 3 * 4 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 5 * Yifeng.zhao, Software Engineering, <zhao0116@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <bouncebuf.h> 12 #include <clk.h> 13 #include <dm.h> 14 #include <dt-structs.h> 15 #include <errno.h> 16 #include <spi.h> 17 #include <linux/errno.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/periph.h> 21 #include <dm/pinctrl.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #ifdef SFC_DEBUG 26 #define SFC_DBG printf 27 #else 28 #define SFC_DBG(args...) 29 #endif 30 31 struct rockchip_sfc_reg { 32 u32 ctrl; 33 u32 imr; 34 u32 iclr; 35 u32 ftlr; 36 u32 rcvr; 37 u32 ax; 38 u32 abit; 39 u32 isr; 40 u32 fsr; 41 u32 sr; 42 u32 risr; 43 u32 ver; 44 u32 qop; 45 u32 ext_ctrl; 46 u32 reserved; 47 u32 dll_ctrl0; 48 u32 reserved1[16]; 49 u32 dmatr; 50 u32 dmaaddr; 51 u32 len_ctrl; 52 u32 len_ext; 53 u32 reserved2[28]; 54 u32 cmd; 55 u32 addr; 56 u32 data; 57 }; 58 59 check_member(rockchip_sfc_reg, data, 0x108); 60 61 /*SFC_CTRL*/ 62 #define SFC_DATA_WIDTH_SHIFT 12 63 #define SFC_DATA_WIDTH_MASK GENMASK(13, 12) 64 #define SFC_ADDR_WIDTH_SHIFT 10 65 #define SFC_ADDR_WIDTH_MASK GENMASK(11, 10) 66 #define SFC_CMD_WIDTH_SHIFT 8 67 #define SFC_CMD_WIDTH_MASK GENMASK(9, 8) 68 #define SFC_DATA_SHIFT_NEGETIVE BIT(1) 69 70 /*SFC_CMD*/ 71 #define SFC_DUMMY_BITS_SHIFT 8 72 #define SFC_RW_SHIFT 12 73 #define SFC_WR 1 74 #define SFC_RD 0 75 #define SFC_ADDR_BITS_SHIFT 14 76 #define SFC_ADDR_BITS_MASK GENMASK(15, 14) 77 #define SFC_ADDR_0BITS 0 78 #define SFC_ADDR_24BITS 1 79 #define SFC_ADDR_32BITS 2 80 #define SFC_ADDR_XBITS 3 81 #define SFC_TRB_SHIFT (16) 82 #define SFC_TRB_MASK GENMASK(29, 16) 83 84 /* Dma start trigger signal. Auto cleared after write */ 85 #define SFC_DMA_START BIT(0) 86 87 #define SFC_RESET BIT(0) 88 89 /*SFC_FSR*/ 90 #define SFC_RXLV_SHIFT (16) 91 #define SFC_RXLV_MASK GENMASK(20, 16) 92 #define SFC_TXLV_SHIFT (8) 93 #define SFC_TXLV_MASK GENMASK(12, 8) 94 #define SFC_RX_FULL BIT(3) /* rx fifo full */ 95 #define SFC_RX_EMPTY BIT(2) /* rx fifo empty */ 96 #define SFC_TX_EMPTY BIT(1) /* tx fifo empty */ 97 #define SFC_TX_FULL BIT(0) /* tx fifo full */ 98 99 #define SFC_BUSY BIT(0) /* sfc busy flag */ 100 101 /*SFC_RISR*/ 102 #define DMA_FINISH_INT BIT(7) /* dma interrupt */ 103 #define SPI_ERR_INT BIT(6) /* Nspi error interrupt */ 104 #define AHB_ERR_INT BIT(5) /* Ahb bus error interrupt */ 105 #define TRANS_FINISH_INT BIT(4) /* Transfer finish interrupt */ 106 #define TX_EMPTY_INT BIT(3) /* Tx fifo empty interrupt */ 107 #define TX_OF_INT BIT(2) /* Tx fifo overflow interrupt */ 108 #define RX_UF_INT BIT(1) /* Rx fifo underflow interrupt */ 109 #define RX_FULL_INT BIT(0) /* Rx fifo full interrupt */ 110 111 /*SFC_DLL_CTRL0*/ 112 #define DLL_CTRL0_SCLK_SMP_DLL BIT(15) /* SCLK sampling enable dll */ 113 #define DLL_CTRL0_DLL_MAX_VER4 0xFFU 114 #define DLL_CTRL0_DLL_MAX_VER5 0x1FFU 115 116 #define SFC_MAX_TRB_VER3 (512 * 31) 117 #define SFC_MAX_TRB_VER4 (0xFFFFFFFF) 118 119 #define SFC_MAX_RATE (150 * 1000 * 1000) 120 #define SFC_DLL_THRESHOLD_RATE (100 * 1000 * 1000) 121 #define SFC_DEFAULT_RATE (80 * 1000 * 1000) 122 #define SFC_MIN_RATE (10 * 1000 * 1000) 123 124 #define SFC_VER_3 0x3 125 #define SFC_VER_4 0x4 126 #define SFC_VER_5 0x5 127 128 enum rockchip_sfc_if_type { 129 IF_TYPE_STD, 130 IF_TYPE_DUAL, 131 IF_TYPE_QUAD, 132 }; 133 134 struct rockchip_sfc_platdata { 135 s32 frequency; 136 void *base; 137 }; 138 139 struct rockchip_sfc { 140 struct rockchip_sfc_reg *regbase; 141 struct clk clk; 142 unsigned int max_freq; 143 unsigned int mode; 144 unsigned int speed_hz; 145 u32 max_iosize; 146 u32 max_dll_cells; 147 bool prepare; 148 u32 last_prepare_size; 149 u32 cmd; 150 u32 addr; 151 u8 addr_bits; 152 u8 addr_xbits_ext; 153 u8 dummy_bits; 154 u8 rw; 155 u32 trb; 156 }; 157 158 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 159 { 160 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 161 162 plat->base = dev_read_addr_ptr(bus); 163 #if CONFIG_IS_ENABLED(CLK) 164 struct rockchip_sfc *sfc = dev_get_priv(bus); 165 int ret; 166 167 ret = clk_get_by_index(bus, 0, &sfc->clk); 168 if (ret < 0) { 169 printf("Could not get clock for %s: %d\n", bus->name, ret); 170 return ret; 171 } 172 #endif 173 174 return 0; 175 } 176 177 u32 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 178 { 179 struct rockchip_sfc_reg *regs = sfc->regbase; 180 181 return (u32)(readl(®s->ver) & 0xFFFF); 182 } 183 184 int rockchip_sfc_set_delay_lines(struct rockchip_sfc *sfc, u32 cells) 185 { 186 struct rockchip_sfc_reg *regs = sfc->regbase; 187 188 if (cells > sfc->max_dll_cells) 189 cells = sfc->max_dll_cells; 190 191 return writel(DLL_CTRL0_SCLK_SMP_DLL | cells, ®s->dll_ctrl0); 192 } 193 194 int rockchip_sfc_disable_delay_lines(struct rockchip_sfc *sfc) 195 { 196 struct rockchip_sfc_reg *regs = sfc->regbase; 197 198 return writel(0, ®s->dll_ctrl0); 199 } 200 201 static int rockchip_sfc_probe(struct udevice *bus) 202 { 203 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 204 struct rockchip_sfc *sfc = dev_get_priv(bus); 205 struct rockchip_sfc_reg *regs; 206 struct dm_spi_bus *dm_spi_bus; 207 208 dm_spi_bus = bus->uclass_priv; 209 dm_spi_bus->max_hz = plat->frequency; 210 sfc->regbase = (struct rockchip_sfc_reg *)plat->base; 211 sfc->max_freq = SFC_MAX_RATE; 212 sfc->speed_hz = SFC_DEFAULT_RATE; 213 #if CONFIG_IS_ENABLED(CLK) 214 clk_set_rate(&sfc->clk, sfc->speed_hz); 215 #endif 216 regs = sfc->regbase; 217 switch (rockchip_sfc_get_version(sfc)) { 218 case SFC_VER_5: 219 sfc->max_dll_cells = DLL_CTRL0_DLL_MAX_VER5; 220 sfc->max_iosize = SFC_MAX_TRB_VER4; 221 writel(1, ®s->len_ctrl); 222 break; 223 case SFC_VER_4: 224 sfc->max_dll_cells = DLL_CTRL0_DLL_MAX_VER4; 225 sfc->max_iosize = SFC_MAX_TRB_VER4; 226 writel(1, ®s->len_ctrl); 227 break; 228 default: 229 sfc->max_iosize = SFC_MAX_TRB_VER3; 230 break; 231 } 232 233 return 0; 234 } 235 236 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 237 { 238 struct rockchip_sfc_reg *regs = sfc->regbase; 239 int tbase = get_timer(0); 240 u32 rcvr; 241 int ret = 0; 242 243 writel(SFC_RESET, ®s->rcvr); 244 do { 245 rcvr = readl(®s->rcvr); 246 if (get_timer(tbase) > 1000) { 247 debug("sfc reset timeout\n"); 248 ret = -ETIMEDOUT; 249 break; 250 } 251 udelay(1); 252 } while (rcvr); 253 254 writel(0xFFFFFFFF, ®s->iclr); 255 256 debug("sfc reset\n"); 257 258 return ret; 259 } 260 261 static int rockchip_sfc_dma_xfer_wait_finished(struct rockchip_sfc *sfc) 262 { 263 struct rockchip_sfc_reg *regs = sfc->regbase; 264 int timeout = sfc->last_prepare_size * 10; 265 unsigned long tbase; 266 int ret = 0; 267 int risr; 268 269 tbase = get_timer(0); 270 do { 271 udelay(1); 272 risr = readl(®s->risr); 273 if (get_timer(tbase) > timeout) { 274 debug("dma timeout\n"); 275 ret = -ETIMEDOUT; 276 break; 277 } 278 } while (!(risr & TRANS_FINISH_INT)); 279 sfc->last_prepare_size = 0; 280 281 return ret; 282 } 283 284 /* The SFC_CTRL register is a global control register, 285 * when the controller is in busy state(SFC_SR), 286 * SFC_CTRL cannot be set. 287 */ 288 static int rockchip_sfc_wait_idle(struct rockchip_sfc *sfc, 289 u32 timeout_ms) 290 { 291 struct rockchip_sfc_reg *regs = sfc->regbase; 292 unsigned long tbase = get_timer(0); 293 u32 sr, fsr; 294 295 if (sfc->last_prepare_size && rockchip_sfc_dma_xfer_wait_finished(sfc)) 296 return -ETIMEDOUT; 297 298 while (1) { 299 sr = readl(®s->sr); 300 fsr = readl(®s->fsr); 301 if ((fsr & SFC_TX_EMPTY) && 302 (fsr & SFC_RX_EMPTY) && 303 !(sr & SFC_BUSY)) 304 break; 305 if (get_timer(tbase) > timeout_ms) { 306 printf("waite sfc idle timeout(sr:0x%08x fsr:0x%08x)\n", 307 sr, fsr); 308 rockchip_sfc_reset(sfc); 309 return -ETIMEDOUT; 310 } 311 udelay(100); 312 } 313 314 return 0; 315 } 316 317 static u8 rockchip_sfc_get_if_type(struct rockchip_sfc *sfc) 318 { 319 int type = IF_TYPE_STD; 320 321 if (sfc->rw == SFC_WR) { 322 if (sfc->mode & SPI_TX_QUAD) 323 type = IF_TYPE_QUAD; 324 else if (sfc->mode & SPI_TX_DUAL) 325 type = IF_TYPE_DUAL; 326 else 327 type = IF_TYPE_STD; 328 } else { 329 if (sfc->mode & SPI_RX_QUAD) 330 type = IF_TYPE_QUAD; 331 else if (sfc->mode & SPI_RX_DUAL) 332 type = IF_TYPE_DUAL; 333 else 334 type = IF_TYPE_STD; 335 } 336 337 return type; 338 } 339 340 static void rockchip_sfc_setup_xfer(struct rockchip_sfc *sfc, u32 trb) 341 { 342 struct rockchip_sfc_reg *regs = sfc->regbase; 343 u32 val; 344 u8 data_width = IF_TYPE_STD; 345 346 rockchip_sfc_wait_idle(sfc, 10); 347 348 if (sfc->addr_bits == SFC_ADDR_24BITS || 349 sfc->addr_bits == SFC_ADDR_32BITS) 350 data_width = rockchip_sfc_get_if_type(sfc); 351 352 SFC_DBG("--- sfc.addr_bit %x\n", sfc->addr_bits); 353 if (sfc->addr_bits == SFC_ADDR_XBITS) 354 writel(sfc->addr_xbits_ext - 1, ®s->abit); 355 356 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) { 357 SFC_DBG("--- sfc.len_ext %x\n", trb); 358 writel(trb, ®s->len_ext); 359 } 360 361 val = 0x2; 362 val |= (data_width << SFC_DATA_WIDTH_SHIFT); 363 364 SFC_DBG("--- sfc.ctrl %x\n", val); 365 writel(val, ®s->ctrl); 366 367 val = sfc->cmd; 368 val |= (trb & 0x3fff) << SFC_TRB_SHIFT; 369 val |= sfc->rw << SFC_RW_SHIFT; 370 val |= sfc->addr_bits << SFC_ADDR_BITS_SHIFT; 371 val |= sfc->dummy_bits << SFC_DUMMY_BITS_SHIFT; 372 373 SFC_DBG("--- sfc.cmd %x\n", val); 374 writel(val, ®s->cmd); 375 376 if (sfc->addr_bits & SFC_ADDR_XBITS) { 377 SFC_DBG("--- sfc.addr %x\n", sfc->addr); 378 writel(sfc->addr, ®s->addr); 379 } 380 } 381 382 static int rockchip_sfc_dma_xfer(struct rockchip_sfc *sfc, void *buffer, 383 size_t trb) 384 { 385 struct rockchip_sfc_reg *regs = sfc->regbase; 386 struct bounce_buffer bb; 387 unsigned int bb_flags; 388 int timeout = trb * 1000; 389 int ret = 0; 390 int risr; 391 unsigned long tbase; 392 393 if (sfc->rw == SFC_WR) 394 bb_flags = GEN_BB_READ; 395 else 396 bb_flags = GEN_BB_WRITE; 397 398 ret = bounce_buffer_start(&bb, buffer, trb, bb_flags); 399 if (ret) 400 return ret; 401 402 rockchip_sfc_setup_xfer(sfc, bb.len_aligned); 403 404 writel(0xFFFFFFFF, ®s->iclr); 405 writel((unsigned long)bb.bounce_buffer, ®s->dmaaddr); 406 writel(SFC_DMA_START, ®s->dmatr); 407 408 tbase = get_timer(0); 409 do { 410 udelay(1); 411 risr = readl(®s->risr); 412 if (get_timer(tbase) > timeout) { 413 debug("dma timeout\n"); 414 ret = -ETIMEDOUT; 415 break; 416 } 417 } while (!(risr & TRANS_FINISH_INT)); 418 419 writel(0xFFFFFFFF, ®s->iclr); 420 421 bounce_buffer_stop(&bb); 422 423 return ret; 424 } 425 426 static int rockchip_sfc_dma_xfer_prepare(struct rockchip_sfc *sfc, 427 void *buffer, size_t trb) 428 { 429 struct rockchip_sfc_reg *regs = sfc->regbase; 430 431 SFC_DBG("sfc_dma_xfer_prepar enter\n"); 432 433 rockchip_sfc_setup_xfer(sfc, trb); 434 sfc->last_prepare_size = trb; 435 436 flush_dcache_range((unsigned long)buffer, 437 (unsigned long)buffer + trb); 438 439 writel(0xFFFFFFFF, ®s->iclr); 440 writel((unsigned long)buffer, ®s->dmaaddr); 441 writel(SFC_DMA_START, ®s->dmatr); 442 443 return 0; 444 } 445 446 static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int rw, 447 u32 timeout) 448 { 449 struct rockchip_sfc_reg *regs = sfc->regbase; 450 unsigned long tbase = get_timer(0); 451 u8 level; 452 u32 fsr; 453 454 do { 455 fsr = readl(®s->fsr); 456 if (rw == SFC_WR) 457 level = (fsr & SFC_TXLV_MASK) >> SFC_TXLV_SHIFT; 458 else 459 level = (fsr & SFC_RXLV_MASK) >> SFC_RXLV_SHIFT; 460 if (get_timer(tbase) > timeout) 461 return -ETIMEDOUT; 462 udelay(1); 463 } while (!level); 464 465 return level; 466 } 467 468 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 469 { 470 struct rockchip_sfc_reg *regs = sfc->regbase; 471 u32 bytes = len & 0x3; 472 u32 words = len >> 2; 473 int tx_level = 0; 474 u32 val = 0; 475 u8 count; 476 477 while (words) { 478 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 479 if (tx_level <= 0) 480 return tx_level; 481 count = min(words, (u32)tx_level); 482 writesl(®s->data, buf, count); 483 buf += count; 484 words -= count; 485 } 486 487 /* handle the last non 4byte aligned bytes */ 488 if (bytes) { 489 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 490 if (tx_level <= 0) 491 return tx_level; 492 memcpy(&val, buf, bytes); 493 writel(val, ®s->data); 494 } 495 496 return 0; 497 } 498 499 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 500 { 501 struct rockchip_sfc_reg *regs = sfc->regbase; 502 u32 bytes = len & 0x3; 503 u32 words = len >> 2; 504 int rx_level = 0; 505 u32 count; 506 u32 val; 507 508 while (words) { 509 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 510 if (rx_level <= 0) 511 return rx_level; 512 count = min(words, (u32)rx_level); 513 readsl(®s->data, buf, count); 514 buf += count; 515 words -= count; 516 } 517 518 /* handle the last non 4 bytes aligned bytes */ 519 if (bytes) { 520 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 521 if (rx_level <= 0) 522 return rx_level; 523 val = readl(®s->data); 524 memcpy(buf, &val, bytes); 525 } 526 527 return 0; 528 } 529 530 static int rockchip_sfc_pio_xfer(struct rockchip_sfc *sfc, void *buf, u32 len) 531 { 532 int ret = 0; 533 534 rockchip_sfc_setup_xfer(sfc, len); 535 536 if (len) { 537 if (sfc->rw == SFC_WR) 538 ret = rockchip_sfc_write_fifo(sfc, (u32 *)buf, len); 539 else 540 ret = rockchip_sfc_read_fifo(sfc, (u32 *)buf, len); 541 } 542 543 return ret; 544 } 545 546 static int rockchip_sfc_read(struct rockchip_sfc *sfc, u32 offset, 547 void *buf, size_t len) 548 { 549 u32 dma_trans; 550 u32 trb; 551 u8 bytes; 552 int ret; 553 554 if (len >= ARCH_DMA_MINALIGN) { 555 bytes = len & (ARCH_DMA_MINALIGN - 1); 556 dma_trans = len - bytes; 557 } else { 558 dma_trans = 0; 559 bytes = len; 560 } 561 562 while (dma_trans) { 563 trb = min_t(size_t, dma_trans, sfc->max_iosize); 564 if (sfc->prepare) 565 ret = rockchip_sfc_dma_xfer_prepare(sfc, buf, len); 566 else 567 ret = rockchip_sfc_dma_xfer(sfc, buf, trb); 568 if (ret < 0) 569 return ret; 570 dma_trans -= trb; 571 sfc->addr += trb; 572 buf += trb; 573 } 574 575 /* 576 * transfer the last non dma anligned byte by pio mode 577 */ 578 if (bytes) 579 ret = rockchip_sfc_pio_xfer(sfc, buf, bytes); 580 581 return 0; 582 } 583 584 static int rockchip_sfc_write(struct rockchip_sfc *sfc, u32 offset, 585 void *buf, size_t len) 586 { 587 if (len > sfc->max_iosize) { 588 printf("out of the max sfc trb"); 589 return -EINVAL; 590 } 591 592 if (len && !(len & (ARCH_DMA_MINALIGN - 1))) 593 return rockchip_sfc_dma_xfer(sfc, buf, len); 594 else 595 return rockchip_sfc_pio_xfer(sfc, buf, len); 596 597 return 0; 598 } 599 600 static int rockchip_sfc_do_xfer(struct rockchip_sfc *sfc, void *buf, size_t len) 601 { 602 if (sfc->rw) 603 return rockchip_sfc_write(sfc, sfc->addr, buf, len); 604 else 605 return rockchip_sfc_read(sfc, sfc->addr, buf, len); 606 } 607 608 static int rockchip_sfc_xfer(struct udevice *dev, unsigned int bitlen, 609 const void *dout, void *din, unsigned long flags) 610 { 611 struct udevice *bus = dev->parent; 612 struct rockchip_sfc *sfc = dev_get_priv(bus); 613 int len = bitlen >> 3; 614 u8 *pcmd = (u8 *)dout; 615 void *data_buf; 616 int ret = 0; 617 618 if (flags & SPI_XFER_BEGIN) { 619 sfc->cmd = pcmd[0]; 620 switch (len) { 621 case 6: /* Nor >16MB 0x6b dummy op */ 622 sfc->addr_bits = SFC_ADDR_32BITS; 623 sfc->dummy_bits = 8; 624 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 625 break; 626 case 5: /* Nor <=16MB 0x6b dummy op, Nor >16MB no dummy op */ 627 if (sfc->cmd == 0x6b) { 628 sfc->addr_bits = SFC_ADDR_24BITS; 629 sfc->dummy_bits = 8; 630 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 631 } else { 632 sfc->addr_bits = SFC_ADDR_32BITS; 633 sfc->dummy_bits = 0; 634 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 635 } 636 break; 637 case 4: /* Nand erase and read, Nor <=16MB no dummy op */ 638 sfc->addr_bits = SFC_ADDR_24BITS; 639 sfc->dummy_bits = 0; 640 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 641 break; 642 case 3: /* Nand prog, */ 643 sfc->addr_bits = SFC_ADDR_XBITS; 644 sfc->addr_xbits_ext = 16; 645 sfc->dummy_bits = 0; 646 sfc->addr = pcmd[2] | pcmd[1] << 8; 647 break; 648 case 2: /* Nand read/write feature */ 649 sfc->addr_bits = SFC_ADDR_XBITS; 650 sfc->addr_xbits_ext = 8; 651 sfc->dummy_bits = 0; 652 sfc->addr = pcmd[1]; 653 break; 654 default: /* Nand/Nor Read/Write status */ 655 sfc->addr_bits = SFC_ADDR_0BITS; 656 sfc->dummy_bits = 0; 657 sfc->addr = 0; 658 break; 659 } 660 SFC_DBG("%s %d %x %d %d %x\n", __func__, len, sfc->cmd, 661 sfc->addr_bits, sfc->dummy_bits, sfc->addr); 662 } 663 if (flags & SPI_XFER_END) { 664 if (din) { 665 sfc->rw = SFC_RD; 666 data_buf = din; 667 } else { 668 sfc->rw = SFC_WR; 669 data_buf = (void *)dout; 670 } 671 672 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 673 len = 0; 674 data_buf = NULL; 675 } 676 677 sfc->prepare = flags & SPI_XFER_PREPARE ? true : false; 678 679 if (sfc->cmd == 0x9f && len == 4) { 680 /* SPI Nand read id */ 681 sfc->addr_bits = SFC_ADDR_XBITS; 682 sfc->addr_xbits_ext = 8; 683 sfc->dummy_bits = 0; 684 sfc->addr = 0; 685 ((u8 *)data_buf)[0] = 0xff; 686 ret = rockchip_sfc_do_xfer(sfc, &((u8 *)data_buf)[1], 3); 687 } else { 688 ret = rockchip_sfc_do_xfer(sfc, data_buf, len); 689 } 690 } 691 692 return ret; 693 } 694 695 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 696 { 697 struct rockchip_sfc *sfc = dev_get_priv(bus); 698 699 if (speed > sfc->max_freq) 700 speed = sfc->max_freq; 701 702 sfc->speed_hz = speed; 703 #if CONFIG_IS_ENABLED(CLK) 704 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4 && 705 sfc->speed_hz > SFC_DLL_THRESHOLD_RATE) { 706 u8 id[3], id_temp[3]; 707 int right, left = -1; 708 709 sfc->cmd = 0x9f; 710 sfc->addr = 0; 711 sfc->addr_bits = 0; 712 sfc->addr_xbits_ext = 8; 713 sfc->dummy_bits = 0; 714 sfc->rw = 0; 715 clk_set_rate(&sfc->clk, SFC_DLL_THRESHOLD_RATE); 716 rockchip_sfc_read(sfc, 0, (void *)&id, 3); 717 718 clk_set_rate(&sfc->clk, sfc->speed_hz); 719 sfc->speed_hz = clk_get_rate(&sfc->clk); 720 if (sfc->speed_hz > SFC_DLL_THRESHOLD_RATE) { 721 for (right = 10; right <= sfc->max_dll_cells; right += 10) { 722 rockchip_sfc_set_delay_lines(sfc, right); 723 rockchip_sfc_read(sfc, 0, (void *)&id_temp, 3); 724 SFC_DBG("sfc dll %d id= %x %x %x\n", right, 725 id_temp[0], id_temp[1], id_temp[2]); 726 if (left == -1 && !memcmp(&id, &id_temp, 3)) 727 left = right; 728 else if (left >= 0 && memcmp(&id, &id_temp, 3)) 729 break; 730 } 731 732 if (left >= 0 && (right - left > 50)) { 733 rockchip_sfc_set_delay_lines(sfc, (u32)((right + left) / 2)); 734 } else { 735 rockchip_sfc_disable_delay_lines(sfc); 736 sfc->speed_hz = SFC_DLL_THRESHOLD_RATE; 737 } 738 } 739 } else if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) { 740 rockchip_sfc_disable_delay_lines(sfc); 741 } 742 743 clk_set_rate(&sfc->clk, sfc->speed_hz); 744 SFC_DBG("%s clk= %ld\n", __func__, clk_get_rate(&sfc->clk)); 745 #endif 746 return 0; 747 } 748 749 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 750 { 751 struct rockchip_sfc *sfc = dev_get_priv(bus); 752 753 sfc->mode = mode; 754 755 return 0; 756 } 757 758 static const struct dm_spi_ops rockchip_sfc_ops = { 759 .xfer = rockchip_sfc_xfer, 760 .set_speed = rockchip_sfc_set_speed, 761 .set_mode = rockchip_sfc_set_mode, 762 }; 763 764 static const struct udevice_id rockchip_sfc_ids[] = { 765 { .compatible = "rockchip,sfc" }, 766 { } 767 }; 768 769 U_BOOT_DRIVER(rockchip_sfc_driver) = { 770 .name = "rockchip_sfc", 771 .id = UCLASS_SPI, 772 .of_match = rockchip_sfc_ids, 773 .ops = &rockchip_sfc_ops, 774 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 775 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc_platdata), 776 .priv_auto_alloc_size = sizeof(struct rockchip_sfc), 777 .probe = rockchip_sfc_probe, 778 }; 779