1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Serial Flash Controller Driver 4 * 5 * Copyright (c) 2017-2021, Rockchip Inc. 6 * Author: Shawn Lin <shawn.lin@rock-chips.com> 7 * Chris Morgan <macromorgan@hotmail.com> 8 * Jon Lin <Jon.lin@rock-chips.com> 9 */ 10 11 #include <asm/io.h> 12 #include <bouncebuf.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <linux/bitops.h> 16 #include <linux/delay.h> 17 #include <linux/iopoll.h> 18 #include <spi.h> 19 #include <spi-mem.h> 20 21 /* System control */ 22 #define SFC_CTRL 0x0 23 #define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) 24 #define SFC_CTRL_CMD_BITS_SHIFT 8 25 #define SFC_CTRL_ADDR_BITS_SHIFT 10 26 #define SFC_CTRL_DATA_BITS_SHIFT 12 27 28 /* Interrupt mask */ 29 #define SFC_IMR 0x4 30 #define SFC_IMR_RX_FULL BIT(0) 31 #define SFC_IMR_RX_UFLOW BIT(1) 32 #define SFC_IMR_TX_OFLOW BIT(2) 33 #define SFC_IMR_TX_EMPTY BIT(3) 34 #define SFC_IMR_TRAN_FINISH BIT(4) 35 #define SFC_IMR_BUS_ERR BIT(5) 36 #define SFC_IMR_NSPI_ERR BIT(6) 37 #define SFC_IMR_DMA BIT(7) 38 39 /* Interrupt clear */ 40 #define SFC_ICLR 0x8 41 #define SFC_ICLR_RX_FULL BIT(0) 42 #define SFC_ICLR_RX_UFLOW BIT(1) 43 #define SFC_ICLR_TX_OFLOW BIT(2) 44 #define SFC_ICLR_TX_EMPTY BIT(3) 45 #define SFC_ICLR_TRAN_FINISH BIT(4) 46 #define SFC_ICLR_BUS_ERR BIT(5) 47 #define SFC_ICLR_NSPI_ERR BIT(6) 48 #define SFC_ICLR_DMA BIT(7) 49 50 /* FIFO threshold level */ 51 #define SFC_FTLR 0xc 52 #define SFC_FTLR_TX_SHIFT 0 53 #define SFC_FTLR_TX_MASK 0x1f 54 #define SFC_FTLR_RX_SHIFT 8 55 #define SFC_FTLR_RX_MASK 0x1f 56 57 /* Reset FSM and FIFO */ 58 #define SFC_RCVR 0x10 59 #define SFC_RCVR_RESET BIT(0) 60 61 /* Enhanced mode */ 62 #define SFC_AX 0x14 63 64 /* Address Bit number */ 65 #define SFC_ABIT 0x18 66 67 /* Interrupt status */ 68 #define SFC_ISR 0x1c 69 #define SFC_ISR_RX_FULL_SHIFT BIT(0) 70 #define SFC_ISR_RX_UFLOW_SHIFT BIT(1) 71 #define SFC_ISR_TX_OFLOW_SHIFT BIT(2) 72 #define SFC_ISR_TX_EMPTY_SHIFT BIT(3) 73 #define SFC_ISR_TX_FINISH_SHIFT BIT(4) 74 #define SFC_ISR_BUS_ERR_SHIFT BIT(5) 75 #define SFC_ISR_NSPI_ERR_SHIFT BIT(6) 76 #define SFC_ISR_DMA_SHIFT BIT(7) 77 78 /* FIFO status */ 79 #define SFC_FSR 0x20 80 #define SFC_FSR_TX_IS_FULL BIT(0) 81 #define SFC_FSR_TX_IS_EMPTY BIT(1) 82 #define SFC_FSR_RX_IS_EMPTY BIT(2) 83 #define SFC_FSR_RX_IS_FULL BIT(3) 84 #define SFC_FSR_TXLV_MASK GENMASK(12, 8) 85 #define SFC_FSR_TXLV_SHIFT 8 86 #define SFC_FSR_RXLV_MASK GENMASK(20, 16) 87 #define SFC_FSR_RXLV_SHIFT 16 88 89 /* FSM status */ 90 #define SFC_SR 0x24 91 #define SFC_SR_IS_IDLE 0x0 92 #define SFC_SR_IS_BUSY 0x1 93 94 /* Raw interrupt status */ 95 #define SFC_RISR 0x28 96 #define SFC_RISR_RX_FULL BIT(0) 97 #define SFC_RISR_RX_UNDERFLOW BIT(1) 98 #define SFC_RISR_TX_OVERFLOW BIT(2) 99 #define SFC_RISR_TX_EMPTY BIT(3) 100 #define SFC_RISR_TRAN_FINISH BIT(4) 101 #define SFC_RISR_BUS_ERR BIT(5) 102 #define SFC_RISR_NSPI_ERR BIT(6) 103 #define SFC_RISR_DMA BIT(7) 104 105 /* Version */ 106 #define SFC_VER 0x2C 107 #define SFC_VER_3 0x3 108 #define SFC_VER_4 0x4 109 #define SFC_VER_5 0x5 110 111 /* Delay line controller resiter */ 112 #define SFC_DLL_CTRL0 0x3C 113 #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) 114 #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU 115 #define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU 116 117 /* Master trigger */ 118 #define SFC_DMA_TRIGGER 0x80 119 #define SFC_DMA_TRIGGER_START 1 120 121 /* Src or Dst addr for master */ 122 #define SFC_DMA_ADDR 0x84 123 124 /* Length control register extension 32GB */ 125 #define SFC_LEN_CTRL 0x88 126 #define SFC_LEN_CTRL_TRB_SEL 1 127 #define SFC_LEN_EXT 0x8C 128 129 /* Command */ 130 #define SFC_CMD 0x100 131 #define SFC_CMD_IDX_SHIFT 0 132 #define SFC_CMD_DUMMY_SHIFT 8 133 #define SFC_CMD_DIR_SHIFT 12 134 #define SFC_CMD_DIR_RD 0 135 #define SFC_CMD_DIR_WR 1 136 #define SFC_CMD_ADDR_SHIFT 14 137 #define SFC_CMD_ADDR_0BITS 0 138 #define SFC_CMD_ADDR_24BITS 1 139 #define SFC_CMD_ADDR_32BITS 2 140 #define SFC_CMD_ADDR_XBITS 3 141 #define SFC_CMD_TRAN_BYTES_SHIFT 16 142 #define SFC_CMD_CS_SHIFT 30 143 144 /* Address */ 145 #define SFC_ADDR 0x104 146 147 /* Data */ 148 #define SFC_DATA 0x108 149 150 /* The controller and documentation reports that it supports up to 4 CS 151 * devices (0-3), however I have only been able to test a single CS (CS 0) 152 * due to the configuration of my device. 153 */ 154 #define SFC_MAX_CHIPSELECT_NUM 4 155 156 /* The SFC can transfer max 16KB - 1 at one time 157 * we set it to 15.5KB here for alignment. 158 */ 159 #define SFC_MAX_IOSIZE_VER3 (512 * 31) 160 161 #define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU) 162 163 /* DMA is only enabled for large data transmission */ 164 #define SFC_DMA_TRANS_THRETHOLD (0x40) 165 166 /* Maximum clock values from datasheet suggest keeping clock value under 167 * 150MHz. No minimum or average value is suggested. 168 */ 169 #define SFC_MAX_SPEED (150 * 1000 * 1000) 170 #define SFC_DLL_THRESHOLD_RATE (50 * 1000 * 1000) 171 172 #define SFC_DLL_TRANING_STEP 10 /* Training step */ 173 #define SFC_DLL_TRANING_VALID_WINDOW 80 /* Training Valid DLL winbow */ 174 175 struct rockchip_sfc { 176 struct udevice *dev; 177 void __iomem *regbase; 178 struct clk hclk; 179 struct clk clk; 180 u32 max_freq; 181 u32 speed; 182 bool use_dma; 183 u32 max_iosize; 184 u16 version; 185 186 u32 last_async_size; 187 u32 async; 188 u32 dll_cells; 189 u32 max_dll_cells; 190 }; 191 192 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 193 { 194 int err; 195 u32 status; 196 197 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); 198 199 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, 200 !(status & SFC_RCVR_RESET), 201 1000000); 202 if (err) 203 printf("SFC reset never finished\n"); 204 205 /* Still need to clear the masked interrupt from RISR */ 206 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 207 208 return err; 209 } 210 211 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 212 { 213 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); 214 } 215 216 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) 217 { 218 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 219 return SFC_MAX_IOSIZE_VER4; 220 221 return SFC_MAX_IOSIZE_VER3; 222 } 223 224 static u32 rockchip_sfc_get_max_dll_cells(struct rockchip_sfc *sfc) 225 { 226 switch (rockchip_sfc_get_version(sfc)) { 227 case SFC_VER_5: 228 return SFC_DLL_CTRL0_DLL_MAX_VER5; 229 case SFC_VER_4: 230 return SFC_DLL_CTRL0_DLL_MAX_VER4; 231 default: 232 return 0; 233 } 234 } 235 236 static __maybe_unused void rockchip_sfc_set_delay_lines(struct rockchip_sfc *sfc, u16 cells) 237 { 238 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc); 239 u32 val = 0; 240 241 if (cells > cell_max) 242 cells = cell_max; 243 244 if (cells) 245 val = SFC_DLL_CTRL0_SCLK_SMP_DLL | cells; 246 247 writel(val, sfc->regbase + SFC_DLL_CTRL0); 248 } 249 250 static int rockchip_sfc_init(struct rockchip_sfc *sfc) 251 { 252 writel(0, sfc->regbase + SFC_CTRL); 253 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 254 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); 255 256 return 0; 257 } 258 259 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 260 { 261 struct rockchip_sfc *sfc = dev_get_platdata(bus); 262 263 sfc->regbase = dev_read_addr_ptr(bus); 264 if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma")) 265 sfc->use_dma = false; 266 else 267 sfc->use_dma = true; 268 269 #if CONFIG_IS_ENABLED(CLK) 270 int ret; 271 272 ret = clk_get_by_index(bus, 0, &sfc->clk); 273 if (ret < 0) { 274 printf("Could not get clock for %s: %d\n", bus->name, ret); 275 return ret; 276 } 277 278 ret = clk_get_by_index(bus, 1, &sfc->hclk); 279 if (ret < 0) { 280 printf("Could not get ahb clock for %s: %d\n", bus->name, ret); 281 return ret; 282 } 283 #endif 284 285 return 0; 286 } 287 288 static int rockchip_sfc_probe(struct udevice *bus) 289 { 290 struct rockchip_sfc *sfc = dev_get_platdata(bus); 291 int ret; 292 293 #if CONFIG_IS_ENABLED(CLK) 294 ret = clk_enable(&sfc->hclk); 295 if (ret) 296 dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); 297 298 ret = clk_enable(&sfc->clk); 299 if (ret) 300 dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); 301 #endif 302 303 ret = rockchip_sfc_init(sfc); 304 if (ret) 305 goto err_init; 306 307 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); 308 sfc->version = rockchip_sfc_get_version(sfc); 309 sfc->max_freq = SFC_MAX_SPEED; 310 sfc->dev = bus; 311 312 return 0; 313 314 err_init: 315 #if CONFIG_IS_ENABLED(CLK) 316 clk_disable(&sfc->clk); 317 clk_disable(&sfc->hclk); 318 #endif 319 320 return ret; 321 } 322 323 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 324 { 325 int ret = 0; 326 u32 status; 327 328 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 329 status & SFC_FSR_TXLV_MASK, 330 timeout_us); 331 if (ret) { 332 dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); 333 334 return -ETIMEDOUT; 335 } 336 337 return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; 338 } 339 340 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 341 { 342 int ret = 0; 343 u32 status; 344 345 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 346 status & SFC_FSR_RXLV_MASK, 347 timeout_us); 348 if (ret) { 349 dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); 350 351 return -ETIMEDOUT; 352 } 353 354 return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; 355 } 356 357 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) 358 { 359 if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { 360 /* 361 * SFC not support output DUMMY cycles right after CMD cycles, so 362 * treat it as ADDR cycles. 363 */ 364 op->addr.nbytes = op->dummy.nbytes; 365 op->addr.buswidth = op->dummy.buswidth; 366 op->addr.val = 0xFFFFFFFFF; 367 368 op->dummy.nbytes = 0; 369 } 370 } 371 372 static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout) 373 { 374 unsigned long tbase; 375 376 /* Wait for the DMA interrupt status */ 377 tbase = get_timer(0); 378 while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) { 379 if (get_timer(tbase) > timeout) { 380 printf("dma timeout\n"); 381 rockchip_sfc_reset(sfc); 382 383 return -ETIMEDOUT; 384 } 385 386 udelay(1); 387 } 388 389 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 390 391 return 0; 392 } 393 394 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, 395 struct spi_slave *mem, 396 const struct spi_mem_op *op, 397 u32 len) 398 { 399 struct dm_spi_slave_platdata *plat = dev_get_platdata(sfc->dev); 400 u32 ctrl = 0, cmd = 0; 401 402 /* set CMD */ 403 cmd = op->cmd.opcode; 404 ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); 405 406 /* set ADDR */ 407 if (op->addr.nbytes) { 408 if (op->addr.nbytes == 4) { 409 cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; 410 } else if (op->addr.nbytes == 3) { 411 cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; 412 } else { 413 cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; 414 writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); 415 } 416 417 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); 418 } 419 420 /* set DUMMY */ 421 if (op->dummy.nbytes) { 422 if (op->dummy.buswidth == 4) 423 cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; 424 else if (op->dummy.buswidth == 2) 425 cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; 426 else 427 cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; 428 } 429 430 /* set DATA */ 431 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ 432 writel(len, sfc->regbase + SFC_LEN_EXT); 433 else 434 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; 435 if (len) { 436 if (op->data.dir == SPI_MEM_DATA_OUT) 437 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 438 439 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); 440 } 441 if (!len && op->addr.nbytes) 442 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 443 444 /* set the Controller */ 445 ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; 446 cmd |= plat->cs << SFC_CMD_CS_SHIFT; 447 448 dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", 449 op->addr.nbytes, op->addr.buswidth, 450 op->dummy.nbytes, op->dummy.buswidth); 451 dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", 452 ctrl, cmd, op->addr.val, len); 453 454 writel(ctrl, sfc->regbase + SFC_CTRL); 455 writel(cmd, sfc->regbase + SFC_CMD); 456 if (op->addr.nbytes) 457 writel(op->addr.val, sfc->regbase + SFC_ADDR); 458 459 return 0; 460 } 461 462 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) 463 { 464 u8 bytes = len & 0x3; 465 u32 dwords; 466 int tx_level; 467 u32 write_words; 468 u32 tmp = 0; 469 470 dwords = len >> 2; 471 while (dwords) { 472 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 473 if (tx_level < 0) 474 return tx_level; 475 write_words = min_t(u32, tx_level, dwords); 476 writesl(sfc->regbase + SFC_DATA, buf, write_words); 477 buf += write_words << 2; 478 dwords -= write_words; 479 } 480 481 /* write the rest non word aligned bytes */ 482 if (bytes) { 483 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 484 if (tx_level < 0) 485 return tx_level; 486 memcpy(&tmp, buf, bytes); 487 writel(tmp, sfc->regbase + SFC_DATA); 488 } 489 490 return len; 491 } 492 493 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) 494 { 495 u8 bytes = len & 0x3; 496 u32 dwords; 497 u8 read_words; 498 int rx_level; 499 int tmp; 500 501 /* word aligned access only */ 502 dwords = len >> 2; 503 while (dwords) { 504 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 505 if (rx_level < 0) 506 return rx_level; 507 read_words = min_t(u32, rx_level, dwords); 508 readsl(sfc->regbase + SFC_DATA, buf, read_words); 509 buf += read_words << 2; 510 dwords -= read_words; 511 } 512 513 /* read the rest non word aligned bytes */ 514 if (bytes) { 515 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 516 if (rx_level < 0) 517 return rx_level; 518 tmp = readl(sfc->regbase + SFC_DATA); 519 memcpy(buf, &tmp, bytes); 520 } 521 522 return len; 523 } 524 525 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) 526 { 527 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 528 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); 529 writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); 530 531 return len; 532 } 533 534 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, 535 const struct spi_mem_op *op, u32 len) 536 { 537 dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); 538 539 if (op->data.dir == SPI_MEM_DATA_OUT) 540 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); 541 else 542 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); 543 } 544 545 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, 546 const struct spi_mem_op *op, u32 len) 547 { 548 struct bounce_buffer bb; 549 unsigned int bb_flags; 550 void *dma_buf; 551 int ret; 552 553 dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); 554 555 if (op->data.dir == SPI_MEM_DATA_OUT) { 556 dma_buf = (void *)op->data.buf.out; 557 bb_flags = GEN_BB_READ; 558 } else { 559 dma_buf = (void *)op->data.buf.in; 560 bb_flags = GEN_BB_WRITE; 561 } 562 563 ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags); 564 if (ret) 565 return ret; 566 567 ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len); 568 rockchip_sfc_wait_for_dma_finished(sfc, len * 10); 569 bounce_buffer_stop(&bb); 570 571 return ret; 572 } 573 574 static int rockchip_sfc_xfer_data_dma_async(struct rockchip_sfc *sfc, 575 const struct spi_mem_op *op, u32 len) 576 { 577 void *dma_buf; 578 579 if (op->data.dir == SPI_MEM_DATA_OUT) 580 dma_buf = (void *)op->data.buf.out; 581 else 582 dma_buf = (void *)op->data.buf.in; 583 584 dev_dbg(sfc->dev, "xfer_dma_async len=%x %p\n", len, dma_buf); 585 586 flush_dcache_range((unsigned long)dma_buf, 587 (unsigned long)dma_buf + len); 588 589 rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)dma_buf, len); 590 sfc->last_async_size = len; 591 592 return 0; 593 } 594 595 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) 596 { 597 int ret = 0; 598 u32 status; 599 600 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, 601 !(status & SFC_SR_IS_BUSY), 602 timeout_us); 603 if (ret) { 604 dev_err(sfc->dev, "wait sfc idle timeout\n"); 605 rockchip_sfc_reset(sfc); 606 607 ret = -EIO; 608 } 609 610 return ret; 611 } 612 613 static int rockchip_sfc_exec_op(struct spi_slave *mem, 614 const struct spi_mem_op *op) 615 { 616 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 617 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 618 int ret; 619 620 /* Wait for last async transfer finished */ 621 if (sfc->last_async_size) { 622 rockchip_sfc_wait_for_dma_finished(sfc, sfc->last_async_size); 623 sfc->last_async_size = 0; 624 } 625 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 626 rockchip_sfc_xfer_setup(sfc, mem, op, len); 627 if (len) { 628 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) { 629 if (mem->mode & SPI_DMA_PREPARE) 630 return rockchip_sfc_xfer_data_dma_async(sfc, op, len); 631 ret = rockchip_sfc_xfer_data_dma(sfc, op, len); 632 } else { 633 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 634 } 635 636 if (ret != len) { 637 dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); 638 639 return -EIO; 640 } 641 } 642 643 return rockchip_sfc_xfer_done(sfc, 100000); 644 } 645 646 static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op) 647 { 648 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 649 650 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); 651 652 return 0; 653 } 654 655 #if CONFIG_IS_ENABLED(CLK) 656 static int rockchip_sfc_exec_op_bypass(struct rockchip_sfc *sfc, 657 struct spi_slave *mem, 658 const struct spi_mem_op *op) 659 { 660 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 661 u32 ret; 662 663 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 664 rockchip_sfc_xfer_setup(sfc, mem, op, len); 665 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 666 if (ret != len) { 667 dev_err(sfc->dev, "xfer data failed ret %d\n", ret); 668 669 return -EIO; 670 } 671 672 return rockchip_sfc_xfer_done(sfc, 100000); 673 } 674 675 static void rockchip_sfc_delay_lines_tuning(struct rockchip_sfc *sfc, struct spi_slave *mem) 676 { 677 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1), 678 SPI_MEM_OP_NO_ADDR, 679 SPI_MEM_OP_NO_DUMMY, 680 SPI_MEM_OP_DATA_IN(3, NULL, 1)); 681 u8 id[3], id_temp[3]; 682 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc); 683 u16 right, left = 0; 684 u16 step = SFC_DLL_TRANING_STEP; 685 bool dll_valid = false; 686 687 clk_set_rate(&sfc->clk, SFC_DLL_THRESHOLD_RATE); 688 op.data.buf.in = &id; 689 rockchip_sfc_exec_op_bypass(sfc, mem, &op); 690 if ((0xFF == id[0] && 0xFF == id[1]) || 691 (0x00 == id[0] && 0x00 == id[1])) { 692 dev_dbg(sfc->dev, "no dev, dll by pass\n"); 693 clk_set_rate(&sfc->clk, sfc->speed); 694 695 return; 696 } 697 698 clk_set_rate(&sfc->clk, sfc->speed); 699 op.data.buf.in = &id_temp; 700 for (right = 0; right <= cell_max; right += step) { 701 int ret; 702 703 rockchip_sfc_set_delay_lines(sfc, right); 704 rockchip_sfc_exec_op_bypass(sfc, mem, &op); 705 dev_dbg(sfc->dev, "dll read flash id:%x %x %x\n", 706 id_temp[0], id_temp[1], id_temp[2]); 707 708 ret = memcmp(&id, &id_temp, 3); 709 if (dll_valid && ret) { 710 right -= step; 711 712 break; 713 } 714 if (!dll_valid && !ret) 715 left = right; 716 717 if (!ret) 718 dll_valid = true; 719 720 /* Add cell_max to loop */ 721 if (right == cell_max) 722 break; 723 if (right + step > cell_max) 724 right = cell_max - step; 725 } 726 727 if (dll_valid && (right - left) >= SFC_DLL_TRANING_VALID_WINDOW) { 728 if (left == 0 && right < cell_max) 729 sfc->dll_cells = left + (right - left) * 2 / 5; 730 else 731 sfc->dll_cells = left + (right - left) / 2; 732 } else { 733 sfc->dll_cells = 0; 734 } 735 736 if (sfc->dll_cells) { 737 dev_dbg(sfc->dev, "%d %d %d dll training success in %dMHz max_cells=%u sfc_ver=%d\n", 738 left, right, sfc->dll_cells, sfc->speed, 739 rockchip_sfc_get_max_dll_cells(sfc), rockchip_sfc_get_version(sfc)); 740 rockchip_sfc_set_delay_lines(sfc, (u16)sfc->dll_cells); 741 } else { 742 dev_err(sfc->dev, "%d %d dll training failed in %dMHz, reduce the speed\n", 743 left, right, sfc->speed); 744 rockchip_sfc_set_delay_lines(sfc, 0); 745 clk_set_rate(&sfc->clk, SFC_DLL_THRESHOLD_RATE); 746 sfc->speed = clk_get_rate(&sfc->clk); 747 } 748 } 749 750 #endif 751 752 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 753 { 754 struct rockchip_sfc *sfc = dev_get_platdata(bus); 755 756 if (speed > sfc->max_freq) 757 speed = sfc->max_freq; 758 759 if (speed == sfc->speed) 760 return 0; 761 762 #if CONFIG_IS_ENABLED(CLK) 763 int ret = clk_set_rate(&sfc->clk, speed); 764 765 if (ret < 0) { 766 dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", 767 speed); 768 return ret; 769 } 770 sfc->speed = speed; 771 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) { 772 if (clk_get_rate(&sfc->clk) > SFC_DLL_THRESHOLD_RATE) 773 rockchip_sfc_delay_lines_tuning(sfc, NULL); 774 else 775 rockchip_sfc_set_delay_lines(sfc, 0); 776 } 777 778 dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n", 779 sfc->speed, clk_get_rate(&sfc->clk)); 780 #else 781 dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); 782 #endif 783 return 0; 784 } 785 786 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 787 { 788 return 0; 789 } 790 791 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { 792 .adjust_op_size = rockchip_sfc_adjust_op_size, 793 .exec_op = rockchip_sfc_exec_op, 794 }; 795 796 static const struct dm_spi_ops rockchip_sfc_ops = { 797 .mem_ops = &rockchip_sfc_mem_ops, 798 .set_speed = rockchip_sfc_set_speed, 799 .set_mode = rockchip_sfc_set_mode, 800 }; 801 802 static const struct udevice_id rockchip_sfc_ids[] = { 803 { .compatible = "rockchip,sfc"}, 804 {}, 805 }; 806 807 U_BOOT_DRIVER(rockchip_sfc_driver) = { 808 .name = "rockchip_sfc", 809 .id = UCLASS_SPI, 810 .of_match = rockchip_sfc_ids, 811 .ops = &rockchip_sfc_ops, 812 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 813 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc), 814 .probe = rockchip_sfc_probe, 815 }; 816