1 /* 2 * SFC driver for rockchip 3 * 4 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 5 * Yifeng.zhao, Software Engineering, <zhao0116@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <bouncebuf.h> 12 #include <clk.h> 13 #include <dm.h> 14 #include <dt-structs.h> 15 #include <errno.h> 16 #include <spi.h> 17 #include <linux/errno.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/periph.h> 21 #include <dm/pinctrl.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #ifdef SFC_DEBUG 26 #define SFC_DBG printf 27 #else 28 #define SFC_DBG(args...) 29 #endif 30 31 struct rockchip_sfc_reg { 32 u32 ctrl; 33 u32 imr; 34 u32 iclr; 35 u32 ftlr; 36 u32 rcvr; 37 u32 ax; 38 u32 abit; 39 u32 isr; 40 u32 fsr; 41 u32 sr; 42 u32 risr; 43 u32 reserved[21]; 44 u32 dmatr; 45 u32 dmaaddr; 46 u32 reserved1[30]; 47 u32 cmd; 48 u32 addr; 49 u32 data; 50 }; 51 52 check_member(rockchip_sfc_reg, data, 0x108); 53 54 /*SFC_CTRL*/ 55 #define SFC_DATA_WIDTH_SHIFT 12 56 #define SFC_DATA_WIDTH_MASK GENMASK(13, 12) 57 #define SFC_ADDR_WIDTH_SHIFT 10 58 #define SFC_ADDR_WIDTH_MASK GENMASK(11, 10) 59 #define SFC_CMD_WIDTH_SHIFT 8 60 #define SFC_CMD_WIDTH_MASK GENMASK(9, 8) 61 #define SFC_DATA_SHIFT_NEGETIVE BIT(1) 62 63 /*SFC_CMD*/ 64 #define SFC_DUMMY_BITS_SHIFT 8 65 #define SFC_RW_SHIFT 12 66 #define SFC_WR 1 67 #define SFC_RD 0 68 #define SFC_ADDR_BITS_SHIFT 14 69 #define SFC_ADDR_BITS_MASK GENMASK(15, 14) 70 #define SFC_ADDR_0BITS 0 71 #define SFC_ADDR_24BITS 1 72 #define SFC_ADDR_32BITS 2 73 #define SFC_ADDR_XBITS 3 74 #define SFC_TRB_SHIFT (16) 75 #define SFC_TRB_MASK GENMASK(29, 16) 76 77 /* Dma start trigger signal. Auto cleared after write */ 78 #define SFC_DMA_START BIT(0) 79 80 #define SFC_RESET BIT(0) 81 82 /*SFC_FSR*/ 83 #define SFC_RXLV_SHIFT (16) 84 #define SFC_RXLV_MASK GENMASK(20, 16) 85 #define SFC_TXLV_SHIFT (8) 86 #define SFC_TXLV_MASK GENMASK(12, 8) 87 #define SFC_RX_FULL BIT(3) /* rx fifo full */ 88 #define SFC_RX_EMPTY BIT(2) /* rx fifo empty */ 89 #define SFC_TX_EMPTY BIT(1) /* tx fifo empty */ 90 #define SFC_TX_FULL BIT(0) /* tx fifo full */ 91 92 #define SFC_BUSY BIT(0) /* sfc busy flag */ 93 94 /*SFC_RISR*/ 95 #define DMA_FINISH_INT BIT(7) /* dma interrupt */ 96 #define SPI_ERR_INT BIT(6) /* Nspi error interrupt */ 97 #define AHB_ERR_INT BIT(5) /* Ahb bus error interrupt */ 98 #define TRANS_FINISH_INT BIT(4) /* Transfer finish interrupt */ 99 #define TX_EMPTY_INT BIT(3) /* Tx fifo empty interrupt */ 100 #define TX_OF_INT BIT(2) /* Tx fifo overflow interrupt */ 101 #define RX_UF_INT BIT(1) /* Rx fifo underflow interrupt */ 102 #define RX_FULL_INT BIT(0) /* Rx fifo full interrupt */ 103 104 #define SFC_MAX_TRB (512 * 31) 105 106 #define SFC_MAX_RATE (150 * 1000 * 1000) 107 #define SFC_DEFAULT_RATE (80 * 1000 * 1000) 108 #define SFC_MIN_RATE (10 * 1000 * 1000) 109 110 enum rockchip_sfc_if_type { 111 IF_TYPE_STD, 112 IF_TYPE_DUAL, 113 IF_TYPE_QUAD, 114 }; 115 116 struct rockchip_sfc_platdata { 117 s32 frequency; 118 void *base; 119 }; 120 121 struct rockchip_sfc { 122 struct rockchip_sfc_reg *regbase; 123 struct clk clk; 124 unsigned int max_freq; 125 unsigned int mode; 126 unsigned int speed_hz; 127 u32 cmd; 128 u32 addr; 129 u8 addr_bits; 130 u8 addr_xbits_ext; 131 u8 dummy_bits; 132 u8 rw; 133 u32 trb; 134 }; 135 136 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 137 { 138 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 139 struct rockchip_sfc *sfc = dev_get_priv(bus); 140 ofnode subnode; 141 int ret; 142 143 plat->base = dev_read_addr_ptr(bus); 144 ret = clk_get_by_index(bus, 0, &sfc->clk); 145 if (ret < 0) { 146 printf("Could not get clock for %s: %d\n", bus->name, ret); 147 return ret; 148 } 149 150 subnode = dev_read_first_subnode(bus); 151 if (!ofnode_valid(subnode)) { 152 printf("Error: subnode with SPI flash config missing!\n"); 153 return -ENODEV; 154 } 155 156 plat->frequency = ofnode_read_u32_default(subnode, "spi-max-frequency", 157 100000000); 158 if (plat->frequency > SFC_MAX_RATE || plat->frequency < SFC_MIN_RATE) 159 plat->frequency = SFC_DEFAULT_RATE; 160 sfc->max_freq = plat->frequency; 161 162 return 0; 163 } 164 165 static int rockchip_sfc_probe(struct udevice *bus) 166 { 167 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 168 struct rockchip_sfc *sfc = dev_get_priv(bus); 169 struct dm_spi_bus *dm_spi_bus; 170 171 dm_spi_bus = bus->uclass_priv; 172 dm_spi_bus->max_hz = plat->frequency; 173 sfc->regbase = (struct rockchip_sfc_reg *)plat->base; 174 175 return 0; 176 } 177 178 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 179 { 180 struct rockchip_sfc_reg *regs = sfc->regbase; 181 int tbase = get_timer(0); 182 u32 rcvr; 183 int ret = 0; 184 185 writel(SFC_RESET, ®s->rcvr); 186 do { 187 rcvr = readl(®s->rcvr); 188 if (get_timer(tbase) > 1000) { 189 debug("sfc reset timeout\n"); 190 ret = -ETIMEDOUT; 191 break; 192 } 193 udelay(1); 194 } while (rcvr); 195 196 writel(0xFFFFFFFF, ®s->iclr); 197 198 debug("sfc reset\n"); 199 200 return ret; 201 } 202 203 /* The SFC_CTRL register is a global control register, 204 * when the controller is in busy state(SFC_SR), 205 * SFC_CTRL cannot be set. 206 */ 207 static int rockchip_sfc_wait_idle(struct rockchip_sfc *sfc, 208 u32 timeout_ms) 209 { 210 struct rockchip_sfc_reg *regs = sfc->regbase; 211 unsigned long tbase = get_timer(0); 212 u32 sr, fsr; 213 214 while (1) { 215 sr = readl(®s->sr); 216 fsr = readl(®s->fsr); 217 if ((fsr & SFC_TX_EMPTY) && 218 (fsr & SFC_RX_EMPTY) && 219 !(sr & SFC_BUSY)) 220 break; 221 if (get_timer(tbase) > timeout_ms) { 222 printf("waite sfc idle timeout(sr:0x%08x fsr:0x%08x)\n", 223 sr, fsr); 224 rockchip_sfc_reset(sfc); 225 return -ETIMEDOUT; 226 } 227 udelay(100); 228 } 229 230 return 0; 231 } 232 233 static u8 rockchip_sfc_get_if_type(struct rockchip_sfc *sfc) 234 { 235 int type = IF_TYPE_STD; 236 237 if (sfc->rw == SFC_WR) { 238 if (sfc->mode & SPI_TX_QUAD) 239 type = IF_TYPE_QUAD; 240 else if (sfc->mode & SPI_TX_DUAL) 241 type = IF_TYPE_DUAL; 242 else 243 type = IF_TYPE_STD; 244 } else { 245 if (sfc->mode & SPI_RX_QUAD) 246 type = IF_TYPE_QUAD; 247 else if (sfc->mode & SPI_RX_DUAL) 248 type = IF_TYPE_DUAL; 249 else 250 type = IF_TYPE_STD; 251 } 252 253 return type; 254 } 255 256 static void rockchip_sfc_setup_xfer(struct rockchip_sfc *sfc, u32 trb) 257 { 258 struct rockchip_sfc_reg *regs = sfc->regbase; 259 u32 val = 0x02; 260 u8 data_width = IF_TYPE_STD; 261 262 SFC_DBG("--- sfc.addr_bit %x\n", sfc->addr_bits); 263 264 if (sfc->addr_bits == SFC_ADDR_24BITS || 265 sfc->addr_bits == SFC_ADDR_32BITS) 266 data_width = rockchip_sfc_get_if_type(sfc); 267 268 if (sfc->addr_bits == SFC_ADDR_XBITS) 269 writel(sfc->addr_xbits_ext - 1, ®s->abit); 270 271 val |= (data_width << SFC_DATA_WIDTH_SHIFT); 272 273 rockchip_sfc_wait_idle(sfc, 10); 274 275 SFC_DBG("--- sfc.ctrl %x\n", val); 276 writel(val, ®s->ctrl); 277 278 val = sfc->cmd; 279 val |= trb << SFC_TRB_SHIFT; 280 val |= sfc->rw << SFC_RW_SHIFT; 281 val |= sfc->addr_bits << SFC_ADDR_BITS_SHIFT; 282 val |= sfc->dummy_bits << SFC_DUMMY_BITS_SHIFT; 283 284 SFC_DBG("--- sfc.cmd %x\n", val); 285 writel(val, ®s->cmd); 286 287 if (sfc->addr_bits & SFC_ADDR_XBITS) { 288 SFC_DBG("--- sfc.addr %x\n", sfc->addr); 289 writel(sfc->addr, ®s->addr); 290 } 291 } 292 293 static int rockchip_sfc_dma_xfer(struct rockchip_sfc *sfc, void *buffer, size_t trb) 294 { 295 struct rockchip_sfc_reg *regs = sfc->regbase; 296 struct bounce_buffer bb; 297 unsigned int bb_flags; 298 int timeout = 1000; 299 int ret = 0; 300 int risr; 301 unsigned long tbase; 302 303 if (sfc->rw == SFC_WR) 304 bb_flags = GEN_BB_READ; 305 else 306 bb_flags = GEN_BB_WRITE; 307 308 ret = bounce_buffer_start(&bb, buffer, trb, bb_flags); 309 if (ret) 310 return ret; 311 312 rockchip_sfc_setup_xfer(sfc, bb.len_aligned); 313 314 writel(0xFFFFFFFF, ®s->iclr); 315 writel((unsigned long)bb.bounce_buffer, ®s->dmaaddr); 316 writel(SFC_DMA_START, ®s->dmatr); 317 318 tbase = get_timer(0); 319 do { 320 udelay(1); 321 risr = readl(®s->risr); 322 if (get_timer(tbase) > timeout) { 323 debug("dma timeout\n"); 324 ret = -ETIMEDOUT; 325 break; 326 } 327 } while (!(risr & TRANS_FINISH_INT)); 328 329 writel(0xFFFFFFFF, ®s->iclr); 330 331 bounce_buffer_stop(&bb); 332 333 return ret; 334 } 335 336 static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int rw, 337 u32 timeout) 338 { 339 struct rockchip_sfc_reg *regs = sfc->regbase; 340 unsigned long tbase = get_timer(0); 341 u8 level; 342 u32 fsr; 343 344 do { 345 fsr = readl(®s->fsr); 346 if (rw == SFC_WR) 347 level = (fsr & SFC_TXLV_MASK) >> SFC_TXLV_SHIFT; 348 else 349 level = (fsr & SFC_RXLV_MASK) >> SFC_RXLV_SHIFT; 350 if (get_timer(tbase) > timeout) 351 return -ETIMEDOUT; 352 udelay(1); 353 } while (!level); 354 355 return level; 356 } 357 358 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 359 { 360 struct rockchip_sfc_reg *regs = sfc->regbase; 361 u32 bytes = len & 0x3; 362 u32 words = len >> 2; 363 int tx_level = 0; 364 u32 val = 0; 365 u8 count; 366 367 while (words) { 368 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 369 if (tx_level <= 0) 370 return tx_level; 371 count = min(words, (u32)tx_level); 372 writesl(®s->data, buf, count); 373 buf += count; 374 words -= count; 375 } 376 377 /* handle the last non 4byte aligned bytes */ 378 if (bytes) { 379 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 380 if (tx_level <= 0) 381 return tx_level; 382 memcpy(&val, buf, bytes); 383 writel(val, ®s->data); 384 } 385 386 return 0; 387 } 388 389 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 390 { 391 struct rockchip_sfc_reg *regs = sfc->regbase; 392 u32 bytes = len & 0x3; 393 u32 words = len >> 2; 394 int rx_level = 0; 395 u32 count; 396 u32 val; 397 398 while (words) { 399 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 400 if (rx_level <= 0) 401 return rx_level; 402 count = min(words, (u32)rx_level); 403 readsl(®s->data, buf, count); 404 buf += count; 405 words -= count; 406 } 407 408 /* handle the last non 4 bytes aligned bytes */ 409 if (bytes) { 410 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 411 if (rx_level <= 0) 412 return rx_level; 413 val = readl(®s->data); 414 memcpy(buf, &val, bytes); 415 } 416 417 return 0; 418 } 419 420 static int rockchip_sfc_pio_xfer(struct rockchip_sfc *sfc, void *buf, u32 len) 421 { 422 int ret = 0; 423 424 rockchip_sfc_setup_xfer(sfc, len); 425 426 if (len) { 427 if (sfc->rw == SFC_WR) 428 ret = rockchip_sfc_write_fifo(sfc, (u32 *)buf, len); 429 else 430 ret = rockchip_sfc_read_fifo(sfc, (u32 *)buf, len); 431 } 432 433 return ret; 434 } 435 436 static int rockchip_sfc_read(struct rockchip_sfc *sfc, u32 offset, 437 void *buf, size_t len) 438 { 439 u32 dma_trans; 440 u32 trb; 441 u8 bytes; 442 int ret; 443 444 if (len >= ARCH_DMA_MINALIGN) { 445 bytes = len & (ARCH_DMA_MINALIGN - 1); 446 dma_trans = len - bytes; 447 } else { 448 dma_trans = 0; 449 bytes = len; 450 } 451 452 while (dma_trans) { 453 trb = min_t(size_t, dma_trans, SFC_MAX_TRB); 454 ret = rockchip_sfc_dma_xfer(sfc, buf, trb); 455 if (ret < 0) 456 return ret; 457 dma_trans -= trb; 458 sfc->addr += trb; 459 buf += trb; 460 } 461 462 /* 463 * transfer the last non dma anligned byte by pio mode 464 */ 465 if (bytes) 466 ret = rockchip_sfc_pio_xfer(sfc, buf, bytes); 467 468 return 0; 469 } 470 471 static int rockchip_sfc_write(struct rockchip_sfc *sfc, u32 offset, 472 void *buf, size_t len) 473 { 474 if (len > SFC_MAX_TRB) { 475 printf("out of the max sfc trb"); 476 return -EINVAL; 477 } 478 479 if (len && !(len & (ARCH_DMA_MINALIGN - 1))) 480 return rockchip_sfc_dma_xfer(sfc, buf, len); 481 else 482 return rockchip_sfc_pio_xfer(sfc, buf, len); 483 484 return 0; 485 } 486 487 static int rockchip_sfc_do_xfer(struct rockchip_sfc *sfc, void *buf, size_t len) 488 { 489 if (sfc->rw) 490 return rockchip_sfc_write(sfc, sfc->addr, buf, len); 491 else 492 return rockchip_sfc_read(sfc, sfc->addr, buf, len); 493 } 494 495 static int rockchip_sfc_xfer(struct udevice *dev, unsigned int bitlen, 496 const void *dout, void *din, unsigned long flags) 497 { 498 struct udevice *bus = dev->parent; 499 struct rockchip_sfc *sfc = dev_get_priv(bus); 500 int len = bitlen >> 3; 501 u8 *pcmd = (u8 *)dout; 502 void *data_buf; 503 int ret = 0; 504 505 if (flags & SPI_XFER_BEGIN) { 506 sfc->cmd = pcmd[0]; 507 switch (len) { 508 case 6: /* Nor >16MB 0x6b dummy op */ 509 sfc->addr_bits = SFC_ADDR_32BITS; 510 sfc->dummy_bits = 8; 511 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 512 break; 513 case 5: /* Nor <=16MB 0x6b dummy op, Nor >16MB no dummy op */ 514 if (sfc->cmd == 0x6b) { 515 sfc->addr_bits = SFC_ADDR_24BITS; 516 sfc->dummy_bits = 8; 517 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 518 } else { 519 sfc->addr_bits = SFC_ADDR_32BITS; 520 sfc->dummy_bits = 0; 521 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 522 } 523 break; 524 case 4: /* Nand erase and read, Nor <=16MB no dummy op */ 525 sfc->addr_bits = SFC_ADDR_24BITS; 526 sfc->dummy_bits = 0; 527 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 528 break; 529 case 3: /* Nand prog, */ 530 sfc->addr_bits = SFC_ADDR_XBITS; 531 sfc->addr_xbits_ext = 16; 532 sfc->dummy_bits = 0; 533 sfc->addr = pcmd[2] | pcmd[1] << 8; 534 break; 535 case 2: /* Nand read/write feature */ 536 sfc->addr_bits = SFC_ADDR_XBITS; 537 sfc->addr_xbits_ext = 8; 538 sfc->dummy_bits = 0; 539 sfc->addr = pcmd[1]; 540 break; 541 default: /* Nand/Nor Read/Write status */ 542 sfc->addr_bits = SFC_ADDR_0BITS; 543 sfc->dummy_bits = 0; 544 sfc->addr = 0; 545 break; 546 } 547 SFC_DBG("%s %d %x %d %d %x\n", __func__, len, sfc->cmd, sfc->addr_bits, 548 sfc->dummy_bits, sfc->addr); 549 } 550 if (flags & SPI_XFER_END) { 551 if (din) { 552 sfc->rw = SFC_RD; 553 data_buf = din; 554 } else { 555 sfc->rw = SFC_WR; 556 data_buf = (void *)dout; 557 } 558 559 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 560 len = 0; 561 data_buf = NULL; 562 } 563 564 if (sfc->cmd == 0x9f && len == 4) { 565 /* SPI Nand read id */ 566 sfc->addr_bits = SFC_ADDR_XBITS; 567 sfc->addr_xbits_ext = 8; 568 sfc->dummy_bits = 0; 569 sfc->addr = 0; 570 ((u8 *)data_buf)[0] = 0xff; 571 ret = rockchip_sfc_do_xfer(sfc, &((u8 *)data_buf)[1], 3); 572 } else { 573 ret = rockchip_sfc_do_xfer(sfc, data_buf, len); 574 } 575 } 576 577 return ret; 578 } 579 580 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 581 { 582 struct rockchip_sfc *sfc = dev_get_priv(bus); 583 584 if (speed > sfc->max_freq) 585 speed = sfc->max_freq; 586 587 sfc->speed_hz = speed; 588 clk_set_rate(&sfc->clk, sfc->speed_hz); 589 SFC_DBG("%s clk= %ld\n", __func__, clk_get_rate(&sfc->clk)); 590 591 return 0; 592 } 593 594 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 595 { 596 struct rockchip_sfc *sfc = dev_get_priv(bus); 597 598 sfc->mode = mode; 599 600 return 0; 601 } 602 603 static const struct dm_spi_ops rockchip_sfc_ops = { 604 .xfer = rockchip_sfc_xfer, 605 .set_speed = rockchip_sfc_set_speed, 606 .set_mode = rockchip_sfc_set_mode, 607 }; 608 609 static const struct udevice_id rockchip_sfc_ids[] = { 610 { .compatible = "rockchip,sfc" }, 611 { } 612 }; 613 614 U_BOOT_DRIVER(rockchip_sfc_driver) = { 615 .name = "rockchip_sfc", 616 .id = UCLASS_SPI, 617 .of_match = rockchip_sfc_ids, 618 .ops = &rockchip_sfc_ops, 619 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 620 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc_platdata), 621 .priv_auto_alloc_size = sizeof(struct rockchip_sfc), 622 .probe = rockchip_sfc_probe, 623 }; 624