1 /* 2 * SFC driver for rockchip 3 * 4 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 5 * Yifeng.zhao, Software Engineering, <zhao0116@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <bouncebuf.h> 12 #include <clk.h> 13 #include <dm.h> 14 #include <dt-structs.h> 15 #include <errno.h> 16 #include <spi.h> 17 #include <linux/errno.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/periph.h> 21 #include <dm/pinctrl.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #ifdef SFC_DEBUG 26 #define SFC_DBG printf 27 #else 28 #define SFC_DBG(args...) 29 #endif 30 31 struct rockchip_sfc_reg { 32 u32 ctrl; 33 u32 imr; 34 u32 iclr; 35 u32 ftlr; 36 u32 rcvr; 37 u32 ax; 38 u32 abit; 39 u32 isr; 40 u32 fsr; 41 u32 sr; 42 u32 risr; 43 u32 ver; 44 u32 qop; 45 u32 ext_ctrl; 46 u32 reserved; 47 u32 dll_ctrl0; 48 u32 reserved1[16]; 49 u32 dmatr; 50 u32 dmaaddr; 51 u32 len_ctrl; 52 u32 len_ext; 53 u32 reserved2[28]; 54 u32 cmd; 55 u32 addr; 56 u32 data; 57 }; 58 59 check_member(rockchip_sfc_reg, data, 0x108); 60 61 /*SFC_CTRL*/ 62 #define SFC_DATA_WIDTH_SHIFT 12 63 #define SFC_DATA_WIDTH_MASK GENMASK(13, 12) 64 #define SFC_ADDR_WIDTH_SHIFT 10 65 #define SFC_ADDR_WIDTH_MASK GENMASK(11, 10) 66 #define SFC_CMD_WIDTH_SHIFT 8 67 #define SFC_CMD_WIDTH_MASK GENMASK(9, 8) 68 #define SFC_DATA_SHIFT_NEGETIVE BIT(1) 69 70 /*SFC_CMD*/ 71 #define SFC_DUMMY_BITS_SHIFT 8 72 #define SFC_RW_SHIFT 12 73 #define SFC_WR 1 74 #define SFC_RD 0 75 #define SFC_ADDR_BITS_SHIFT 14 76 #define SFC_ADDR_BITS_MASK GENMASK(15, 14) 77 #define SFC_ADDR_0BITS 0 78 #define SFC_ADDR_24BITS 1 79 #define SFC_ADDR_32BITS 2 80 #define SFC_ADDR_XBITS 3 81 #define SFC_TRB_SHIFT (16) 82 #define SFC_TRB_MASK GENMASK(29, 16) 83 84 /* Dma start trigger signal. Auto cleared after write */ 85 #define SFC_DMA_START BIT(0) 86 87 #define SFC_RESET BIT(0) 88 89 /*SFC_FSR*/ 90 #define SFC_RXLV_SHIFT (16) 91 #define SFC_RXLV_MASK GENMASK(20, 16) 92 #define SFC_TXLV_SHIFT (8) 93 #define SFC_TXLV_MASK GENMASK(12, 8) 94 #define SFC_RX_FULL BIT(3) /* rx fifo full */ 95 #define SFC_RX_EMPTY BIT(2) /* rx fifo empty */ 96 #define SFC_TX_EMPTY BIT(1) /* tx fifo empty */ 97 #define SFC_TX_FULL BIT(0) /* tx fifo full */ 98 99 #define SFC_BUSY BIT(0) /* sfc busy flag */ 100 101 /*SFC_RISR*/ 102 #define DMA_FINISH_INT BIT(7) /* dma interrupt */ 103 #define SPI_ERR_INT BIT(6) /* Nspi error interrupt */ 104 #define AHB_ERR_INT BIT(5) /* Ahb bus error interrupt */ 105 #define TRANS_FINISH_INT BIT(4) /* Transfer finish interrupt */ 106 #define TX_EMPTY_INT BIT(3) /* Tx fifo empty interrupt */ 107 #define TX_OF_INT BIT(2) /* Tx fifo overflow interrupt */ 108 #define RX_UF_INT BIT(1) /* Rx fifo underflow interrupt */ 109 #define RX_FULL_INT BIT(0) /* Rx fifo full interrupt */ 110 111 /*SFC_DLL_CTRL0*/ 112 #define DLL_CTRL0_SCLK_SMP_DLL BIT(15) /* SCLK sampling enable dll */ 113 #define DLL_CTRL0_DLL_MAX_VER4 0x1FFU 114 #define DLL_CTRL0_DLL_MAX_VER5 0xFFU 115 116 #define SFC_MAX_TRB_VER3 (512 * 31) 117 #define SFC_MAX_TRB_VER4 (0xFFFFFFFF) 118 119 #define SFC_MAX_RATE (150 * 1000 * 1000) 120 #define SFC_DLL_THRESHOLD_RATE (50 * 1000 * 1000) 121 #define SFC_DEFAULT_RATE (80 * 1000 * 1000) 122 123 #define SFC_VER_3 0x3 124 #define SFC_VER_4 0x4 125 #define SFC_VER_5 0x5 126 127 #define SFC_DLL_TRANING_STEP 10 /* Training step */ 128 #define SFC_DLL_TRANING_VALID_WINDOW 80 /* Training Valid DLL winbow */ 129 130 enum rockchip_sfc_if_type { 131 IF_TYPE_STD, 132 IF_TYPE_DUAL, 133 IF_TYPE_QUAD, 134 }; 135 136 struct rockchip_sfc_platdata { 137 s32 frequency; 138 void *base; 139 }; 140 141 struct rockchip_sfc { 142 struct rockchip_sfc_reg *regbase; 143 struct clk clk; 144 unsigned int max_freq; 145 unsigned int mode; 146 unsigned int speed_hz; 147 u32 max_iosize; 148 u16 max_dll_cells; 149 u16 dll_cells; 150 bool prepare; 151 u32 last_prepare_size; 152 u32 cmd; 153 u32 addr; 154 u8 addr_bits; 155 u8 addr_xbits_ext; 156 u8 dummy_bits; 157 u8 rw; 158 u32 trb; 159 }; 160 161 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 162 { 163 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 164 165 plat->base = dev_read_addr_ptr(bus); 166 #if CONFIG_IS_ENABLED(CLK) 167 struct rockchip_sfc *sfc = dev_get_priv(bus); 168 int ret; 169 170 ret = clk_get_by_index(bus, 0, &sfc->clk); 171 if (ret < 0) { 172 printf("Could not get clock for %s: %d\n", bus->name, ret); 173 return ret; 174 } 175 #endif 176 177 return 0; 178 } 179 180 u32 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 181 { 182 struct rockchip_sfc_reg *regs = sfc->regbase; 183 184 return (u32)(readl(®s->ver) & 0xFFFF); 185 } 186 187 int rockchip_sfc_set_delay_lines(struct rockchip_sfc *sfc, u32 cells) 188 { 189 struct rockchip_sfc_reg *regs = sfc->regbase; 190 u32 val = 0; 191 192 if (cells > sfc->max_dll_cells) 193 cells = sfc->max_dll_cells; 194 195 if (cells) 196 val = DLL_CTRL0_SCLK_SMP_DLL | cells; 197 198 return writel(val, ®s->dll_ctrl0); 199 } 200 201 #if CONFIG_IS_ENABLED(CLK) 202 static void rockchip_sfc_delay_lines_training(struct udevice *bus, struct rockchip_sfc *sfc); 203 #endif 204 205 static int rockchip_sfc_probe(struct udevice *bus) 206 { 207 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 208 struct rockchip_sfc *sfc = dev_get_priv(bus); 209 struct rockchip_sfc_reg *regs; 210 211 sfc->regbase = (struct rockchip_sfc_reg *)plat->base; 212 sfc->max_freq = SFC_MAX_RATE; 213 regs = sfc->regbase; 214 switch (rockchip_sfc_get_version(sfc)) { 215 case SFC_VER_5: 216 sfc->max_dll_cells = DLL_CTRL0_DLL_MAX_VER5; 217 sfc->max_iosize = SFC_MAX_TRB_VER4; 218 writel(1, ®s->len_ctrl); 219 break; 220 case SFC_VER_4: 221 sfc->max_dll_cells = DLL_CTRL0_DLL_MAX_VER4; 222 sfc->max_iosize = SFC_MAX_TRB_VER4; 223 writel(1, ®s->len_ctrl); 224 break; 225 default: 226 sfc->max_dll_cells = 0; 227 sfc->max_iosize = SFC_MAX_TRB_VER3; 228 break; 229 } 230 231 return 0; 232 } 233 234 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 235 { 236 struct rockchip_sfc_reg *regs = sfc->regbase; 237 int tbase = get_timer(0); 238 u32 rcvr; 239 int ret = 0; 240 241 writel(SFC_RESET, ®s->rcvr); 242 do { 243 rcvr = readl(®s->rcvr); 244 if (get_timer(tbase) > 1000) { 245 debug("sfc reset timeout\n"); 246 ret = -ETIMEDOUT; 247 break; 248 } 249 udelay(1); 250 } while (rcvr); 251 252 writel(0xFFFFFFFF, ®s->iclr); 253 254 debug("sfc reset\n"); 255 256 return ret; 257 } 258 259 static int rockchip_sfc_dma_xfer_wait_finished(struct rockchip_sfc *sfc) 260 { 261 struct rockchip_sfc_reg *regs = sfc->regbase; 262 int timeout = sfc->last_prepare_size * 10; 263 unsigned long tbase; 264 int ret = 0; 265 int risr; 266 267 tbase = get_timer(0); 268 do { 269 udelay(1); 270 risr = readl(®s->risr); 271 if (get_timer(tbase) > timeout) { 272 debug("dma timeout\n"); 273 ret = -ETIMEDOUT; 274 break; 275 } 276 } while (!(risr & TRANS_FINISH_INT)); 277 sfc->last_prepare_size = 0; 278 279 return ret; 280 } 281 282 /* The SFC_CTRL register is a global control register, 283 * when the controller is in busy state(SFC_SR), 284 * SFC_CTRL cannot be set. 285 */ 286 static int rockchip_sfc_wait_idle(struct rockchip_sfc *sfc, 287 u32 timeout_ms) 288 { 289 struct rockchip_sfc_reg *regs = sfc->regbase; 290 unsigned long tbase = get_timer(0); 291 u32 sr, fsr; 292 293 if (sfc->last_prepare_size && rockchip_sfc_dma_xfer_wait_finished(sfc)) 294 return -ETIMEDOUT; 295 296 while (1) { 297 sr = readl(®s->sr); 298 fsr = readl(®s->fsr); 299 if ((fsr & SFC_TX_EMPTY) && 300 (fsr & SFC_RX_EMPTY) && 301 !(sr & SFC_BUSY)) 302 break; 303 if (get_timer(tbase) > timeout_ms) { 304 printf("waite sfc idle timeout(sr:0x%08x fsr:0x%08x)\n", 305 sr, fsr); 306 rockchip_sfc_reset(sfc); 307 return -ETIMEDOUT; 308 } 309 udelay(100); 310 } 311 312 return 0; 313 } 314 315 static u8 rockchip_sfc_get_if_type(struct rockchip_sfc *sfc) 316 { 317 int type = IF_TYPE_STD; 318 319 if (sfc->rw == SFC_WR) { 320 if (sfc->mode & SPI_TX_QUAD) 321 type = IF_TYPE_QUAD; 322 else if (sfc->mode & SPI_TX_DUAL) 323 type = IF_TYPE_DUAL; 324 else 325 type = IF_TYPE_STD; 326 } else { 327 if (sfc->mode & SPI_RX_QUAD) 328 type = IF_TYPE_QUAD; 329 else if (sfc->mode & SPI_RX_DUAL) 330 type = IF_TYPE_DUAL; 331 else 332 type = IF_TYPE_STD; 333 } 334 335 return type; 336 } 337 338 static void rockchip_sfc_setup_xfer(struct rockchip_sfc *sfc, u32 trb) 339 { 340 struct rockchip_sfc_reg *regs = sfc->regbase; 341 u32 val; 342 u8 data_width = IF_TYPE_STD; 343 344 rockchip_sfc_wait_idle(sfc, 10); 345 346 if (sfc->addr_bits == SFC_ADDR_24BITS || 347 sfc->addr_bits == SFC_ADDR_32BITS) 348 data_width = rockchip_sfc_get_if_type(sfc); 349 350 SFC_DBG("--- sfc.addr_bit %x\n", sfc->addr_bits); 351 if (sfc->addr_bits == SFC_ADDR_XBITS) 352 writel(sfc->addr_xbits_ext - 1, ®s->abit); 353 354 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) { 355 SFC_DBG("--- sfc.len_ext %x\n", trb); 356 writel(trb, ®s->len_ext); 357 } 358 359 val = 0x2; 360 val |= (data_width << SFC_DATA_WIDTH_SHIFT); 361 362 SFC_DBG("--- sfc.ctrl %x\n", val); 363 writel(val, ®s->ctrl); 364 365 val = sfc->cmd; 366 val |= (trb & 0x3fff) << SFC_TRB_SHIFT; 367 val |= sfc->rw << SFC_RW_SHIFT; 368 val |= sfc->addr_bits << SFC_ADDR_BITS_SHIFT; 369 val |= sfc->dummy_bits << SFC_DUMMY_BITS_SHIFT; 370 371 SFC_DBG("--- sfc.cmd %x\n", val); 372 writel(val, ®s->cmd); 373 374 if (sfc->addr_bits & SFC_ADDR_XBITS) { 375 SFC_DBG("--- sfc.addr %x\n", sfc->addr); 376 writel(sfc->addr, ®s->addr); 377 } 378 } 379 380 static int rockchip_sfc_dma_xfer(struct rockchip_sfc *sfc, void *buffer, 381 size_t trb) 382 { 383 struct rockchip_sfc_reg *regs = sfc->regbase; 384 struct bounce_buffer bb; 385 unsigned int bb_flags; 386 int timeout = trb * 1000; 387 int ret = 0; 388 int risr; 389 unsigned long tbase; 390 391 if (sfc->rw == SFC_WR) 392 bb_flags = GEN_BB_READ; 393 else 394 bb_flags = GEN_BB_WRITE; 395 396 ret = bounce_buffer_start(&bb, buffer, trb, bb_flags); 397 if (ret) 398 return ret; 399 400 rockchip_sfc_setup_xfer(sfc, bb.len_aligned); 401 402 writel(0xFFFFFFFF, ®s->iclr); 403 writel((unsigned long)bb.bounce_buffer, ®s->dmaaddr); 404 writel(SFC_DMA_START, ®s->dmatr); 405 406 tbase = get_timer(0); 407 do { 408 udelay(1); 409 risr = readl(®s->risr); 410 if (get_timer(tbase) > timeout) { 411 debug("dma timeout\n"); 412 ret = -ETIMEDOUT; 413 break; 414 } 415 } while (!(risr & TRANS_FINISH_INT)); 416 417 writel(0xFFFFFFFF, ®s->iclr); 418 419 bounce_buffer_stop(&bb); 420 421 return ret; 422 } 423 424 static int rockchip_sfc_dma_xfer_prepare(struct rockchip_sfc *sfc, 425 void *buffer, size_t trb) 426 { 427 struct rockchip_sfc_reg *regs = sfc->regbase; 428 429 SFC_DBG("sfc_dma_xfer_prepar enter\n"); 430 431 rockchip_sfc_setup_xfer(sfc, trb); 432 sfc->last_prepare_size = trb; 433 434 flush_dcache_range((unsigned long)buffer, 435 (unsigned long)buffer + trb); 436 437 writel(0xFFFFFFFF, ®s->iclr); 438 writel((unsigned long)buffer, ®s->dmaaddr); 439 writel(SFC_DMA_START, ®s->dmatr); 440 441 return 0; 442 } 443 444 static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int rw, 445 u32 timeout) 446 { 447 struct rockchip_sfc_reg *regs = sfc->regbase; 448 unsigned long tbase = get_timer(0); 449 u8 level; 450 u32 fsr; 451 452 do { 453 fsr = readl(®s->fsr); 454 if (rw == SFC_WR) 455 level = (fsr & SFC_TXLV_MASK) >> SFC_TXLV_SHIFT; 456 else 457 level = (fsr & SFC_RXLV_MASK) >> SFC_RXLV_SHIFT; 458 if (get_timer(tbase) > timeout) 459 return -ETIMEDOUT; 460 udelay(1); 461 } while (!level); 462 463 return level; 464 } 465 466 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 467 { 468 struct rockchip_sfc_reg *regs = sfc->regbase; 469 u32 bytes = len & 0x3; 470 u32 words = len >> 2; 471 int tx_level = 0; 472 u32 val = 0; 473 u8 count; 474 475 while (words) { 476 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 477 if (tx_level <= 0) 478 return tx_level; 479 count = min(words, (u32)tx_level); 480 writesl(®s->data, buf, count); 481 buf += count; 482 words -= count; 483 } 484 485 /* handle the last non 4byte aligned bytes */ 486 if (bytes) { 487 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 488 if (tx_level <= 0) 489 return tx_level; 490 memcpy(&val, buf, bytes); 491 writel(val, ®s->data); 492 } 493 494 return 0; 495 } 496 497 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 498 { 499 struct rockchip_sfc_reg *regs = sfc->regbase; 500 u32 bytes = len & 0x3; 501 u32 words = len >> 2; 502 int rx_level = 0; 503 u32 count; 504 u32 val; 505 506 while (words) { 507 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 508 if (rx_level <= 0) 509 return rx_level; 510 count = min(words, (u32)rx_level); 511 readsl(®s->data, buf, count); 512 buf += count; 513 words -= count; 514 } 515 516 /* handle the last non 4 bytes aligned bytes */ 517 if (bytes) { 518 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 519 if (rx_level <= 0) 520 return rx_level; 521 val = readl(®s->data); 522 memcpy(buf, &val, bytes); 523 } 524 525 return 0; 526 } 527 528 static int rockchip_sfc_pio_xfer(struct rockchip_sfc *sfc, void *buf, u32 len) 529 { 530 int ret = 0; 531 532 rockchip_sfc_setup_xfer(sfc, len); 533 534 if (len) { 535 if (sfc->rw == SFC_WR) 536 ret = rockchip_sfc_write_fifo(sfc, (u32 *)buf, len); 537 else 538 ret = rockchip_sfc_read_fifo(sfc, (u32 *)buf, len); 539 } 540 541 return ret; 542 } 543 544 static int rockchip_sfc_read(struct rockchip_sfc *sfc, u32 offset, 545 void *buf, size_t len) 546 { 547 u32 dma_trans; 548 u32 trb; 549 u8 bytes; 550 int ret; 551 552 if (len >= ARCH_DMA_MINALIGN) { 553 bytes = len & (ARCH_DMA_MINALIGN - 1); 554 dma_trans = len - bytes; 555 } else { 556 dma_trans = 0; 557 bytes = len; 558 } 559 560 while (dma_trans) { 561 trb = min_t(size_t, dma_trans, sfc->max_iosize); 562 if (sfc->prepare) 563 ret = rockchip_sfc_dma_xfer_prepare(sfc, buf, len); 564 else 565 ret = rockchip_sfc_dma_xfer(sfc, buf, trb); 566 if (ret < 0) 567 return ret; 568 dma_trans -= trb; 569 sfc->addr += trb; 570 buf += trb; 571 } 572 573 /* 574 * transfer the last non dma anligned byte by pio mode 575 */ 576 if (bytes) 577 ret = rockchip_sfc_pio_xfer(sfc, buf, bytes); 578 579 return 0; 580 } 581 582 static int rockchip_sfc_write(struct rockchip_sfc *sfc, u32 offset, 583 void *buf, size_t len) 584 { 585 if (len > sfc->max_iosize) { 586 printf("out of the max sfc trb"); 587 return -EINVAL; 588 } 589 590 if (len && !(len & (ARCH_DMA_MINALIGN - 1))) 591 return rockchip_sfc_dma_xfer(sfc, buf, len); 592 else 593 return rockchip_sfc_pio_xfer(sfc, buf, len); 594 595 return 0; 596 } 597 598 static int rockchip_sfc_do_xfer(struct rockchip_sfc *sfc, void *buf, size_t len) 599 { 600 if (sfc->rw) 601 return rockchip_sfc_write(sfc, sfc->addr, buf, len); 602 else 603 return rockchip_sfc_read(sfc, sfc->addr, buf, len); 604 } 605 606 #if CONFIG_IS_ENABLED(CLK) 607 static void rockchip_sfc_delay_lines_training(struct udevice *bus, struct rockchip_sfc *sfc) 608 { 609 u8 id[3], id_temp[3]; 610 u16 cell_max = sfc->max_dll_cells; 611 u16 right, left = 0; 612 u16 step = SFC_DLL_TRANING_STEP; 613 bool dll_valid = false; 614 615 sfc->cmd = 0x9f; 616 sfc->addr = 0; 617 sfc->addr_bits = 0; 618 sfc->addr_xbits_ext = 8; 619 sfc->dummy_bits = 0; 620 sfc->rw = 0; 621 622 clk_set_rate(&sfc->clk, SFC_DLL_THRESHOLD_RATE); 623 rockchip_sfc_pio_xfer(sfc, (void *)&id, 3); 624 if ((0xFF == id[0] && 0xFF == id[1]) || 625 (0x00 == id[0] && 0x00 == id[1])) { 626 dev_dbg(bus, "no dev, dll by pass\n"); 627 clk_set_rate(&sfc->clk, sfc->speed_hz); 628 629 return; 630 } 631 632 clk_set_rate(&sfc->clk, sfc->speed_hz); 633 for (right = 0; right <= cell_max; right += step) { 634 int ret; 635 636 rockchip_sfc_set_delay_lines(sfc, right); 637 rockchip_sfc_pio_xfer(sfc, (void *)&id_temp, 3); 638 dev_dbg(bus, "dll read flash id:%x %x %x\n", 639 id_temp[0], id_temp[1], id_temp[2]); 640 641 ret = memcmp(&id, &id_temp, 3); 642 if (dll_valid && ret) { 643 right -= step; 644 645 break; 646 } 647 if (!dll_valid && !ret) 648 left = right; 649 650 if (!ret) 651 dll_valid = true; 652 653 /* Add cell_max to loop */ 654 if (right == cell_max) 655 break; 656 if (right + step > cell_max) 657 right = cell_max - step; 658 } 659 660 if (dll_valid && (right - left) >= SFC_DLL_TRANING_VALID_WINDOW) { 661 if (left == 0 && right < cell_max) 662 sfc->dll_cells = left + (right - left) * 2 / 5; 663 else 664 sfc->dll_cells = left + (right - left) / 2; 665 } else { 666 sfc->dll_cells = 0; 667 } 668 669 if (sfc->dll_cells) { 670 dev_dbg(bus, "%d %d %d dll training success in %dHz max_cells=%u sfc_ver=%d\n", 671 left, right, sfc->dll_cells, sfc->speed_hz, 672 cell_max, rockchip_sfc_get_version(sfc)); 673 rockchip_sfc_set_delay_lines(sfc, sfc->dll_cells); 674 } else { 675 dev_err(bus, "%d %d dll training failed in %dHz, reduce the frequency\n", 676 left, right, sfc->speed_hz); 677 rockchip_sfc_set_delay_lines(sfc, 0); 678 clk_set_rate(&sfc->clk, SFC_DLL_THRESHOLD_RATE); 679 sfc->speed_hz = SFC_DLL_THRESHOLD_RATE; 680 } 681 } 682 #endif 683 684 static int rockchip_sfc_xfer(struct udevice *dev, unsigned int bitlen, 685 const void *dout, void *din, unsigned long flags) 686 { 687 struct udevice *bus = dev->parent; 688 struct rockchip_sfc *sfc = dev_get_priv(bus); 689 int len = bitlen >> 3; 690 u8 *pcmd = (u8 *)dout; 691 void *data_buf; 692 int ret = 0; 693 694 if (flags & SPI_XFER_BEGIN) { 695 sfc->cmd = pcmd[0]; 696 switch (len) { 697 case 6: /* Nor >16MB 0x6b dummy op */ 698 sfc->addr_bits = SFC_ADDR_32BITS; 699 sfc->dummy_bits = 8; 700 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 701 break; 702 case 5: /* Nor <=16MB 0x6b dummy op, Nor >16MB no dummy op */ 703 if (sfc->cmd == 0x6b) { 704 sfc->addr_bits = SFC_ADDR_24BITS; 705 sfc->dummy_bits = 8; 706 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 707 } else { 708 sfc->addr_bits = SFC_ADDR_32BITS; 709 sfc->dummy_bits = 0; 710 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 711 } 712 break; 713 case 4: /* Nand erase and read, Nor <=16MB no dummy op */ 714 sfc->addr_bits = SFC_ADDR_24BITS; 715 sfc->dummy_bits = 0; 716 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 717 break; 718 case 3: /* Nand prog, */ 719 sfc->addr_bits = SFC_ADDR_XBITS; 720 sfc->addr_xbits_ext = 16; 721 sfc->dummy_bits = 0; 722 sfc->addr = pcmd[2] | pcmd[1] << 8; 723 break; 724 case 2: /* Nand read/write feature */ 725 sfc->addr_bits = SFC_ADDR_XBITS; 726 sfc->addr_xbits_ext = 8; 727 sfc->dummy_bits = 0; 728 sfc->addr = pcmd[1]; 729 break; 730 default: /* Nand/Nor Read/Write status */ 731 sfc->addr_bits = SFC_ADDR_0BITS; 732 sfc->dummy_bits = 0; 733 sfc->addr = 0; 734 break; 735 } 736 SFC_DBG("%s %d %x %d %d %x\n", __func__, len, sfc->cmd, 737 sfc->addr_bits, sfc->dummy_bits, sfc->addr); 738 } 739 if (flags & SPI_XFER_END) { 740 if (din) { 741 sfc->rw = SFC_RD; 742 data_buf = din; 743 } else { 744 sfc->rw = SFC_WR; 745 data_buf = (void *)dout; 746 } 747 748 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 749 len = 0; 750 data_buf = NULL; 751 } 752 753 sfc->prepare = flags & SPI_XFER_PREPARE ? true : false; 754 755 if (sfc->cmd == 0x9f && len == 4) { 756 /* SPI Nand read id */ 757 sfc->addr_bits = SFC_ADDR_XBITS; 758 sfc->addr_xbits_ext = 8; 759 sfc->dummy_bits = 0; 760 sfc->addr = 0; 761 ((u8 *)data_buf)[0] = 0xff; 762 ret = rockchip_sfc_do_xfer(sfc, &((u8 *)data_buf)[1], 3); 763 } else { 764 ret = rockchip_sfc_do_xfer(sfc, data_buf, len); 765 } 766 } 767 768 return ret; 769 } 770 771 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 772 { 773 struct rockchip_sfc *sfc = dev_get_priv(bus); 774 775 if (speed > sfc->max_freq) 776 speed = sfc->max_freq; 777 778 if (speed == sfc->speed_hz) 779 return 0; 780 781 #if CONFIG_IS_ENABLED(CLK) 782 clk_set_rate(&sfc->clk, speed); 783 sfc->speed_hz = speed; 784 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4 && 785 clk_get_rate(&sfc->clk) > SFC_DLL_THRESHOLD_RATE) 786 rockchip_sfc_delay_lines_training(bus, sfc); 787 else if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 788 rockchip_sfc_set_delay_lines(sfc, 0); 789 SFC_DBG("%s clk= %ld\n", __func__, clk_get_rate(&sfc->clk)); 790 #else 791 pr_err("%s failed, CLK not support\n", __func__); 792 #endif 793 return 0; 794 } 795 796 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 797 { 798 struct rockchip_sfc *sfc = dev_get_priv(bus); 799 800 sfc->mode = mode; 801 802 return 0; 803 } 804 805 static const struct dm_spi_ops rockchip_sfc_ops = { 806 .xfer = rockchip_sfc_xfer, 807 .set_speed = rockchip_sfc_set_speed, 808 .set_mode = rockchip_sfc_set_mode, 809 }; 810 811 static const struct udevice_id rockchip_sfc_ids[] = { 812 { .compatible = "rockchip,sfc" }, 813 { } 814 }; 815 816 U_BOOT_DRIVER(rockchip_sfc_driver) = { 817 .name = "rockchip_sfc", 818 .id = UCLASS_SPI, 819 .of_match = rockchip_sfc_ids, 820 .ops = &rockchip_sfc_ops, 821 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 822 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc_platdata), 823 .priv_auto_alloc_size = sizeof(struct rockchip_sfc), 824 .probe = rockchip_sfc_probe, 825 }; 826