1 /* 2 * SFC driver for rockchip 3 * 4 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 5 * Yifeng.zhao, Software Engineering, <zhao0116@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <bouncebuf.h> 12 #include <clk.h> 13 #include <dm.h> 14 #include <dt-structs.h> 15 #include <errno.h> 16 #include <spi.h> 17 #include <linux/errno.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/periph.h> 21 #include <dm/pinctrl.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #ifdef SFC_DEBUG 26 #define SFC_DBG printf 27 #else 28 #define SFC_DBG(args...) 29 #endif 30 31 struct rockchip_sfc_reg { 32 u32 ctrl; 33 u32 imr; 34 u32 iclr; 35 u32 ftlr; 36 u32 rcvr; 37 u32 ax; 38 u32 abit; 39 u32 isr; 40 u32 fsr; 41 u32 sr; 42 u32 risr; 43 u32 ver; 44 u32 reserved[20]; 45 u32 dmatr; 46 u32 dmaaddr; 47 u32 len_ctrl; 48 u32 len_ext; 49 u32 reserved1[28]; 50 u32 cmd; 51 u32 addr; 52 u32 data; 53 }; 54 55 check_member(rockchip_sfc_reg, data, 0x108); 56 57 /*SFC_CTRL*/ 58 #define SFC_DATA_WIDTH_SHIFT 12 59 #define SFC_DATA_WIDTH_MASK GENMASK(13, 12) 60 #define SFC_ADDR_WIDTH_SHIFT 10 61 #define SFC_ADDR_WIDTH_MASK GENMASK(11, 10) 62 #define SFC_CMD_WIDTH_SHIFT 8 63 #define SFC_CMD_WIDTH_MASK GENMASK(9, 8) 64 #define SFC_DATA_SHIFT_NEGETIVE BIT(1) 65 66 /*SFC_CMD*/ 67 #define SFC_DUMMY_BITS_SHIFT 8 68 #define SFC_RW_SHIFT 12 69 #define SFC_WR 1 70 #define SFC_RD 0 71 #define SFC_ADDR_BITS_SHIFT 14 72 #define SFC_ADDR_BITS_MASK GENMASK(15, 14) 73 #define SFC_ADDR_0BITS 0 74 #define SFC_ADDR_24BITS 1 75 #define SFC_ADDR_32BITS 2 76 #define SFC_ADDR_XBITS 3 77 #define SFC_TRB_SHIFT (16) 78 #define SFC_TRB_MASK GENMASK(29, 16) 79 80 /* Dma start trigger signal. Auto cleared after write */ 81 #define SFC_DMA_START BIT(0) 82 83 #define SFC_RESET BIT(0) 84 85 /*SFC_FSR*/ 86 #define SFC_RXLV_SHIFT (16) 87 #define SFC_RXLV_MASK GENMASK(20, 16) 88 #define SFC_TXLV_SHIFT (8) 89 #define SFC_TXLV_MASK GENMASK(12, 8) 90 #define SFC_RX_FULL BIT(3) /* rx fifo full */ 91 #define SFC_RX_EMPTY BIT(2) /* rx fifo empty */ 92 #define SFC_TX_EMPTY BIT(1) /* tx fifo empty */ 93 #define SFC_TX_FULL BIT(0) /* tx fifo full */ 94 95 #define SFC_BUSY BIT(0) /* sfc busy flag */ 96 97 /*SFC_RISR*/ 98 #define DMA_FINISH_INT BIT(7) /* dma interrupt */ 99 #define SPI_ERR_INT BIT(6) /* Nspi error interrupt */ 100 #define AHB_ERR_INT BIT(5) /* Ahb bus error interrupt */ 101 #define TRANS_FINISH_INT BIT(4) /* Transfer finish interrupt */ 102 #define TX_EMPTY_INT BIT(3) /* Tx fifo empty interrupt */ 103 #define TX_OF_INT BIT(2) /* Tx fifo overflow interrupt */ 104 #define RX_UF_INT BIT(1) /* Rx fifo underflow interrupt */ 105 #define RX_FULL_INT BIT(0) /* Rx fifo full interrupt */ 106 107 #define SFC_MAX_TRB_VER3 (512 * 31) 108 #define SFC_MAX_TRB_VER4 (0xFFFFFFFF) 109 110 #define SFC_MAX_RATE (100 * 1000 * 1000) 111 #define SFC_DEFAULT_RATE (80 * 1000 * 1000) 112 #define SFC_MIN_RATE (10 * 1000 * 1000) 113 114 #define SFC_VER_3 0x3 115 #define SFC_VER_4 0x4 116 117 enum rockchip_sfc_if_type { 118 IF_TYPE_STD, 119 IF_TYPE_DUAL, 120 IF_TYPE_QUAD, 121 }; 122 123 struct rockchip_sfc_platdata { 124 s32 frequency; 125 void *base; 126 }; 127 128 struct rockchip_sfc { 129 struct rockchip_sfc_reg *regbase; 130 struct clk clk; 131 unsigned int max_freq; 132 unsigned int mode; 133 unsigned int speed_hz; 134 u32 max_iosize; 135 bool prepare; 136 u32 last_prepare_size; 137 u32 cmd; 138 u32 addr; 139 u8 addr_bits; 140 u8 addr_xbits_ext; 141 u8 dummy_bits; 142 u8 rw; 143 u32 trb; 144 }; 145 146 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 147 { 148 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 149 struct rockchip_sfc *sfc = dev_get_priv(bus); 150 int ret; 151 152 plat->base = dev_read_addr_ptr(bus); 153 ret = clk_get_by_index(bus, 0, &sfc->clk); 154 if (ret < 0) { 155 printf("Could not get clock for %s: %d\n", bus->name, ret); 156 return ret; 157 } 158 159 return 0; 160 } 161 162 u32 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 163 { 164 struct rockchip_sfc_reg *regs = sfc->regbase; 165 166 return (u32)(readl(®s->ver) & 0xFFFF); 167 } 168 169 static int rockchip_sfc_probe(struct udevice *bus) 170 { 171 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 172 struct rockchip_sfc *sfc = dev_get_priv(bus); 173 struct rockchip_sfc_reg *regs; 174 struct dm_spi_bus *dm_spi_bus; 175 176 dm_spi_bus = bus->uclass_priv; 177 dm_spi_bus->max_hz = plat->frequency; 178 sfc->regbase = (struct rockchip_sfc_reg *)plat->base; 179 sfc->max_freq = SFC_MAX_RATE; 180 sfc->speed_hz = SFC_DEFAULT_RATE; 181 clk_set_rate(&sfc->clk, sfc->speed_hz); 182 183 regs = sfc->regbase; 184 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) { 185 sfc->max_iosize = SFC_MAX_TRB_VER4; 186 writel(1, ®s->len_ctrl); 187 } else { 188 sfc->max_iosize = SFC_MAX_TRB_VER3; 189 } 190 191 return 0; 192 } 193 194 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 195 { 196 struct rockchip_sfc_reg *regs = sfc->regbase; 197 int tbase = get_timer(0); 198 u32 rcvr; 199 int ret = 0; 200 201 writel(SFC_RESET, ®s->rcvr); 202 do { 203 rcvr = readl(®s->rcvr); 204 if (get_timer(tbase) > 1000) { 205 debug("sfc reset timeout\n"); 206 ret = -ETIMEDOUT; 207 break; 208 } 209 udelay(1); 210 } while (rcvr); 211 212 writel(0xFFFFFFFF, ®s->iclr); 213 214 debug("sfc reset\n"); 215 216 return ret; 217 } 218 219 static int rockchip_sfc_dma_xfer_wait_finished(struct rockchip_sfc *sfc) 220 { 221 struct rockchip_sfc_reg *regs = sfc->regbase; 222 int timeout = sfc->last_prepare_size * 10; 223 unsigned long tbase; 224 int ret = 0; 225 int risr; 226 227 tbase = get_timer(0); 228 do { 229 udelay(1); 230 risr = readl(®s->risr); 231 if (get_timer(tbase) > timeout) { 232 debug("dma timeout\n"); 233 ret = -ETIMEDOUT; 234 break; 235 } 236 } while (!(risr & TRANS_FINISH_INT)); 237 sfc->last_prepare_size = 0; 238 239 return ret; 240 } 241 242 /* The SFC_CTRL register is a global control register, 243 * when the controller is in busy state(SFC_SR), 244 * SFC_CTRL cannot be set. 245 */ 246 static int rockchip_sfc_wait_idle(struct rockchip_sfc *sfc, 247 u32 timeout_ms) 248 { 249 struct rockchip_sfc_reg *regs = sfc->regbase; 250 unsigned long tbase = get_timer(0); 251 u32 sr, fsr; 252 253 if (sfc->last_prepare_size && rockchip_sfc_dma_xfer_wait_finished(sfc)) 254 return -ETIMEDOUT; 255 256 while (1) { 257 sr = readl(®s->sr); 258 fsr = readl(®s->fsr); 259 if ((fsr & SFC_TX_EMPTY) && 260 (fsr & SFC_RX_EMPTY) && 261 !(sr & SFC_BUSY)) 262 break; 263 if (get_timer(tbase) > timeout_ms) { 264 printf("waite sfc idle timeout(sr:0x%08x fsr:0x%08x)\n", 265 sr, fsr); 266 rockchip_sfc_reset(sfc); 267 return -ETIMEDOUT; 268 } 269 udelay(100); 270 } 271 272 return 0; 273 } 274 275 static u8 rockchip_sfc_get_if_type(struct rockchip_sfc *sfc) 276 { 277 int type = IF_TYPE_STD; 278 279 if (sfc->rw == SFC_WR) { 280 if (sfc->mode & SPI_TX_QUAD) 281 type = IF_TYPE_QUAD; 282 else if (sfc->mode & SPI_TX_DUAL) 283 type = IF_TYPE_DUAL; 284 else 285 type = IF_TYPE_STD; 286 } else { 287 if (sfc->mode & SPI_RX_QUAD) 288 type = IF_TYPE_QUAD; 289 else if (sfc->mode & SPI_RX_DUAL) 290 type = IF_TYPE_DUAL; 291 else 292 type = IF_TYPE_STD; 293 } 294 295 return type; 296 } 297 298 static void rockchip_sfc_setup_xfer(struct rockchip_sfc *sfc, u32 trb) 299 { 300 struct rockchip_sfc_reg *regs = sfc->regbase; 301 u32 val; 302 u8 data_width = IF_TYPE_STD; 303 304 rockchip_sfc_wait_idle(sfc, 10); 305 306 if (sfc->addr_bits == SFC_ADDR_24BITS || 307 sfc->addr_bits == SFC_ADDR_32BITS) 308 data_width = rockchip_sfc_get_if_type(sfc); 309 310 SFC_DBG("--- sfc.addr_bit %x\n", sfc->addr_bits); 311 if (sfc->addr_bits == SFC_ADDR_XBITS) 312 writel(sfc->addr_xbits_ext - 1, ®s->abit); 313 314 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) { 315 SFC_DBG("--- sfc.len_ext %x\n", trb); 316 writel(trb, ®s->len_ext); 317 } 318 319 val = 0x02; 320 val |= (data_width << SFC_DATA_WIDTH_SHIFT); 321 322 SFC_DBG("--- sfc.ctrl %x\n", val); 323 writel(val, ®s->ctrl); 324 325 val = sfc->cmd; 326 val |= (trb & 0x3fff) << SFC_TRB_SHIFT; 327 val |= sfc->rw << SFC_RW_SHIFT; 328 val |= sfc->addr_bits << SFC_ADDR_BITS_SHIFT; 329 val |= sfc->dummy_bits << SFC_DUMMY_BITS_SHIFT; 330 331 SFC_DBG("--- sfc.cmd %x\n", val); 332 writel(val, ®s->cmd); 333 334 if (sfc->addr_bits & SFC_ADDR_XBITS) { 335 SFC_DBG("--- sfc.addr %x\n", sfc->addr); 336 writel(sfc->addr, ®s->addr); 337 } 338 } 339 340 static int rockchip_sfc_dma_xfer(struct rockchip_sfc *sfc, void *buffer, 341 size_t trb) 342 { 343 struct rockchip_sfc_reg *regs = sfc->regbase; 344 struct bounce_buffer bb; 345 unsigned int bb_flags; 346 int timeout = trb * 1000; 347 int ret = 0; 348 int risr; 349 unsigned long tbase; 350 351 if (sfc->rw == SFC_WR) 352 bb_flags = GEN_BB_READ; 353 else 354 bb_flags = GEN_BB_WRITE; 355 356 ret = bounce_buffer_start(&bb, buffer, trb, bb_flags); 357 if (ret) 358 return ret; 359 360 rockchip_sfc_setup_xfer(sfc, bb.len_aligned); 361 362 writel(0xFFFFFFFF, ®s->iclr); 363 writel((unsigned long)bb.bounce_buffer, ®s->dmaaddr); 364 writel(SFC_DMA_START, ®s->dmatr); 365 366 tbase = get_timer(0); 367 do { 368 udelay(1); 369 risr = readl(®s->risr); 370 if (get_timer(tbase) > timeout) { 371 debug("dma timeout\n"); 372 ret = -ETIMEDOUT; 373 break; 374 } 375 } while (!(risr & TRANS_FINISH_INT)); 376 377 writel(0xFFFFFFFF, ®s->iclr); 378 379 bounce_buffer_stop(&bb); 380 381 return ret; 382 } 383 384 static int rockchip_sfc_dma_xfer_prepare(struct rockchip_sfc *sfc, 385 void *buffer, size_t trb) 386 { 387 struct rockchip_sfc_reg *regs = sfc->regbase; 388 389 SFC_DBG("sfc_dma_xfer_prepar enter\n"); 390 391 rockchip_sfc_setup_xfer(sfc, trb); 392 sfc->last_prepare_size = trb; 393 394 flush_dcache_range((unsigned long)buffer, 395 (unsigned long)buffer + trb); 396 397 writel(0xFFFFFFFF, ®s->iclr); 398 writel((unsigned long)buffer, ®s->dmaaddr); 399 writel(SFC_DMA_START, ®s->dmatr); 400 401 return 0; 402 } 403 404 static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int rw, 405 u32 timeout) 406 { 407 struct rockchip_sfc_reg *regs = sfc->regbase; 408 unsigned long tbase = get_timer(0); 409 u8 level; 410 u32 fsr; 411 412 do { 413 fsr = readl(®s->fsr); 414 if (rw == SFC_WR) 415 level = (fsr & SFC_TXLV_MASK) >> SFC_TXLV_SHIFT; 416 else 417 level = (fsr & SFC_RXLV_MASK) >> SFC_RXLV_SHIFT; 418 if (get_timer(tbase) > timeout) 419 return -ETIMEDOUT; 420 udelay(1); 421 } while (!level); 422 423 return level; 424 } 425 426 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 427 { 428 struct rockchip_sfc_reg *regs = sfc->regbase; 429 u32 bytes = len & 0x3; 430 u32 words = len >> 2; 431 int tx_level = 0; 432 u32 val = 0; 433 u8 count; 434 435 while (words) { 436 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 437 if (tx_level <= 0) 438 return tx_level; 439 count = min(words, (u32)tx_level); 440 writesl(®s->data, buf, count); 441 buf += count; 442 words -= count; 443 } 444 445 /* handle the last non 4byte aligned bytes */ 446 if (bytes) { 447 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 448 if (tx_level <= 0) 449 return tx_level; 450 memcpy(&val, buf, bytes); 451 writel(val, ®s->data); 452 } 453 454 return 0; 455 } 456 457 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 458 { 459 struct rockchip_sfc_reg *regs = sfc->regbase; 460 u32 bytes = len & 0x3; 461 u32 words = len >> 2; 462 int rx_level = 0; 463 u32 count; 464 u32 val; 465 466 while (words) { 467 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 468 if (rx_level <= 0) 469 return rx_level; 470 count = min(words, (u32)rx_level); 471 readsl(®s->data, buf, count); 472 buf += count; 473 words -= count; 474 } 475 476 /* handle the last non 4 bytes aligned bytes */ 477 if (bytes) { 478 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 479 if (rx_level <= 0) 480 return rx_level; 481 val = readl(®s->data); 482 memcpy(buf, &val, bytes); 483 } 484 485 return 0; 486 } 487 488 static int rockchip_sfc_pio_xfer(struct rockchip_sfc *sfc, void *buf, u32 len) 489 { 490 int ret = 0; 491 492 rockchip_sfc_setup_xfer(sfc, len); 493 494 if (len) { 495 if (sfc->rw == SFC_WR) 496 ret = rockchip_sfc_write_fifo(sfc, (u32 *)buf, len); 497 else 498 ret = rockchip_sfc_read_fifo(sfc, (u32 *)buf, len); 499 } 500 501 return ret; 502 } 503 504 static int rockchip_sfc_read(struct rockchip_sfc *sfc, u32 offset, 505 void *buf, size_t len) 506 { 507 u32 dma_trans; 508 u32 trb; 509 u8 bytes; 510 int ret; 511 512 if (len >= ARCH_DMA_MINALIGN) { 513 bytes = len & (ARCH_DMA_MINALIGN - 1); 514 dma_trans = len - bytes; 515 } else { 516 dma_trans = 0; 517 bytes = len; 518 } 519 520 while (dma_trans) { 521 trb = min_t(size_t, dma_trans, sfc->max_iosize); 522 if (sfc->prepare) 523 ret = rockchip_sfc_dma_xfer_prepare(sfc, buf, len); 524 else 525 ret = rockchip_sfc_dma_xfer(sfc, buf, trb); 526 if (ret < 0) 527 return ret; 528 dma_trans -= trb; 529 sfc->addr += trb; 530 buf += trb; 531 } 532 533 /* 534 * transfer the last non dma anligned byte by pio mode 535 */ 536 if (bytes) 537 ret = rockchip_sfc_pio_xfer(sfc, buf, bytes); 538 539 return 0; 540 } 541 542 static int rockchip_sfc_write(struct rockchip_sfc *sfc, u32 offset, 543 void *buf, size_t len) 544 { 545 if (len > sfc->max_iosize) { 546 printf("out of the max sfc trb"); 547 return -EINVAL; 548 } 549 550 if (len && !(len & (ARCH_DMA_MINALIGN - 1))) 551 return rockchip_sfc_dma_xfer(sfc, buf, len); 552 else 553 return rockchip_sfc_pio_xfer(sfc, buf, len); 554 555 return 0; 556 } 557 558 static int rockchip_sfc_do_xfer(struct rockchip_sfc *sfc, void *buf, size_t len) 559 { 560 if (sfc->rw) 561 return rockchip_sfc_write(sfc, sfc->addr, buf, len); 562 else 563 return rockchip_sfc_read(sfc, sfc->addr, buf, len); 564 } 565 566 static int rockchip_sfc_xfer(struct udevice *dev, unsigned int bitlen, 567 const void *dout, void *din, unsigned long flags) 568 { 569 struct udevice *bus = dev->parent; 570 struct rockchip_sfc *sfc = dev_get_priv(bus); 571 int len = bitlen >> 3; 572 u8 *pcmd = (u8 *)dout; 573 void *data_buf; 574 int ret = 0; 575 576 if (flags & SPI_XFER_BEGIN) { 577 sfc->cmd = pcmd[0]; 578 switch (len) { 579 case 6: /* Nor >16MB 0x6b dummy op */ 580 sfc->addr_bits = SFC_ADDR_32BITS; 581 sfc->dummy_bits = 8; 582 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 583 break; 584 case 5: /* Nor <=16MB 0x6b dummy op, Nor >16MB no dummy op */ 585 if (sfc->cmd == 0x6b) { 586 sfc->addr_bits = SFC_ADDR_24BITS; 587 sfc->dummy_bits = 8; 588 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 589 } else { 590 sfc->addr_bits = SFC_ADDR_32BITS; 591 sfc->dummy_bits = 0; 592 sfc->addr = pcmd[4] | (pcmd[3] << 8) | (pcmd[2] << 16) | (pcmd[1] << 24); 593 } 594 break; 595 case 4: /* Nand erase and read, Nor <=16MB no dummy op */ 596 sfc->addr_bits = SFC_ADDR_24BITS; 597 sfc->dummy_bits = 0; 598 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 599 break; 600 case 3: /* Nand prog, */ 601 sfc->addr_bits = SFC_ADDR_XBITS; 602 sfc->addr_xbits_ext = 16; 603 sfc->dummy_bits = 0; 604 sfc->addr = pcmd[2] | pcmd[1] << 8; 605 break; 606 case 2: /* Nand read/write feature */ 607 sfc->addr_bits = SFC_ADDR_XBITS; 608 sfc->addr_xbits_ext = 8; 609 sfc->dummy_bits = 0; 610 sfc->addr = pcmd[1]; 611 break; 612 default: /* Nand/Nor Read/Write status */ 613 sfc->addr_bits = SFC_ADDR_0BITS; 614 sfc->dummy_bits = 0; 615 sfc->addr = 0; 616 break; 617 } 618 SFC_DBG("%s %d %x %d %d %x\n", __func__, len, sfc->cmd, 619 sfc->addr_bits, sfc->dummy_bits, sfc->addr); 620 } 621 if (flags & SPI_XFER_END) { 622 if (din) { 623 sfc->rw = SFC_RD; 624 data_buf = din; 625 } else { 626 sfc->rw = SFC_WR; 627 data_buf = (void *)dout; 628 } 629 630 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 631 len = 0; 632 data_buf = NULL; 633 } 634 635 sfc->prepare = flags & SPI_XFER_PREPARE ? true : false; 636 637 if (sfc->cmd == 0x9f && len == 4) { 638 /* SPI Nand read id */ 639 sfc->addr_bits = SFC_ADDR_XBITS; 640 sfc->addr_xbits_ext = 8; 641 sfc->dummy_bits = 0; 642 sfc->addr = 0; 643 ((u8 *)data_buf)[0] = 0xff; 644 ret = rockchip_sfc_do_xfer(sfc, &((u8 *)data_buf)[1], 3); 645 } else { 646 ret = rockchip_sfc_do_xfer(sfc, data_buf, len); 647 } 648 } 649 650 return ret; 651 } 652 653 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 654 { 655 struct rockchip_sfc *sfc = dev_get_priv(bus); 656 657 if (speed > sfc->max_freq) 658 speed = sfc->max_freq; 659 660 sfc->speed_hz = speed; 661 clk_set_rate(&sfc->clk, sfc->speed_hz); 662 SFC_DBG("%s clk= %ld\n", __func__, clk_get_rate(&sfc->clk)); 663 664 return 0; 665 } 666 667 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 668 { 669 struct rockchip_sfc *sfc = dev_get_priv(bus); 670 671 sfc->mode = mode; 672 673 return 0; 674 } 675 676 static const struct dm_spi_ops rockchip_sfc_ops = { 677 .xfer = rockchip_sfc_xfer, 678 .set_speed = rockchip_sfc_set_speed, 679 .set_mode = rockchip_sfc_set_mode, 680 }; 681 682 static const struct udevice_id rockchip_sfc_ids[] = { 683 { .compatible = "rockchip,sfc" }, 684 { } 685 }; 686 687 U_BOOT_DRIVER(rockchip_sfc_driver) = { 688 .name = "rockchip_sfc", 689 .id = UCLASS_SPI, 690 .of_match = rockchip_sfc_ids, 691 .ops = &rockchip_sfc_ops, 692 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 693 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc_platdata), 694 .priv_auto_alloc_size = sizeof(struct rockchip_sfc), 695 .probe = rockchip_sfc_probe, 696 }; 697