1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Serial Flash Controller Driver 4 * 5 * Copyright (c) 2017-2021, Rockchip Inc. 6 * Author: Shawn Lin <shawn.lin@rock-chips.com> 7 * Chris Morgan <macromorgan@hotmail.com> 8 * Jon Lin <Jon.lin@rock-chips.com> 9 */ 10 11 #include <asm/io.h> 12 #include <bouncebuf.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <linux/bitops.h> 16 #include <linux/delay.h> 17 #include <linux/iopoll.h> 18 #include <spi.h> 19 #include <spi-mem.h> 20 #include <asm/gpio.h> 21 22 /* System control */ 23 #define SFC_CTRL 0x0 24 #define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) 25 #define SFC_CTRL_CMD_BITS_SHIFT 8 26 #define SFC_CTRL_ADDR_BITS_SHIFT 10 27 #define SFC_CTRL_DATA_BITS_SHIFT 12 28 29 /* Interrupt mask */ 30 #define SFC_IMR 0x4 31 #define SFC_IMR_RX_FULL BIT(0) 32 #define SFC_IMR_RX_UFLOW BIT(1) 33 #define SFC_IMR_TX_OFLOW BIT(2) 34 #define SFC_IMR_TX_EMPTY BIT(3) 35 #define SFC_IMR_TRAN_FINISH BIT(4) 36 #define SFC_IMR_BUS_ERR BIT(5) 37 #define SFC_IMR_NSPI_ERR BIT(6) 38 #define SFC_IMR_DMA BIT(7) 39 40 /* Interrupt clear */ 41 #define SFC_ICLR 0x8 42 #define SFC_ICLR_RX_FULL BIT(0) 43 #define SFC_ICLR_RX_UFLOW BIT(1) 44 #define SFC_ICLR_TX_OFLOW BIT(2) 45 #define SFC_ICLR_TX_EMPTY BIT(3) 46 #define SFC_ICLR_TRAN_FINISH BIT(4) 47 #define SFC_ICLR_BUS_ERR BIT(5) 48 #define SFC_ICLR_NSPI_ERR BIT(6) 49 #define SFC_ICLR_DMA BIT(7) 50 51 /* FIFO threshold level */ 52 #define SFC_FTLR 0xc 53 #define SFC_FTLR_TX_SHIFT 0 54 #define SFC_FTLR_TX_MASK 0x1f 55 #define SFC_FTLR_RX_SHIFT 8 56 #define SFC_FTLR_RX_MASK 0x1f 57 58 /* Reset FSM and FIFO */ 59 #define SFC_RCVR 0x10 60 #define SFC_RCVR_RESET BIT(0) 61 62 /* Enhanced mode */ 63 #define SFC_AX 0x14 64 65 /* Address Bit number */ 66 #define SFC_ABIT 0x18 67 68 /* Interrupt status */ 69 #define SFC_ISR 0x1c 70 #define SFC_ISR_RX_FULL_SHIFT BIT(0) 71 #define SFC_ISR_RX_UFLOW_SHIFT BIT(1) 72 #define SFC_ISR_TX_OFLOW_SHIFT BIT(2) 73 #define SFC_ISR_TX_EMPTY_SHIFT BIT(3) 74 #define SFC_ISR_TX_FINISH_SHIFT BIT(4) 75 #define SFC_ISR_BUS_ERR_SHIFT BIT(5) 76 #define SFC_ISR_NSPI_ERR_SHIFT BIT(6) 77 #define SFC_ISR_DMA_SHIFT BIT(7) 78 79 /* FIFO status */ 80 #define SFC_FSR 0x20 81 #define SFC_FSR_TX_IS_FULL BIT(0) 82 #define SFC_FSR_TX_IS_EMPTY BIT(1) 83 #define SFC_FSR_RX_IS_EMPTY BIT(2) 84 #define SFC_FSR_RX_IS_FULL BIT(3) 85 #define SFC_FSR_TXLV_MASK GENMASK(13, 8) 86 #define SFC_FSR_TXLV_SHIFT 8 87 #define SFC_FSR_RXLV_MASK GENMASK(20, 16) 88 #define SFC_FSR_RXLV_SHIFT 16 89 90 /* FSM status */ 91 #define SFC_SR 0x24 92 #define SFC_SR_IS_IDLE 0x0 93 #define SFC_SR_IS_BUSY 0x1 94 95 /* Raw interrupt status */ 96 #define SFC_RISR 0x28 97 #define SFC_RISR_RX_FULL BIT(0) 98 #define SFC_RISR_RX_UNDERFLOW BIT(1) 99 #define SFC_RISR_TX_OVERFLOW BIT(2) 100 #define SFC_RISR_TX_EMPTY BIT(3) 101 #define SFC_RISR_TRAN_FINISH BIT(4) 102 #define SFC_RISR_BUS_ERR BIT(5) 103 #define SFC_RISR_NSPI_ERR BIT(6) 104 #define SFC_RISR_DMA BIT(7) 105 106 /* Version */ 107 #define SFC_VER 0x2C 108 #define SFC_VER_3 0x3 109 #define SFC_VER_4 0x4 110 #define SFC_VER_5 0x5 111 #define SFC_VER_6 0x6 112 #define SFC_VER_8 0x8 113 114 /* Delay line controller resiter */ 115 #define SFC_DLL_CTRL0 0x3C 116 #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) 117 #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU 118 #define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU 119 120 /* Master trigger */ 121 #define SFC_DMA_TRIGGER 0x80 122 #define SFC_DMA_TRIGGER_START 1 123 124 /* Src or Dst addr for master */ 125 #define SFC_DMA_ADDR 0x84 126 127 /* Length control register extension 32GB */ 128 #define SFC_LEN_CTRL 0x88 129 #define SFC_LEN_CTRL_TRB_SEL 1 130 #define SFC_LEN_EXT 0x8C 131 132 /* Command */ 133 #define SFC_CMD 0x100 134 #define SFC_CMD_IDX_SHIFT 0 135 #define SFC_CMD_DUMMY_SHIFT 8 136 #define SFC_CMD_DIR_SHIFT 12 137 #define SFC_CMD_DIR_RD 0 138 #define SFC_CMD_DIR_WR 1 139 #define SFC_CMD_ADDR_SHIFT 14 140 #define SFC_CMD_ADDR_0BITS 0 141 #define SFC_CMD_ADDR_24BITS 1 142 #define SFC_CMD_ADDR_32BITS 2 143 #define SFC_CMD_ADDR_XBITS 3 144 #define SFC_CMD_TRAN_BYTES_SHIFT 16 145 #define SFC_CMD_CS_SHIFT 30 146 147 /* Address */ 148 #define SFC_ADDR 0x104 149 150 /* Data */ 151 #define SFC_DATA 0x108 152 153 #define SFC_CS1_REG_OFFSET 0x200 154 155 #define SFC_MAX_CHIPSELECT_NUM 2 156 157 /* The SFC can transfer max 16KB - 1 at one time 158 * we set it to 15.5KB here for alignment. 159 */ 160 #define SFC_MAX_IOSIZE_VER3 (512 * 31) 161 162 #define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU) 163 164 /* DMA is only enabled for large data transmission */ 165 #define SFC_DMA_TRANS_THRETHOLD (0x40) 166 167 /* Maximum clock values from datasheet suggest keeping clock value under 168 * 150MHz. No minimum or average value is suggested. 169 */ 170 #define SFC_MAX_SPEED (150 * 1000 * 1000) 171 #define SFC_DLL_THRESHOLD_RATE (50 * 1000 * 1000) 172 173 #define SFC_DLL_TRANING_STEP 10 /* Training step */ 174 #define SFC_DLL_TRANING_VALID_WINDOW 80 /* Training Valid DLL winbow */ 175 176 struct rockchip_sfc { 177 struct udevice *dev; 178 void __iomem *regbase; 179 struct clk hclk; 180 struct clk clk; 181 u32 max_freq; 182 u32 cur_speed; 183 u32 cur_real_speed; 184 u32 speed[SFC_MAX_CHIPSELECT_NUM]; 185 bool use_dma; 186 u32 max_iosize; 187 u16 version; 188 189 u32 last_async_size; 190 u32 async; 191 u32 dll_cells[SFC_MAX_CHIPSELECT_NUM]; 192 u32 max_dll_cells; 193 194 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) 195 struct gpio_desc cs_gpios[SFC_MAX_CHIPSELECT_NUM]; 196 #endif 197 }; 198 199 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 200 { 201 int err; 202 u32 status; 203 204 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); 205 206 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, 207 !(status & SFC_RCVR_RESET), 208 1000000); 209 if (err) 210 dev_err(sfc->dev, "SFC reset never finished\n"); 211 212 /* Still need to clear the masked interrupt from RISR */ 213 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 214 215 dev_dbg(sfc->dev, "reset\n"); 216 217 return err; 218 } 219 220 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 221 { 222 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); 223 } 224 225 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) 226 { 227 if (sfc->version >= SFC_VER_4) 228 return SFC_MAX_IOSIZE_VER4; 229 230 return SFC_MAX_IOSIZE_VER3; 231 } 232 233 static u32 rockchip_sfc_get_max_dll_cells(struct rockchip_sfc *sfc) 234 { 235 if (sfc->version > SFC_VER_4) 236 return SFC_DLL_CTRL0_DLL_MAX_VER5; 237 else if (sfc->version == SFC_VER_4) 238 return SFC_DLL_CTRL0_DLL_MAX_VER4; 239 else 240 return 0; 241 } 242 243 static __maybe_unused void rockchip_sfc_set_delay_lines(struct rockchip_sfc *sfc, u16 cells, u8 cs) 244 { 245 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc); 246 u32 val = 0; 247 248 if (cells > cell_max) 249 cells = cell_max; 250 251 if (cells) 252 val = SFC_DLL_CTRL0_SCLK_SMP_DLL | cells; 253 254 writel(val, sfc->regbase + cs * SFC_CS1_REG_OFFSET + SFC_DLL_CTRL0); 255 } 256 257 #if CONFIG_IS_ENABLED(CLK) 258 static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, unsigned long speed) 259 { 260 if (sfc->version >= SFC_VER_8) 261 return clk_set_rate(&sfc->clk, speed * 2); 262 else 263 return clk_set_rate(&sfc->clk, speed); 264 } 265 266 static unsigned long rockchip_sfc_clk_get_rate(struct rockchip_sfc *sfc) 267 { 268 if (sfc->version >= SFC_VER_8) 269 return clk_get_rate(&sfc->clk) / 2; 270 else 271 return clk_get_rate(&sfc->clk); 272 } 273 #endif 274 275 static int rockchip_sfc_init(struct rockchip_sfc *sfc) 276 { 277 #if defined(CONFIG_SPL_BUILD) 278 printf("sfc cmd=%02xH(6BH-x4)\n", readl(sfc->regbase + SFC_CMD) & 0xFF); 279 #endif 280 writel(0, sfc->regbase + SFC_CTRL); 281 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 282 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); 283 284 return 0; 285 } 286 287 static int rockchip_cs_setup(struct udevice *bus) 288 { 289 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) 290 struct rockchip_sfc *sfc = dev_get_platdata(bus); 291 int ret; 292 int i; 293 294 ret = gpio_request_list_by_name(bus, "sfc-cs-gpios", sfc->cs_gpios, 295 ARRAY_SIZE(sfc->cs_gpios), 0); 296 if (ret < 0) { 297 pr_err("Can't get %s gpios! Error: %d\n", bus->name, ret); 298 return ret; 299 } 300 301 for (i = 0; i < ARRAY_SIZE(sfc->cs_gpios); i++) { 302 if (!dm_gpio_is_valid(&sfc->cs_gpios[i])) 303 continue; 304 305 ret = dm_gpio_set_dir_flags(&sfc->cs_gpios[i], 306 GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); 307 if (ret) { 308 dev_err(bus, "Setting cs %d error, ret=%d\n", i, ret); 309 return ret; 310 } 311 } 312 #endif 313 return 0; 314 } 315 316 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 317 { 318 struct rockchip_sfc *sfc = dev_get_platdata(bus); 319 320 sfc->regbase = dev_read_addr_ptr(bus); 321 if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma")) 322 sfc->use_dma = false; 323 else 324 sfc->use_dma = true; 325 #if CONFIG_IS_ENABLED(CLK) 326 int ret; 327 328 ret = clk_get_by_index(bus, 0, &sfc->clk); 329 if (ret < 0) { 330 printf("Could not get clock for %s: %d\n", bus->name, ret); 331 return ret; 332 } 333 334 ret = clk_get_by_index(bus, 1, &sfc->hclk); 335 if (ret < 0) { 336 printf("Could not get ahb clock for %s: %d\n", bus->name, ret); 337 return ret; 338 } 339 #endif 340 341 rockchip_cs_setup(bus); 342 343 return 0; 344 } 345 346 static int rockchip_sfc_probe(struct udevice *bus) 347 { 348 struct rockchip_sfc *sfc = dev_get_platdata(bus); 349 int ret; 350 351 #if CONFIG_IS_ENABLED(CLK) 352 ret = clk_enable(&sfc->hclk); 353 if (ret) 354 dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); 355 356 ret = clk_enable(&sfc->clk); 357 if (ret) 358 dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); 359 #endif 360 /* Initial the version at the first */ 361 sfc->version = rockchip_sfc_get_version(sfc); 362 363 ret = rockchip_sfc_init(sfc); 364 if (ret) 365 goto err_init; 366 367 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); 368 sfc->max_freq = SFC_MAX_SPEED; 369 sfc->dev = bus; 370 371 return 0; 372 373 err_init: 374 #if CONFIG_IS_ENABLED(CLK) 375 clk_disable(&sfc->clk); 376 clk_disable(&sfc->hclk); 377 #endif 378 379 return ret; 380 } 381 382 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 383 { 384 int ret = 0; 385 u32 status; 386 387 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 388 status & SFC_FSR_TXLV_MASK, 389 timeout_us); 390 if (ret) { 391 dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); 392 393 return -ETIMEDOUT; 394 } 395 396 return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; 397 } 398 399 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 400 { 401 int ret = 0; 402 u32 status; 403 404 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 405 status & SFC_FSR_RXLV_MASK, 406 timeout_us); 407 if (ret) { 408 dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); 409 410 return -ETIMEDOUT; 411 } 412 413 return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; 414 } 415 416 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) 417 { 418 if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { 419 /* 420 * SFC not support output DUMMY cycles right after CMD cycles, so 421 * treat it as ADDR cycles. 422 */ 423 op->addr.nbytes = op->dummy.nbytes; 424 op->addr.buswidth = op->dummy.buswidth; 425 op->addr.val = 0xFFFFFFFFF; 426 427 op->dummy.nbytes = 0; 428 } 429 } 430 431 static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout) 432 { 433 unsigned long tbase; 434 435 /* Wait for the DMA interrupt status */ 436 tbase = get_timer(0); 437 while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) { 438 if (get_timer(tbase) > timeout) { 439 printf("dma timeout\n"); 440 rockchip_sfc_reset(sfc); 441 442 return -ETIMEDOUT; 443 } 444 445 udelay(1); 446 } 447 448 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 449 450 return 0; 451 } 452 453 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, 454 struct spi_slave *mem, 455 const struct spi_mem_op *op, 456 u32 len) 457 { 458 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(mem->dev); 459 u32 ctrl = 0, cmd = 0; 460 461 /* set CMD */ 462 cmd = op->cmd.opcode; 463 ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); 464 465 /* set ADDR */ 466 if (op->addr.nbytes) { 467 if (op->addr.nbytes == 4) { 468 cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; 469 } else if (op->addr.nbytes == 3) { 470 cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; 471 } else { 472 cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; 473 writel(op->addr.nbytes * 8 - 1, sfc->regbase + plat->cs * SFC_CS1_REG_OFFSET + SFC_ABIT); 474 } 475 476 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); 477 } 478 479 /* set DUMMY */ 480 if (op->dummy.nbytes) { 481 if (op->dummy.buswidth == 4) 482 cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; 483 else if (op->dummy.buswidth == 2) 484 cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; 485 else 486 cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; 487 } 488 489 /* set DATA */ 490 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ 491 writel(len, sfc->regbase + SFC_LEN_EXT); 492 else 493 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; 494 if (len) { 495 if (op->data.dir == SPI_MEM_DATA_OUT) 496 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 497 498 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); 499 } 500 if (!len && op->addr.nbytes) 501 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 502 503 /* set the Controller */ 504 ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; 505 cmd |= plat->cs << SFC_CMD_CS_SHIFT; 506 507 dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", 508 op->addr.nbytes, op->addr.buswidth, 509 op->dummy.nbytes, op->dummy.buswidth); 510 dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x cs=%x\n", 511 ctrl, cmd, op->addr.val, len, plat->cs); 512 513 writel(ctrl, sfc->regbase + plat->cs * SFC_CS1_REG_OFFSET + SFC_CTRL); 514 writel(cmd, sfc->regbase + SFC_CMD); 515 if (op->addr.nbytes) 516 writel(op->addr.val, sfc->regbase + SFC_ADDR); 517 518 return 0; 519 } 520 521 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) 522 { 523 u8 bytes = len & 0x3; 524 u32 dwords; 525 int tx_level; 526 u32 write_words; 527 u32 tmp = 0; 528 529 dwords = len >> 2; 530 while (dwords) { 531 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 532 if (tx_level < 0) 533 return tx_level; 534 write_words = min_t(u32, tx_level, dwords); 535 writesl(sfc->regbase + SFC_DATA, buf, write_words); 536 buf += write_words << 2; 537 dwords -= write_words; 538 } 539 540 /* write the rest non word aligned bytes */ 541 if (bytes) { 542 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 543 if (tx_level < 0) 544 return tx_level; 545 memcpy(&tmp, buf, bytes); 546 writel(tmp, sfc->regbase + SFC_DATA); 547 } 548 549 return len; 550 } 551 552 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) 553 { 554 u8 bytes = len & 0x3; 555 u32 dwords; 556 u8 read_words; 557 int rx_level; 558 int tmp; 559 560 /* word aligned access only */ 561 dwords = len >> 2; 562 while (dwords) { 563 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 564 if (rx_level < 0) 565 return rx_level; 566 read_words = min_t(u32, rx_level, dwords); 567 readsl(sfc->regbase + SFC_DATA, buf, read_words); 568 buf += read_words << 2; 569 dwords -= read_words; 570 } 571 572 /* read the rest non word aligned bytes */ 573 if (bytes) { 574 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 575 if (rx_level < 0) 576 return rx_level; 577 tmp = readl(sfc->regbase + SFC_DATA); 578 memcpy(buf, &tmp, bytes); 579 } 580 581 return len; 582 } 583 584 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) 585 { 586 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 587 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); 588 writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); 589 590 return len; 591 } 592 593 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, 594 const struct spi_mem_op *op, u32 len) 595 { 596 dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); 597 598 if (op->data.dir == SPI_MEM_DATA_OUT) 599 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); 600 else 601 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); 602 } 603 604 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, 605 const struct spi_mem_op *op, u32 len) 606 { 607 struct bounce_buffer bb; 608 unsigned int bb_flags; 609 void *dma_buf; 610 int ret; 611 612 dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); 613 614 if (op->data.dir == SPI_MEM_DATA_OUT) { 615 dma_buf = (void *)op->data.buf.out; 616 bb_flags = GEN_BB_READ; 617 } else { 618 dma_buf = (void *)op->data.buf.in; 619 bb_flags = GEN_BB_WRITE; 620 } 621 622 ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags); 623 if (ret) 624 return ret; 625 626 ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len); 627 rockchip_sfc_wait_for_dma_finished(sfc, len * 10); 628 bounce_buffer_stop(&bb); 629 630 return ret; 631 } 632 633 static int rockchip_sfc_xfer_data_dma_async(struct rockchip_sfc *sfc, 634 const struct spi_mem_op *op, u32 len) 635 { 636 void *dma_buf; 637 638 if (op->data.dir == SPI_MEM_DATA_OUT) { 639 dma_buf = (void *)op->data.buf.out; 640 flush_dcache_range((unsigned long)dma_buf, 641 (unsigned long)dma_buf + len); 642 } else { 643 dma_buf = (void *)op->data.buf.in; 644 } 645 646 dev_dbg(sfc->dev, "xfer_dma_async len=%x %p\n", len, dma_buf); 647 648 rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)dma_buf, len); 649 sfc->last_async_size = len; 650 651 return 0; 652 } 653 654 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) 655 { 656 int ret = 0; 657 u32 status; 658 659 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, 660 !(status & SFC_SR_IS_BUSY), 661 timeout_us); 662 if (ret) { 663 dev_err(sfc->dev, "wait sfc idle timeout\n"); 664 rockchip_sfc_reset(sfc); 665 666 ret = -EIO; 667 } 668 669 return ret; 670 } 671 672 static int rockchip_spi_set_cs(struct rockchip_sfc *sfc, struct spi_slave *mem, bool enable) 673 { 674 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) 675 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(mem->dev); 676 u32 cs = plat->cs; 677 678 if (!dm_gpio_is_valid(&sfc->cs_gpios[cs])) 679 return 0; 680 681 debug("%s %d %x\n", __func__, cs, enable); 682 dm_gpio_set_value(&sfc->cs_gpios[cs], enable); 683 #endif 684 return 0; 685 } 686 687 #if CONFIG_IS_ENABLED(CLK) 688 static int rockchip_sfc_exec_op_bypass(struct rockchip_sfc *sfc, 689 struct spi_slave *mem, 690 const struct spi_mem_op *op) 691 { 692 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 693 u32 ret; 694 695 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 696 rockchip_spi_set_cs(sfc, mem, true); 697 rockchip_sfc_xfer_setup(sfc, mem, op, len); 698 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 699 if (ret != len) { 700 dev_err(sfc->dev, "xfer data failed ret %d\n", ret); 701 702 return -EIO; 703 } 704 705 ret = rockchip_sfc_xfer_done(sfc, 100000); 706 rockchip_spi_set_cs(sfc, mem, false); 707 708 return ret; 709 } 710 711 static void rockchip_sfc_delay_lines_tuning(struct rockchip_sfc *sfc, struct spi_slave *mem) 712 { 713 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(mem->dev); 714 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1), 715 SPI_MEM_OP_NO_ADDR, 716 SPI_MEM_OP_NO_DUMMY, 717 SPI_MEM_OP_DATA_IN(3, NULL, 1)); 718 u8 id[3], id_temp[3]; 719 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc); 720 u16 right, left = 0; 721 u16 step = SFC_DLL_TRANING_STEP; 722 bool dll_valid = false; 723 u8 cs = plat->cs; 724 725 rockchip_sfc_clk_set_rate(sfc, SFC_DLL_THRESHOLD_RATE); 726 op.data.buf.in = &id; 727 rockchip_sfc_exec_op_bypass(sfc, mem, &op); 728 if ((0xFF == id[0] && 0xFF == id[1]) || 729 (0x00 == id[0] && 0x00 == id[1])) { 730 dev_dbg(sfc->dev, "no dev, dll by pass\n"); 731 rockchip_sfc_clk_set_rate(sfc, sfc->speed[cs]); 732 sfc->speed[cs] = SFC_DLL_THRESHOLD_RATE; 733 734 return; 735 } 736 737 rockchip_sfc_clk_set_rate(sfc, sfc->speed[cs]); 738 op.data.buf.in = &id_temp; 739 for (right = 0; right <= cell_max; right += step) { 740 int ret; 741 742 rockchip_sfc_set_delay_lines(sfc, right, cs); 743 rockchip_sfc_exec_op_bypass(sfc, mem, &op); 744 dev_dbg(sfc->dev, "dll read flash id:%x %x %x\n", 745 id_temp[0], id_temp[1], id_temp[2]); 746 747 ret = memcmp(&id, &id_temp, 3); 748 if (dll_valid && ret) { 749 right -= step; 750 751 break; 752 } 753 if (!dll_valid && !ret) 754 left = right; 755 756 if (!ret) 757 dll_valid = true; 758 759 /* Add cell_max to loop */ 760 if (right == cell_max) 761 break; 762 if (right + step > cell_max) 763 right = cell_max - step; 764 } 765 766 if (dll_valid && (right - left) >= SFC_DLL_TRANING_VALID_WINDOW) { 767 if (left == 0 && right < cell_max) 768 sfc->dll_cells[cs] = left + (right - left) * 2 / 5; 769 else 770 sfc->dll_cells[cs] = left + (right - left) / 2; 771 } else { 772 sfc->dll_cells[cs] = 0; 773 } 774 775 if (sfc->dll_cells[cs]) { 776 dev_dbg(sfc->dev, "%d %d %d dll training success in %dMHz max_cells=%u sfc_ver=%d\n", 777 left, right, sfc->dll_cells[cs], sfc->speed[cs], 778 rockchip_sfc_get_max_dll_cells(sfc), rockchip_sfc_get_version(sfc)); 779 rockchip_sfc_set_delay_lines(sfc, (u16)sfc->dll_cells[cs], cs); 780 } else { 781 dev_err(sfc->dev, "%d %d dll training failed in %dMHz, reduce the speed\n", 782 left, right, sfc->speed[cs]); 783 rockchip_sfc_set_delay_lines(sfc, 0, cs); 784 rockchip_sfc_clk_set_rate(sfc, SFC_DLL_THRESHOLD_RATE); 785 sfc->cur_speed = SFC_DLL_THRESHOLD_RATE; 786 sfc->cur_real_speed = rockchip_sfc_clk_get_rate(sfc); 787 sfc->speed[cs] = SFC_DLL_THRESHOLD_RATE; 788 } 789 } 790 791 #endif 792 793 static int rockchip_sfc_exec_op(struct spi_slave *mem, 794 const struct spi_mem_op *op) 795 { 796 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 797 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(mem->dev); 798 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 799 int ret; 800 801 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4 && 802 sfc->cur_speed != sfc->speed[plat->cs]) { 803 sfc->speed[plat->cs] = sfc->cur_speed; 804 #if CONFIG_IS_ENABLED(CLK) 805 if (sfc->cur_real_speed > SFC_DLL_THRESHOLD_RATE) 806 rockchip_sfc_delay_lines_tuning(sfc, mem); 807 else 808 #endif 809 rockchip_sfc_set_delay_lines(sfc, 0, plat->cs); 810 } 811 812 /* Wait for last async transfer finished */ 813 if (sfc->last_async_size) { 814 rockchip_sfc_wait_for_dma_finished(sfc, sfc->last_async_size); 815 sfc->last_async_size = 0; 816 } 817 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 818 rockchip_spi_set_cs(sfc, mem, true); 819 rockchip_sfc_xfer_setup(sfc, mem, op, len); 820 if (len) { 821 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) { 822 if (mem->mode & SPI_DMA_PREPARE) 823 return rockchip_sfc_xfer_data_dma_async(sfc, op, len); 824 ret = rockchip_sfc_xfer_data_dma(sfc, op, len); 825 } else { 826 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 827 } 828 829 if (ret != len) { 830 dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); 831 832 return -EIO; 833 } 834 } 835 836 ret = rockchip_sfc_xfer_done(sfc, 100000); 837 rockchip_spi_set_cs(sfc, mem, false); 838 839 return ret; 840 } 841 842 static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op) 843 { 844 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 845 846 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); 847 848 return 0; 849 } 850 851 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 852 { 853 struct rockchip_sfc *sfc = dev_get_platdata(bus); 854 855 if (speed > sfc->max_freq) 856 speed = sfc->max_freq; 857 858 if (speed == sfc->cur_speed) 859 return 0; 860 861 #if CONFIG_IS_ENABLED(CLK) 862 int ret = rockchip_sfc_clk_set_rate(sfc, speed); 863 864 if (ret < 0) { 865 dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", 866 speed); 867 return ret; 868 } 869 sfc->cur_speed = speed; 870 sfc->cur_real_speed = rockchip_sfc_clk_get_rate(sfc); 871 872 dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%dHz\n", 873 sfc->cur_speed, sfc->cur_real_speed); 874 #else 875 dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); 876 #endif 877 return 0; 878 } 879 880 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 881 { 882 return 0; 883 } 884 885 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { 886 .adjust_op_size = rockchip_sfc_adjust_op_size, 887 .exec_op = rockchip_sfc_exec_op, 888 }; 889 890 static const struct dm_spi_ops rockchip_sfc_ops = { 891 .mem_ops = &rockchip_sfc_mem_ops, 892 .set_speed = rockchip_sfc_set_speed, 893 .set_mode = rockchip_sfc_set_mode, 894 }; 895 896 static const struct udevice_id rockchip_sfc_ids[] = { 897 { .compatible = "rockchip,sfc"}, 898 {}, 899 }; 900 901 U_BOOT_DRIVER(rockchip_sfc_driver) = { 902 .name = "rockchip_sfc", 903 .id = UCLASS_SPI, 904 .of_match = rockchip_sfc_ids, 905 .ops = &rockchip_sfc_ops, 906 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 907 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc), 908 .probe = rockchip_sfc_probe, 909 }; 910