1 /* 2 * Copyright (c) 2011-12 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * This file is derived from the flashrom project. 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <spi.h> 12 #include <pci.h> 13 #include <pci_ids.h> 14 #include <asm/io.h> 15 16 #include "ich.h" 17 18 #define SPI_OPCODE_WREN 0x06 19 #define SPI_OPCODE_FAST_READ 0x0b 20 21 struct ich_ctlr { 22 pci_dev_t dev; /* PCI device number */ 23 int ich_version; /* Controller version, 7 or 9 */ 24 int ichspi_lock; 25 int locked; 26 uint8_t *opmenu; 27 int menubytes; 28 void *base; /* Base of register set */ 29 uint16_t *preop; 30 uint16_t *optype; 31 uint32_t *addr; 32 uint8_t *data; 33 unsigned databytes; 34 uint8_t *status; 35 uint16_t *control; 36 uint32_t *bbar; 37 uint32_t *pr; /* only for ich9 */ 38 uint8_t *speed; /* pointer to speed control */ 39 ulong max_speed; /* Maximum bus speed in MHz */ 40 }; 41 42 struct ich_ctlr ctlr; 43 44 static inline struct ich_spi_slave *to_ich_spi(struct spi_slave *slave) 45 { 46 return container_of(slave, struct ich_spi_slave, slave); 47 } 48 49 static unsigned int ich_reg(const void *addr) 50 { 51 return (unsigned)(addr - ctlr.base) & 0xffff; 52 } 53 54 static u8 ich_readb(const void *addr) 55 { 56 u8 value = readb(addr); 57 58 debug("read %2.2x from %4.4x\n", value, ich_reg(addr)); 59 60 return value; 61 } 62 63 static u16 ich_readw(const void *addr) 64 { 65 u16 value = readw(addr); 66 67 debug("read %4.4x from %4.4x\n", value, ich_reg(addr)); 68 69 return value; 70 } 71 72 static u32 ich_readl(const void *addr) 73 { 74 u32 value = readl(addr); 75 76 debug("read %8.8x from %4.4x\n", value, ich_reg(addr)); 77 78 return value; 79 } 80 81 static void ich_writeb(u8 value, void *addr) 82 { 83 writeb(value, addr); 84 debug("wrote %2.2x to %4.4x\n", value, ich_reg(addr)); 85 } 86 87 static void ich_writew(u16 value, void *addr) 88 { 89 writew(value, addr); 90 debug("wrote %4.4x to %4.4x\n", value, ich_reg(addr)); 91 } 92 93 static void ich_writel(u32 value, void *addr) 94 { 95 writel(value, addr); 96 debug("wrote %8.8x to %4.4x\n", value, ich_reg(addr)); 97 } 98 99 static void write_reg(const void *value, void *dest, uint32_t size) 100 { 101 memcpy_toio(dest, value, size); 102 } 103 104 static void read_reg(const void *src, void *value, uint32_t size) 105 { 106 memcpy_fromio(value, src, size); 107 } 108 109 static void ich_set_bbar(struct ich_ctlr *ctlr, uint32_t minaddr) 110 { 111 const uint32_t bbar_mask = 0x00ffff00; 112 uint32_t ichspi_bbar; 113 114 minaddr &= bbar_mask; 115 ichspi_bbar = ich_readl(ctlr->bbar) & ~bbar_mask; 116 ichspi_bbar |= minaddr; 117 ich_writel(ichspi_bbar, ctlr->bbar); 118 } 119 120 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 121 { 122 puts("spi_cs_is_valid used but not implemented\n"); 123 return 0; 124 } 125 126 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 127 unsigned int max_hz, unsigned int mode) 128 { 129 struct ich_spi_slave *ich; 130 131 ich = spi_alloc_slave(struct ich_spi_slave, bus, cs); 132 if (!ich) { 133 puts("ICH SPI: Out of memory\n"); 134 return NULL; 135 } 136 137 /* 138 * Yes this controller can only write a small number of bytes at 139 * once! The limit is typically 64 bytes. 140 */ 141 ich->slave.max_write_size = ctlr.databytes; 142 ich->speed = max_hz; 143 144 /* ICH 7 SPI controller only supports array read command */ 145 if (ctlr.ich_version == 7) 146 ich->slave.op_mode_rx = SPI_OPM_RX_AS; 147 148 return &ich->slave; 149 } 150 151 void spi_free_slave(struct spi_slave *slave) 152 { 153 struct ich_spi_slave *ich = to_ich_spi(slave); 154 155 free(ich); 156 } 157 158 /* 159 * Check if this device ID matches one of supported Intel PCH devices. 160 * 161 * Return the ICH version if there is a match, or zero otherwise. 162 */ 163 static int get_ich_version(uint16_t device_id) 164 { 165 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) 166 return 7; 167 168 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 169 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || 170 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 171 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) 172 return 9; 173 174 return 0; 175 } 176 177 /* @return 1 if the SPI flash supports the 33MHz speed */ 178 static int ich9_can_do_33mhz(pci_dev_t dev) 179 { 180 u32 fdod, speed; 181 182 /* Observe SPI Descriptor Component Section 0 */ 183 pci_write_config_dword(dev, 0xb0, 0x1000); 184 185 /* Extract the Write/Erase SPI Frequency from descriptor */ 186 pci_read_config_dword(dev, 0xb4, &fdod); 187 188 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ 189 speed = (fdod >> 21) & 7; 190 191 return speed == 1; 192 } 193 194 static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp) 195 { 196 int last_bus = pci_last_busno(); 197 int bus; 198 199 if (last_bus == -1) { 200 debug("No PCI busses?\n"); 201 return -1; 202 } 203 204 for (bus = 0; bus <= last_bus; bus++) { 205 uint16_t vendor_id, device_id; 206 uint32_t ids; 207 pci_dev_t dev; 208 209 dev = PCI_BDF(bus, 31, 0); 210 pci_read_config_dword(dev, 0, &ids); 211 vendor_id = ids; 212 device_id = ids >> 16; 213 214 if (vendor_id == PCI_VENDOR_ID_INTEL) { 215 *devp = dev; 216 *ich_versionp = get_ich_version(device_id); 217 return 0; 218 } 219 } 220 221 debug("ICH SPI: No ICH found.\n"); 222 return -1; 223 } 224 225 static int ich_init_controller(struct ich_ctlr *ctlr) 226 { 227 uint8_t *rcrb; /* Root Complex Register Block */ 228 uint32_t rcba; /* Root Complex Base Address */ 229 230 pci_read_config_dword(ctlr->dev, 0xf0, &rcba); 231 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ 232 rcrb = (uint8_t *)(rcba & 0xffffc000); 233 if (ctlr->ich_version == 7) { 234 struct ich7_spi_regs *ich7_spi; 235 236 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); 237 ctlr->ichspi_lock = ich_readw(&ich7_spi->spis) & SPIS_LOCK; 238 ctlr->opmenu = ich7_spi->opmenu; 239 ctlr->menubytes = sizeof(ich7_spi->opmenu); 240 ctlr->optype = &ich7_spi->optype; 241 ctlr->addr = &ich7_spi->spia; 242 ctlr->data = (uint8_t *)ich7_spi->spid; 243 ctlr->databytes = sizeof(ich7_spi->spid); 244 ctlr->status = (uint8_t *)&ich7_spi->spis; 245 ctlr->control = &ich7_spi->spic; 246 ctlr->bbar = &ich7_spi->bbar; 247 ctlr->preop = &ich7_spi->preop; 248 ctlr->base = ich7_spi; 249 } else if (ctlr->ich_version == 9) { 250 struct ich9_spi_regs *ich9_spi; 251 252 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); 253 ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; 254 ctlr->opmenu = ich9_spi->opmenu; 255 ctlr->menubytes = sizeof(ich9_spi->opmenu); 256 ctlr->optype = &ich9_spi->optype; 257 ctlr->addr = &ich9_spi->faddr; 258 ctlr->data = (uint8_t *)ich9_spi->fdata; 259 ctlr->databytes = sizeof(ich9_spi->fdata); 260 ctlr->status = &ich9_spi->ssfs; 261 ctlr->control = (uint16_t *)ich9_spi->ssfc; 262 ctlr->speed = ich9_spi->ssfc + 2; 263 ctlr->bbar = &ich9_spi->bbar; 264 ctlr->preop = &ich9_spi->preop; 265 ctlr->pr = &ich9_spi->pr[0]; 266 ctlr->base = ich9_spi; 267 } else { 268 debug("ICH SPI: Unrecognized ICH version %d.\n", 269 ctlr->ich_version); 270 return -1; 271 } 272 debug("ICH SPI: Version %d detected\n", ctlr->ich_version); 273 274 /* Work out the maximum speed we can support */ 275 ctlr->max_speed = 20000000; 276 if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev)) 277 ctlr->max_speed = 33000000; 278 279 ich_set_bbar(ctlr, 0); 280 281 return 0; 282 } 283 284 void spi_init(void) 285 { 286 uint8_t bios_cntl; 287 288 if (ich_find_spi_controller(&ctlr.dev, &ctlr.ich_version)) { 289 printf("ICH SPI: Cannot find device\n"); 290 return; 291 } 292 293 if (ich_init_controller(&ctlr)) { 294 printf("ICH SPI: Cannot setup controller\n"); 295 return; 296 } 297 298 /* 299 * Disable the BIOS write protect so write commands are allowed. On 300 * v9, deassert SMM BIOS Write Protect Disable. 301 */ 302 pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl); 303 if (ctlr.ich_version == 9) 304 bios_cntl &= ~(1 << 5); 305 pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1); 306 } 307 308 int spi_claim_bus(struct spi_slave *slave) 309 { 310 /* Handled by ICH automatically. */ 311 return 0; 312 } 313 314 void spi_release_bus(struct spi_slave *slave) 315 { 316 /* Handled by ICH automatically. */ 317 } 318 319 void spi_cs_activate(struct spi_slave *slave) 320 { 321 /* Handled by ICH automatically. */ 322 } 323 324 void spi_cs_deactivate(struct spi_slave *slave) 325 { 326 /* Handled by ICH automatically. */ 327 } 328 329 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) 330 { 331 trans->out += bytes; 332 trans->bytesout -= bytes; 333 } 334 335 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) 336 { 337 trans->in += bytes; 338 trans->bytesin -= bytes; 339 } 340 341 static void spi_setup_type(struct spi_trans *trans, int data_bytes) 342 { 343 trans->type = 0xFF; 344 345 /* Try to guess spi type from read/write sizes. */ 346 if (trans->bytesin == 0) { 347 if (trans->bytesout + data_bytes > 4) 348 /* 349 * If bytesin = 0 and bytesout > 4, we presume this is 350 * a write data operation, which is accompanied by an 351 * address. 352 */ 353 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; 354 else 355 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; 356 return; 357 } 358 359 if (trans->bytesout == 1) { /* and bytesin is > 0 */ 360 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; 361 return; 362 } 363 364 if (trans->bytesout == 4) /* and bytesin is > 0 */ 365 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 366 367 /* Fast read command is called with 5 bytes instead of 4 */ 368 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { 369 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 370 --trans->bytesout; 371 } 372 } 373 374 static int spi_setup_opcode(struct spi_trans *trans) 375 { 376 uint16_t optypes; 377 uint8_t opmenu[ctlr.menubytes]; 378 379 trans->opcode = trans->out[0]; 380 spi_use_out(trans, 1); 381 if (!ctlr.ichspi_lock) { 382 /* The lock is off, so just use index 0. */ 383 ich_writeb(trans->opcode, ctlr.opmenu); 384 optypes = ich_readw(ctlr.optype); 385 optypes = (optypes & 0xfffc) | (trans->type & 0x3); 386 ich_writew(optypes, ctlr.optype); 387 return 0; 388 } else { 389 /* The lock is on. See if what we need is on the menu. */ 390 uint8_t optype; 391 uint16_t opcode_index; 392 393 /* Write Enable is handled as atomic prefix */ 394 if (trans->opcode == SPI_OPCODE_WREN) 395 return 0; 396 397 read_reg(ctlr.opmenu, opmenu, sizeof(opmenu)); 398 for (opcode_index = 0; opcode_index < ctlr.menubytes; 399 opcode_index++) { 400 if (opmenu[opcode_index] == trans->opcode) 401 break; 402 } 403 404 if (opcode_index == ctlr.menubytes) { 405 printf("ICH SPI: Opcode %x not found\n", 406 trans->opcode); 407 return -1; 408 } 409 410 optypes = ich_readw(ctlr.optype); 411 optype = (optypes >> (opcode_index * 2)) & 0x3; 412 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && 413 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && 414 trans->bytesout >= 3) { 415 /* We guessed wrong earlier. Fix it up. */ 416 trans->type = optype; 417 } 418 if (optype != trans->type) { 419 printf("ICH SPI: Transaction doesn't fit type %d\n", 420 optype); 421 return -1; 422 } 423 return opcode_index; 424 } 425 } 426 427 static int spi_setup_offset(struct spi_trans *trans) 428 { 429 /* Separate the SPI address and data. */ 430 switch (trans->type) { 431 case SPI_OPCODE_TYPE_READ_NO_ADDRESS: 432 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: 433 return 0; 434 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: 435 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: 436 trans->offset = ((uint32_t)trans->out[0] << 16) | 437 ((uint32_t)trans->out[1] << 8) | 438 ((uint32_t)trans->out[2] << 0); 439 spi_use_out(trans, 3); 440 return 1; 441 default: 442 printf("Unrecognized SPI transaction type %#x\n", trans->type); 443 return -1; 444 } 445 } 446 447 /* 448 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set 449 * below is true) or 0. In case the wait was for the bit(s) to set - write 450 * those bits back, which would cause resetting them. 451 * 452 * Return the last read status value on success or -1 on failure. 453 */ 454 static int ich_status_poll(u16 bitmask, int wait_til_set) 455 { 456 int timeout = 600000; /* This will result in 6s */ 457 u16 status = 0; 458 459 while (timeout--) { 460 status = ich_readw(ctlr.status); 461 if (wait_til_set ^ ((status & bitmask) == 0)) { 462 if (wait_til_set) 463 ich_writew((status & bitmask), ctlr.status); 464 return status; 465 } 466 udelay(10); 467 } 468 469 printf("ICH SPI: SCIP timeout, read %x, expected %x\n", 470 status, bitmask); 471 return -1; 472 } 473 474 /* 475 int spi_xfer(struct spi_slave *slave, const void *dout, 476 unsigned int bitsout, void *din, unsigned int bitsin) 477 */ 478 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 479 void *din, unsigned long flags) 480 { 481 struct ich_spi_slave *ich = to_ich_spi(slave); 482 uint16_t control; 483 int16_t opcode_index; 484 int with_address; 485 int status; 486 int bytes = bitlen / 8; 487 struct spi_trans *trans = &ich->trans; 488 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); 489 int using_cmd = 0; 490 491 /* Ee don't support writing partial bytes. */ 492 if (bitlen % 8) { 493 debug("ICH SPI: Accessing partial bytes not supported\n"); 494 return -1; 495 } 496 497 /* An empty end transaction can be ignored */ 498 if (type == SPI_XFER_END && !dout && !din) 499 return 0; 500 501 if (type & SPI_XFER_BEGIN) 502 memset(trans, '\0', sizeof(*trans)); 503 504 /* Dp we need to come back later to finish it? */ 505 if (dout && type == SPI_XFER_BEGIN) { 506 if (bytes > ICH_MAX_CMD_LEN) { 507 debug("ICH SPI: Command length limit exceeded\n"); 508 return -1; 509 } 510 memcpy(trans->cmd, dout, bytes); 511 trans->cmd_len = bytes; 512 debug("ICH SPI: Saved %d bytes\n", bytes); 513 return 0; 514 } 515 516 /* 517 * We process a 'middle' spi_xfer() call, which has no 518 * SPI_XFER_BEGIN/END, as an independent transaction as if it had 519 * an end. We therefore repeat the command. This is because ICH 520 * seems to have no support for this, or because interest (in digging 521 * out the details and creating a special case in the code) is low. 522 */ 523 if (trans->cmd_len) { 524 trans->out = trans->cmd; 525 trans->bytesout = trans->cmd_len; 526 using_cmd = 1; 527 debug("ICH SPI: Using %d bytes\n", trans->cmd_len); 528 } else { 529 trans->out = dout; 530 trans->bytesout = dout ? bytes : 0; 531 } 532 533 trans->in = din; 534 trans->bytesin = din ? bytes : 0; 535 536 /* There has to always at least be an opcode. */ 537 if (!trans->bytesout) { 538 debug("ICH SPI: No opcode for transfer\n"); 539 return -1; 540 } 541 542 if (ich_status_poll(SPIS_SCIP, 0) == -1) 543 return -1; 544 545 ich_writew(SPIS_CDS | SPIS_FCERR, ctlr.status); 546 547 spi_setup_type(trans, using_cmd ? bytes : 0); 548 opcode_index = spi_setup_opcode(trans); 549 if (opcode_index < 0) 550 return -1; 551 with_address = spi_setup_offset(trans); 552 if (with_address < 0) 553 return -1; 554 555 if (trans->opcode == SPI_OPCODE_WREN) { 556 /* 557 * Treat Write Enable as Atomic Pre-Op if possible 558 * in order to prevent the Management Engine from 559 * issuing a transaction between WREN and DATA. 560 */ 561 if (!ctlr.ichspi_lock) 562 ich_writew(trans->opcode, ctlr.preop); 563 return 0; 564 } 565 566 if (ctlr.speed && ctlr.max_speed >= 33000000) { 567 int byte; 568 569 byte = ich_readb(ctlr.speed); 570 if (ich->speed >= 33000000) 571 byte |= SSFC_SCF_33MHZ; 572 else 573 byte &= ~SSFC_SCF_33MHZ; 574 ich_writeb(byte, ctlr.speed); 575 } 576 577 /* See if we have used up the command data */ 578 if (using_cmd && dout && bytes) { 579 trans->out = dout; 580 trans->bytesout = bytes; 581 debug("ICH SPI: Moving to data, %d bytes\n", bytes); 582 } 583 584 /* Preset control fields */ 585 control = ich_readw(ctlr.control); 586 control &= ~SSFC_RESERVED; 587 control = SPIC_SCGO | ((opcode_index & 0x07) << 4); 588 589 /* Issue atomic preop cycle if needed */ 590 if (ich_readw(ctlr.preop)) 591 control |= SPIC_ACS; 592 593 if (!trans->bytesout && !trans->bytesin) { 594 /* SPI addresses are 24 bit only */ 595 if (with_address) 596 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); 597 598 /* 599 * This is a 'no data' command (like Write Enable), its 600 * bitesout size was 1, decremented to zero while executing 601 * spi_setup_opcode() above. Tell the chip to send the 602 * command. 603 */ 604 ich_writew(control, ctlr.control); 605 606 /* wait for the result */ 607 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); 608 if (status == -1) 609 return -1; 610 611 if (status & SPIS_FCERR) { 612 debug("ICH SPI: Command transaction error\n"); 613 return -1; 614 } 615 616 return 0; 617 } 618 619 /* 620 * Check if this is a write command atempting to transfer more bytes 621 * than the controller can handle. Iterations for writes are not 622 * supported here because each SPI write command needs to be preceded 623 * and followed by other SPI commands, and this sequence is controlled 624 * by the SPI chip driver. 625 */ 626 if (trans->bytesout > ctlr.databytes) { 627 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); 628 return -1; 629 } 630 631 /* 632 * Read or write up to databytes bytes at a time until everything has 633 * been sent. 634 */ 635 while (trans->bytesout || trans->bytesin) { 636 uint32_t data_length; 637 638 /* SPI addresses are 24 bit only */ 639 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); 640 641 if (trans->bytesout) 642 data_length = min(trans->bytesout, ctlr.databytes); 643 else 644 data_length = min(trans->bytesin, ctlr.databytes); 645 646 /* Program data into FDATA0 to N */ 647 if (trans->bytesout) { 648 write_reg(trans->out, ctlr.data, data_length); 649 spi_use_out(trans, data_length); 650 if (with_address) 651 trans->offset += data_length; 652 } 653 654 /* Add proper control fields' values */ 655 control &= ~((ctlr.databytes - 1) << 8); 656 control |= SPIC_DS; 657 control |= (data_length - 1) << 8; 658 659 /* write it */ 660 ich_writew(control, ctlr.control); 661 662 /* Wait for Cycle Done Status or Flash Cycle Error. */ 663 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); 664 if (status == -1) 665 return -1; 666 667 if (status & SPIS_FCERR) { 668 debug("ICH SPI: Data transaction error\n"); 669 return -1; 670 } 671 672 if (trans->bytesin) { 673 read_reg(ctlr.data, trans->in, data_length); 674 spi_use_in(trans, data_length); 675 if (with_address) 676 trans->offset += data_length; 677 } 678 } 679 680 /* Clear atomic preop now that xfer is done */ 681 ich_writew(0, ctlr.preop); 682 683 return 0; 684 } 685 686 687 /* 688 * This uses the SPI controller from the Intel Cougar Point and Panther Point 689 * PCH to write-protect portions of the SPI flash until reboot. The changes 690 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's 691 * done elsewhere. 692 */ 693 int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint) 694 { 695 uint32_t tmplong; 696 uint32_t upper_limit; 697 698 if (!ctlr.pr) { 699 printf("%s: operation not supported on this chipset\n", 700 __func__); 701 return -1; 702 } 703 704 if (length == 0 || 705 lower_limit > (0xFFFFFFFFUL - length) + 1 || 706 hint < 0 || hint > 4) { 707 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, 708 lower_limit, length, hint); 709 return -1; 710 } 711 712 upper_limit = lower_limit + length - 1; 713 714 /* 715 * Determine bits to write, as follows: 716 * 31 Write-protection enable (includes erase operation) 717 * 30:29 reserved 718 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) 719 * 15 Read-protection enable 720 * 14:13 reserved 721 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) 722 */ 723 tmplong = 0x80000000 | 724 ((upper_limit & 0x01fff000) << 4) | 725 ((lower_limit & 0x01fff000) >> 12); 726 727 printf("%s: writing 0x%08x to %p\n", __func__, tmplong, 728 &ctlr.pr[hint]); 729 ctlr.pr[hint] = tmplong; 730 731 return 0; 732 } 733