1 /* 2 * Copyright (c) 2011-12 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * This file is derived from the flashrom project. 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <spi.h> 12 #include <pci.h> 13 #include <pci_ids.h> 14 #include <asm/io.h> 15 16 #include "ich.h" 17 18 #define SPI_OPCODE_WREN 0x06 19 #define SPI_OPCODE_FAST_READ 0x0b 20 21 struct ich_ctlr { 22 pci_dev_t dev; /* PCI device number */ 23 int ich_version; /* Controller version, 7 or 9 */ 24 int ichspi_lock; 25 int locked; 26 uint8_t *opmenu; 27 int menubytes; 28 void *base; /* Base of register set */ 29 uint16_t *preop; 30 uint16_t *optype; 31 uint32_t *addr; 32 uint8_t *data; 33 unsigned databytes; 34 uint8_t *status; 35 uint16_t *control; 36 uint32_t *bbar; 37 uint32_t *pr; /* only for ich9 */ 38 uint8_t *speed; /* pointer to speed control */ 39 ulong max_speed; /* Maximum bus speed in MHz */ 40 }; 41 42 struct ich_ctlr ctlr; 43 44 static inline struct ich_spi_slave *to_ich_spi(struct spi_slave *slave) 45 { 46 return container_of(slave, struct ich_spi_slave, slave); 47 } 48 49 static unsigned int ich_reg(const void *addr) 50 { 51 return (unsigned)(addr - ctlr.base) & 0xffff; 52 } 53 54 static u8 ich_readb(const void *addr) 55 { 56 u8 value = readb(addr); 57 58 debug("read %2.2x from %4.4x\n", value, ich_reg(addr)); 59 60 return value; 61 } 62 63 static u16 ich_readw(const void *addr) 64 { 65 u16 value = readw(addr); 66 67 debug("read %4.4x from %4.4x\n", value, ich_reg(addr)); 68 69 return value; 70 } 71 72 static u32 ich_readl(const void *addr) 73 { 74 u32 value = readl(addr); 75 76 debug("read %8.8x from %4.4x\n", value, ich_reg(addr)); 77 78 return value; 79 } 80 81 static void ich_writeb(u8 value, void *addr) 82 { 83 writeb(value, addr); 84 debug("wrote %2.2x to %4.4x\n", value, ich_reg(addr)); 85 } 86 87 static void ich_writew(u16 value, void *addr) 88 { 89 writew(value, addr); 90 debug("wrote %4.4x to %4.4x\n", value, ich_reg(addr)); 91 } 92 93 static void ich_writel(u32 value, void *addr) 94 { 95 writel(value, addr); 96 debug("wrote %8.8x to %4.4x\n", value, ich_reg(addr)); 97 } 98 99 static void write_reg(const void *value, void *dest, uint32_t size) 100 { 101 memcpy_toio(dest, value, size); 102 } 103 104 static void read_reg(const void *src, void *value, uint32_t size) 105 { 106 memcpy_fromio(value, src, size); 107 } 108 109 static void ich_set_bbar(struct ich_ctlr *ctlr, uint32_t minaddr) 110 { 111 const uint32_t bbar_mask = 0x00ffff00; 112 uint32_t ichspi_bbar; 113 114 minaddr &= bbar_mask; 115 ichspi_bbar = ich_readl(ctlr->bbar) & ~bbar_mask; 116 ichspi_bbar |= minaddr; 117 ich_writel(ichspi_bbar, ctlr->bbar); 118 } 119 120 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 121 { 122 puts("spi_cs_is_valid used but not implemented\n"); 123 return 0; 124 } 125 126 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 127 unsigned int max_hz, unsigned int mode) 128 { 129 struct ich_spi_slave *ich; 130 131 ich = spi_alloc_slave(struct ich_spi_slave, bus, cs); 132 if (!ich) { 133 puts("ICH SPI: Out of memory\n"); 134 return NULL; 135 } 136 137 /* 138 * Yes this controller can only write a small number of bytes at 139 * once! The limit is typically 64 bytes. 140 */ 141 ich->slave.max_write_size = ctlr.databytes; 142 ich->speed = max_hz; 143 144 /* 145 * ICH 7 SPI controller only supports array read command 146 * and byte program command for SST flash 147 */ 148 if (ctlr.ich_version == 7) { 149 ich->slave.op_mode_rx = SPI_OPM_RX_AS; 150 ich->slave.op_mode_tx = SPI_OPM_TX_BP; 151 } 152 153 return &ich->slave; 154 } 155 156 void spi_free_slave(struct spi_slave *slave) 157 { 158 struct ich_spi_slave *ich = to_ich_spi(slave); 159 160 free(ich); 161 } 162 163 /* 164 * Check if this device ID matches one of supported Intel PCH devices. 165 * 166 * Return the ICH version if there is a match, or zero otherwise. 167 */ 168 static int get_ich_version(uint16_t device_id) 169 { 170 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) 171 return 7; 172 173 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 174 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || 175 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 176 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) 177 return 9; 178 179 return 0; 180 } 181 182 /* @return 1 if the SPI flash supports the 33MHz speed */ 183 static int ich9_can_do_33mhz(pci_dev_t dev) 184 { 185 u32 fdod, speed; 186 187 /* Observe SPI Descriptor Component Section 0 */ 188 pci_write_config_dword(dev, 0xb0, 0x1000); 189 190 /* Extract the Write/Erase SPI Frequency from descriptor */ 191 pci_read_config_dword(dev, 0xb4, &fdod); 192 193 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ 194 speed = (fdod >> 21) & 7; 195 196 return speed == 1; 197 } 198 199 static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp) 200 { 201 int last_bus = pci_last_busno(); 202 int bus; 203 204 if (last_bus == -1) { 205 debug("No PCI busses?\n"); 206 return -1; 207 } 208 209 for (bus = 0; bus <= last_bus; bus++) { 210 uint16_t vendor_id, device_id; 211 uint32_t ids; 212 pci_dev_t dev; 213 214 dev = PCI_BDF(bus, 31, 0); 215 pci_read_config_dword(dev, 0, &ids); 216 vendor_id = ids; 217 device_id = ids >> 16; 218 219 if (vendor_id == PCI_VENDOR_ID_INTEL) { 220 *devp = dev; 221 *ich_versionp = get_ich_version(device_id); 222 return 0; 223 } 224 } 225 226 debug("ICH SPI: No ICH found.\n"); 227 return -1; 228 } 229 230 static int ich_init_controller(struct ich_ctlr *ctlr) 231 { 232 uint8_t *rcrb; /* Root Complex Register Block */ 233 uint32_t rcba; /* Root Complex Base Address */ 234 235 pci_read_config_dword(ctlr->dev, 0xf0, &rcba); 236 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ 237 rcrb = (uint8_t *)(rcba & 0xffffc000); 238 if (ctlr->ich_version == 7) { 239 struct ich7_spi_regs *ich7_spi; 240 241 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); 242 ctlr->ichspi_lock = ich_readw(&ich7_spi->spis) & SPIS_LOCK; 243 ctlr->opmenu = ich7_spi->opmenu; 244 ctlr->menubytes = sizeof(ich7_spi->opmenu); 245 ctlr->optype = &ich7_spi->optype; 246 ctlr->addr = &ich7_spi->spia; 247 ctlr->data = (uint8_t *)ich7_spi->spid; 248 ctlr->databytes = sizeof(ich7_spi->spid); 249 ctlr->status = (uint8_t *)&ich7_spi->spis; 250 ctlr->control = &ich7_spi->spic; 251 ctlr->bbar = &ich7_spi->bbar; 252 ctlr->preop = &ich7_spi->preop; 253 ctlr->base = ich7_spi; 254 } else if (ctlr->ich_version == 9) { 255 struct ich9_spi_regs *ich9_spi; 256 257 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); 258 ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; 259 ctlr->opmenu = ich9_spi->opmenu; 260 ctlr->menubytes = sizeof(ich9_spi->opmenu); 261 ctlr->optype = &ich9_spi->optype; 262 ctlr->addr = &ich9_spi->faddr; 263 ctlr->data = (uint8_t *)ich9_spi->fdata; 264 ctlr->databytes = sizeof(ich9_spi->fdata); 265 ctlr->status = &ich9_spi->ssfs; 266 ctlr->control = (uint16_t *)ich9_spi->ssfc; 267 ctlr->speed = ich9_spi->ssfc + 2; 268 ctlr->bbar = &ich9_spi->bbar; 269 ctlr->preop = &ich9_spi->preop; 270 ctlr->pr = &ich9_spi->pr[0]; 271 ctlr->base = ich9_spi; 272 } else { 273 debug("ICH SPI: Unrecognized ICH version %d.\n", 274 ctlr->ich_version); 275 return -1; 276 } 277 debug("ICH SPI: Version %d detected\n", ctlr->ich_version); 278 279 /* Work out the maximum speed we can support */ 280 ctlr->max_speed = 20000000; 281 if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev)) 282 ctlr->max_speed = 33000000; 283 284 ich_set_bbar(ctlr, 0); 285 286 return 0; 287 } 288 289 void spi_init(void) 290 { 291 uint8_t bios_cntl; 292 293 if (ich_find_spi_controller(&ctlr.dev, &ctlr.ich_version)) { 294 printf("ICH SPI: Cannot find device\n"); 295 return; 296 } 297 298 if (ich_init_controller(&ctlr)) { 299 printf("ICH SPI: Cannot setup controller\n"); 300 return; 301 } 302 303 /* 304 * Disable the BIOS write protect so write commands are allowed. On 305 * v9, deassert SMM BIOS Write Protect Disable. 306 */ 307 pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl); 308 if (ctlr.ich_version == 9) 309 bios_cntl &= ~(1 << 5); 310 pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1); 311 } 312 313 int spi_claim_bus(struct spi_slave *slave) 314 { 315 /* Handled by ICH automatically. */ 316 return 0; 317 } 318 319 void spi_release_bus(struct spi_slave *slave) 320 { 321 /* Handled by ICH automatically. */ 322 } 323 324 void spi_cs_activate(struct spi_slave *slave) 325 { 326 /* Handled by ICH automatically. */ 327 } 328 329 void spi_cs_deactivate(struct spi_slave *slave) 330 { 331 /* Handled by ICH automatically. */ 332 } 333 334 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) 335 { 336 trans->out += bytes; 337 trans->bytesout -= bytes; 338 } 339 340 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) 341 { 342 trans->in += bytes; 343 trans->bytesin -= bytes; 344 } 345 346 static void spi_setup_type(struct spi_trans *trans, int data_bytes) 347 { 348 trans->type = 0xFF; 349 350 /* Try to guess spi type from read/write sizes. */ 351 if (trans->bytesin == 0) { 352 if (trans->bytesout + data_bytes > 4) 353 /* 354 * If bytesin = 0 and bytesout > 4, we presume this is 355 * a write data operation, which is accompanied by an 356 * address. 357 */ 358 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; 359 else 360 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; 361 return; 362 } 363 364 if (trans->bytesout == 1) { /* and bytesin is > 0 */ 365 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; 366 return; 367 } 368 369 if (trans->bytesout == 4) /* and bytesin is > 0 */ 370 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 371 372 /* Fast read command is called with 5 bytes instead of 4 */ 373 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { 374 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 375 --trans->bytesout; 376 } 377 } 378 379 static int spi_setup_opcode(struct spi_trans *trans) 380 { 381 uint16_t optypes; 382 uint8_t opmenu[ctlr.menubytes]; 383 384 trans->opcode = trans->out[0]; 385 spi_use_out(trans, 1); 386 if (!ctlr.ichspi_lock) { 387 /* The lock is off, so just use index 0. */ 388 ich_writeb(trans->opcode, ctlr.opmenu); 389 optypes = ich_readw(ctlr.optype); 390 optypes = (optypes & 0xfffc) | (trans->type & 0x3); 391 ich_writew(optypes, ctlr.optype); 392 return 0; 393 } else { 394 /* The lock is on. See if what we need is on the menu. */ 395 uint8_t optype; 396 uint16_t opcode_index; 397 398 /* Write Enable is handled as atomic prefix */ 399 if (trans->opcode == SPI_OPCODE_WREN) 400 return 0; 401 402 read_reg(ctlr.opmenu, opmenu, sizeof(opmenu)); 403 for (opcode_index = 0; opcode_index < ctlr.menubytes; 404 opcode_index++) { 405 if (opmenu[opcode_index] == trans->opcode) 406 break; 407 } 408 409 if (opcode_index == ctlr.menubytes) { 410 printf("ICH SPI: Opcode %x not found\n", 411 trans->opcode); 412 return -1; 413 } 414 415 optypes = ich_readw(ctlr.optype); 416 optype = (optypes >> (opcode_index * 2)) & 0x3; 417 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && 418 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && 419 trans->bytesout >= 3) { 420 /* We guessed wrong earlier. Fix it up. */ 421 trans->type = optype; 422 } 423 if (optype != trans->type) { 424 printf("ICH SPI: Transaction doesn't fit type %d\n", 425 optype); 426 return -1; 427 } 428 return opcode_index; 429 } 430 } 431 432 static int spi_setup_offset(struct spi_trans *trans) 433 { 434 /* Separate the SPI address and data. */ 435 switch (trans->type) { 436 case SPI_OPCODE_TYPE_READ_NO_ADDRESS: 437 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: 438 return 0; 439 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: 440 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: 441 trans->offset = ((uint32_t)trans->out[0] << 16) | 442 ((uint32_t)trans->out[1] << 8) | 443 ((uint32_t)trans->out[2] << 0); 444 spi_use_out(trans, 3); 445 return 1; 446 default: 447 printf("Unrecognized SPI transaction type %#x\n", trans->type); 448 return -1; 449 } 450 } 451 452 /* 453 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set 454 * below is true) or 0. In case the wait was for the bit(s) to set - write 455 * those bits back, which would cause resetting them. 456 * 457 * Return the last read status value on success or -1 on failure. 458 */ 459 static int ich_status_poll(u16 bitmask, int wait_til_set) 460 { 461 int timeout = 600000; /* This will result in 6s */ 462 u16 status = 0; 463 464 while (timeout--) { 465 status = ich_readw(ctlr.status); 466 if (wait_til_set ^ ((status & bitmask) == 0)) { 467 if (wait_til_set) 468 ich_writew((status & bitmask), ctlr.status); 469 return status; 470 } 471 udelay(10); 472 } 473 474 printf("ICH SPI: SCIP timeout, read %x, expected %x\n", 475 status, bitmask); 476 return -1; 477 } 478 479 /* 480 int spi_xfer(struct spi_slave *slave, const void *dout, 481 unsigned int bitsout, void *din, unsigned int bitsin) 482 */ 483 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 484 void *din, unsigned long flags) 485 { 486 struct ich_spi_slave *ich = to_ich_spi(slave); 487 uint16_t control; 488 int16_t opcode_index; 489 int with_address; 490 int status; 491 int bytes = bitlen / 8; 492 struct spi_trans *trans = &ich->trans; 493 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); 494 int using_cmd = 0; 495 496 /* Ee don't support writing partial bytes. */ 497 if (bitlen % 8) { 498 debug("ICH SPI: Accessing partial bytes not supported\n"); 499 return -1; 500 } 501 502 /* An empty end transaction can be ignored */ 503 if (type == SPI_XFER_END && !dout && !din) 504 return 0; 505 506 if (type & SPI_XFER_BEGIN) 507 memset(trans, '\0', sizeof(*trans)); 508 509 /* Dp we need to come back later to finish it? */ 510 if (dout && type == SPI_XFER_BEGIN) { 511 if (bytes > ICH_MAX_CMD_LEN) { 512 debug("ICH SPI: Command length limit exceeded\n"); 513 return -1; 514 } 515 memcpy(trans->cmd, dout, bytes); 516 trans->cmd_len = bytes; 517 debug("ICH SPI: Saved %d bytes\n", bytes); 518 return 0; 519 } 520 521 /* 522 * We process a 'middle' spi_xfer() call, which has no 523 * SPI_XFER_BEGIN/END, as an independent transaction as if it had 524 * an end. We therefore repeat the command. This is because ICH 525 * seems to have no support for this, or because interest (in digging 526 * out the details and creating a special case in the code) is low. 527 */ 528 if (trans->cmd_len) { 529 trans->out = trans->cmd; 530 trans->bytesout = trans->cmd_len; 531 using_cmd = 1; 532 debug("ICH SPI: Using %d bytes\n", trans->cmd_len); 533 } else { 534 trans->out = dout; 535 trans->bytesout = dout ? bytes : 0; 536 } 537 538 trans->in = din; 539 trans->bytesin = din ? bytes : 0; 540 541 /* There has to always at least be an opcode. */ 542 if (!trans->bytesout) { 543 debug("ICH SPI: No opcode for transfer\n"); 544 return -1; 545 } 546 547 if (ich_status_poll(SPIS_SCIP, 0) == -1) 548 return -1; 549 550 ich_writew(SPIS_CDS | SPIS_FCERR, ctlr.status); 551 552 spi_setup_type(trans, using_cmd ? bytes : 0); 553 opcode_index = spi_setup_opcode(trans); 554 if (opcode_index < 0) 555 return -1; 556 with_address = spi_setup_offset(trans); 557 if (with_address < 0) 558 return -1; 559 560 if (trans->opcode == SPI_OPCODE_WREN) { 561 /* 562 * Treat Write Enable as Atomic Pre-Op if possible 563 * in order to prevent the Management Engine from 564 * issuing a transaction between WREN and DATA. 565 */ 566 if (!ctlr.ichspi_lock) 567 ich_writew(trans->opcode, ctlr.preop); 568 return 0; 569 } 570 571 if (ctlr.speed && ctlr.max_speed >= 33000000) { 572 int byte; 573 574 byte = ich_readb(ctlr.speed); 575 if (ich->speed >= 33000000) 576 byte |= SSFC_SCF_33MHZ; 577 else 578 byte &= ~SSFC_SCF_33MHZ; 579 ich_writeb(byte, ctlr.speed); 580 } 581 582 /* See if we have used up the command data */ 583 if (using_cmd && dout && bytes) { 584 trans->out = dout; 585 trans->bytesout = bytes; 586 debug("ICH SPI: Moving to data, %d bytes\n", bytes); 587 } 588 589 /* Preset control fields */ 590 control = ich_readw(ctlr.control); 591 control &= ~SSFC_RESERVED; 592 control = SPIC_SCGO | ((opcode_index & 0x07) << 4); 593 594 /* Issue atomic preop cycle if needed */ 595 if (ich_readw(ctlr.preop)) 596 control |= SPIC_ACS; 597 598 if (!trans->bytesout && !trans->bytesin) { 599 /* SPI addresses are 24 bit only */ 600 if (with_address) 601 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); 602 603 /* 604 * This is a 'no data' command (like Write Enable), its 605 * bitesout size was 1, decremented to zero while executing 606 * spi_setup_opcode() above. Tell the chip to send the 607 * command. 608 */ 609 ich_writew(control, ctlr.control); 610 611 /* wait for the result */ 612 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); 613 if (status == -1) 614 return -1; 615 616 if (status & SPIS_FCERR) { 617 debug("ICH SPI: Command transaction error\n"); 618 return -1; 619 } 620 621 return 0; 622 } 623 624 /* 625 * Check if this is a write command atempting to transfer more bytes 626 * than the controller can handle. Iterations for writes are not 627 * supported here because each SPI write command needs to be preceded 628 * and followed by other SPI commands, and this sequence is controlled 629 * by the SPI chip driver. 630 */ 631 if (trans->bytesout > ctlr.databytes) { 632 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); 633 return -1; 634 } 635 636 /* 637 * Read or write up to databytes bytes at a time until everything has 638 * been sent. 639 */ 640 while (trans->bytesout || trans->bytesin) { 641 uint32_t data_length; 642 643 /* SPI addresses are 24 bit only */ 644 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); 645 646 if (trans->bytesout) 647 data_length = min(trans->bytesout, ctlr.databytes); 648 else 649 data_length = min(trans->bytesin, ctlr.databytes); 650 651 /* Program data into FDATA0 to N */ 652 if (trans->bytesout) { 653 write_reg(trans->out, ctlr.data, data_length); 654 spi_use_out(trans, data_length); 655 if (with_address) 656 trans->offset += data_length; 657 } 658 659 /* Add proper control fields' values */ 660 control &= ~((ctlr.databytes - 1) << 8); 661 control |= SPIC_DS; 662 control |= (data_length - 1) << 8; 663 664 /* write it */ 665 ich_writew(control, ctlr.control); 666 667 /* Wait for Cycle Done Status or Flash Cycle Error. */ 668 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); 669 if (status == -1) 670 return -1; 671 672 if (status & SPIS_FCERR) { 673 debug("ICH SPI: Data transaction error\n"); 674 return -1; 675 } 676 677 if (trans->bytesin) { 678 read_reg(ctlr.data, trans->in, data_length); 679 spi_use_in(trans, data_length); 680 if (with_address) 681 trans->offset += data_length; 682 } 683 } 684 685 /* Clear atomic preop now that xfer is done */ 686 ich_writew(0, ctlr.preop); 687 688 return 0; 689 } 690 691 692 /* 693 * This uses the SPI controller from the Intel Cougar Point and Panther Point 694 * PCH to write-protect portions of the SPI flash until reboot. The changes 695 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's 696 * done elsewhere. 697 */ 698 int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint) 699 { 700 uint32_t tmplong; 701 uint32_t upper_limit; 702 703 if (!ctlr.pr) { 704 printf("%s: operation not supported on this chipset\n", 705 __func__); 706 return -1; 707 } 708 709 if (length == 0 || 710 lower_limit > (0xFFFFFFFFUL - length) + 1 || 711 hint < 0 || hint > 4) { 712 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, 713 lower_limit, length, hint); 714 return -1; 715 } 716 717 upper_limit = lower_limit + length - 1; 718 719 /* 720 * Determine bits to write, as follows: 721 * 31 Write-protection enable (includes erase operation) 722 * 30:29 reserved 723 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) 724 * 15 Read-protection enable 725 * 14:13 reserved 726 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) 727 */ 728 tmplong = 0x80000000 | 729 ((upper_limit & 0x01fff000) << 4) | 730 ((lower_limit & 0x01fff000) >> 12); 731 732 printf("%s: writing 0x%08x to %p\n", __func__, tmplong, 733 &ctlr.pr[hint]); 734 ctlr.pr[hint] = tmplong; 735 736 return 0; 737 } 738