1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip USB2.0 PHY with Naneng IP block driver 4 * 5 * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <dm/lists.h> 11 #include <generic-phy.h> 12 #include <syscon.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #include <reset-uclass.h> 16 #include <power/regulator.h> 17 18 #define U2PHY_BIT_WRITEABLE_SHIFT 16 19 20 struct rockchip_usb2phy; 21 22 enum power_supply_type { 23 POWER_SUPPLY_TYPE_UNKNOWN = 0, 24 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 25 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 26 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 27 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 28 }; 29 30 enum rockchip_usb2phy_port_id { 31 USB2PHY_PORT_OTG, 32 USB2PHY_PORT_HOST, 33 USB2PHY_NUM_PORTS, 34 }; 35 36 struct usb2phy_reg { 37 u32 offset; 38 u32 bitend; 39 u32 bitstart; 40 u32 disable; 41 u32 enable; 42 }; 43 44 /** 45 * struct rockchip_chg_det_reg: usb charger detect registers 46 * @chg_valid: charge valid signal. 47 * @phy_connect: PHY start handshake signal. 48 * @chg_en: charge detector enable signal. 49 * @chg_rst: charge detector reset signal, active high. 50 */ 51 struct rockchip_chg_det_reg { 52 struct usb2phy_reg chg_valid; 53 struct usb2phy_reg phy_connect; 54 struct usb2phy_reg chg_en; 55 struct usb2phy_reg chg_rst; 56 }; 57 58 /** 59 * struct rockchip_usb2phy_port_cfg: usb phy port configuration. 60 * @bypass_otgsuspendm: otg-suspendm bypass control register. 61 * 0: iddig; 1: grf. 62 * @bvalidfall_det_en: vbus valid fall detection enable register. 63 * @bvalidfall_det_st: vbus valid fall detection status register. 64 * @bvalidfall_det_clr: vbus valid fall detection clear register. 65 * @bvalidrise_det_en: vbus valid rise detection enable register. 66 * @bvalidrise_det_st: vbus valid rise detection status register. 67 * @bvalidrise_det_clr: vbus valid rise detection clear register. 68 * @disconfall_det_en: host connect detection enable register. 69 * @disconfall_det_st: host connect detection status register. 70 * @disconfall_det_clr: host connect detection clear register. 71 * @disconrise_det_en: host disconnect detection enable register. 72 * @disconrise_det_st: host disconnect detection status register. 73 * @disconrise_det_clr: host disconnect detection clear register. 74 * @idfall_det_en: id fall detection enable register. 75 * @idfall_det_st: id fall detection state register. 76 * @idfall_det_clr: id fall detection clear register. 77 * @idpullup: id pin pullup or pulldown control register. 78 * @idrise_det_en: id rise detection enable register. 79 * @idrise_det_st: id rise detection state register. 80 * @idrise_det_clr: id rise detection clear register. 81 * @ls_det_en: linestate detection enable register. 82 * @ls_det_st: linestate detection state register. 83 * @ls_det_clr: linestate detection clear register. 84 * @phy_sus: phy suspend register. 85 * @utmi_bvalid: utmi vbus bvalid status register. 86 * @utmi_iddig: otg port id pin status register. 87 * @utmi_hostdet: utmi host disconnect status register. 88 */ 89 struct rockchip_usb2phy_port_cfg { 90 struct usb2phy_reg bypass_otgsuspendm; 91 struct usb2phy_reg bvalidfall_det_en; 92 struct usb2phy_reg bvalidfall_det_st; 93 struct usb2phy_reg bvalidfall_det_clr; 94 struct usb2phy_reg bvalidrise_det_en; 95 struct usb2phy_reg bvalidrise_det_st; 96 struct usb2phy_reg bvalidrise_det_clr; 97 struct usb2phy_reg disconfall_det_en; 98 struct usb2phy_reg disconfall_det_st; 99 struct usb2phy_reg disconfall_det_clr; 100 struct usb2phy_reg disconrise_det_en; 101 struct usb2phy_reg disconrise_det_st; 102 struct usb2phy_reg disconrise_det_clr; 103 struct usb2phy_reg idfall_det_en; 104 struct usb2phy_reg idfall_det_st; 105 struct usb2phy_reg idfall_det_clr; 106 struct usb2phy_reg idpullup; 107 struct usb2phy_reg idrise_det_en; 108 struct usb2phy_reg idrise_det_st; 109 struct usb2phy_reg idrise_det_clr; 110 struct usb2phy_reg ls_det_en; 111 struct usb2phy_reg ls_det_st; 112 struct usb2phy_reg ls_det_clr; 113 struct usb2phy_reg phy_sus; 114 struct usb2phy_reg utmi_bvalid; 115 struct usb2phy_reg utmi_iddig; 116 struct usb2phy_reg utmi_hostdet; 117 }; 118 119 /** 120 * struct rockchip_usb2phy_cfg: usb phy configuration. 121 * @reg: the address offset of grf for usb-phy config. 122 * @num_ports: specify how many ports that the phy has. 123 * @phy_tuning: phy default parameters tuning. 124 * @clkout_ctl: keep on/turn off output clk of phy. 125 * @port_cfgs: ports register configuration, assigned by driver data. 126 * @chg_det: charger detection registers. 127 * @last: indicate the last one. 128 */ 129 struct rockchip_usb2phy_cfg { 130 unsigned int reg; 131 unsigned int num_ports; 132 int (*phy_tuning)(struct rockchip_usb2phy *rphy); 133 struct usb2phy_reg clkout_ctl; 134 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 135 const struct rockchip_chg_det_reg chg_det; 136 bool last; 137 }; 138 139 /** 140 * struct rockchip_usb2phy: usb2.0 phy driver data. 141 * @grf: General Register Files register base. 142 * @reset: power reset signal for phy. 143 * @vbus_supply: vbus supply for usb host. 144 * @phy_cfg: phy register configuration, assigned by driver data. 145 */ 146 struct rockchip_usb2phy { 147 void __iomem *grf; 148 struct reset_ctl *reset; 149 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 150 const struct rockchip_usb2phy_cfg *phy_cfg; 151 }; 152 153 static inline int property_enable(void __iomem *base, 154 const struct usb2phy_reg *reg, bool en) 155 { 156 u32 val, mask, tmp; 157 158 tmp = en ? reg->enable : reg->disable; 159 mask = GENMASK(reg->bitend, reg->bitstart); 160 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 161 162 writel(val, base + reg->offset); 163 164 return 0; 165 } 166 167 static inline bool property_enabled(void __iomem *base, 168 const struct usb2phy_reg *reg) 169 { 170 u32 tmp, orig; 171 u32 mask = GENMASK(reg->bitend, reg->bitstart); 172 173 orig = readl(base + reg->offset); 174 175 tmp = (orig & mask) >> reg->bitstart; 176 177 return tmp == reg->enable; 178 } 179 180 static const char *chg_to_string(enum power_supply_type chg_type) 181 { 182 switch (chg_type) { 183 case POWER_SUPPLY_TYPE_USB: 184 return "USB_SDP_CHARGER"; 185 case POWER_SUPPLY_TYPE_USB_DCP: 186 return "USB_DCP_CHARGER"; 187 case POWER_SUPPLY_TYPE_USB_CDP: 188 return "USB_CDP_CHARGER"; 189 case POWER_SUPPLY_TYPE_USB_FLOATING: 190 return "USB_FLOATING_CHARGER"; 191 default: 192 return "INVALID_CHARGER"; 193 } 194 } 195 196 int rockchip_chg_get_type(void) 197 { 198 const struct rockchip_usb2phy_port_cfg *port_cfg; 199 enum power_supply_type chg_type; 200 struct rockchip_usb2phy *rphy; 201 struct udevice *udev; 202 bool chg_valid, phy_connect; 203 int cnt; 204 int ret; 205 206 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 207 if (ret == -ENODEV) { 208 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 209 return ret; 210 } 211 212 rphy = dev_get_priv(udev); 213 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 214 215 /* Check USB-Vbus status first */ 216 if (!property_enabled(rphy->grf, &port_cfg->utmi_bvalid)) { 217 pr_info("%s: no charger found\n", __func__); 218 return POWER_SUPPLY_TYPE_UNKNOWN; 219 } 220 221 reset_assert(rphy->reset); 222 223 /* CHG_RST is set to 1'b0 to start charge detection */ 224 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, true); 225 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, false); 226 227 for (cnt = 0; cnt < 12; cnt++) { 228 mdelay(100); 229 230 chg_valid = property_enabled(rphy->grf, 231 &rphy->phy_cfg->chg_det.chg_valid); 232 phy_connect = 233 property_enabled(rphy->grf, 234 &rphy->phy_cfg->chg_det.phy_connect); 235 chg_type = (chg_valid << 1) | phy_connect; 236 237 if (chg_type) 238 goto compeleted; 239 } 240 241 compeleted: 242 debug("charger = %s\n", chg_to_string(chg_type)); 243 244 mdelay(1); 245 reset_deassert(rphy->reset); 246 /* disable the chg detection module */ 247 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, true); 248 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, false); 249 250 return chg_type; 251 } 252 253 int rockchip_u2phy_vbus_detect(void) 254 { 255 int chg_type; 256 257 chg_type = rockchip_chg_get_type(); 258 259 return (chg_type == POWER_SUPPLY_TYPE_USB || 260 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 261 } 262 263 static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy) 264 { 265 struct udevice *parent = phy->dev->parent; 266 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 267 const struct rockchip_usb2phy_port_cfg *port_cfg; 268 void __iomem *base = rphy->grf; 269 struct udevice *vbus = NULL; 270 bool iddig = true; 271 272 if (phy->id == USB2PHY_PORT_HOST) { 273 vbus = rphy->vbus_supply[USB2PHY_PORT_HOST]; 274 } else if (phy->id == USB2PHY_PORT_OTG) { 275 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 276 if (port_cfg->utmi_iddig.offset) { 277 iddig = property_enabled(base, &port_cfg->utmi_iddig); 278 if (!iddig) 279 vbus = rphy->vbus_supply[USB2PHY_PORT_OTG]; 280 } 281 } 282 283 return vbus; 284 } 285 286 static int rockchip_usb2phy_init(struct phy *phy) 287 { 288 struct udevice *parent = phy->dev->parent; 289 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 290 const struct rockchip_usb2phy_port_cfg *port_cfg; 291 292 if (phy->id == USB2PHY_PORT_OTG) { 293 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 294 } else if (phy->id == USB2PHY_PORT_HOST) { 295 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 296 } else { 297 dev_err(phy->dev, "phy id %lu not support", phy->id); 298 return -EINVAL; 299 } 300 301 property_enable(rphy->grf, &port_cfg->phy_sus, false); 302 303 /* waiting for the utmi_clk to become stable */ 304 udelay(2000); 305 306 return 0; 307 } 308 309 static int rockchip_usb2phy_exit(struct phy *phy) 310 { 311 struct udevice *parent = phy->dev->parent; 312 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 313 const struct rockchip_usb2phy_port_cfg *port_cfg; 314 315 if (phy->id == USB2PHY_PORT_OTG) { 316 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 317 } else if (phy->id == USB2PHY_PORT_HOST) { 318 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 319 } else { 320 dev_err(phy->dev, "phy id %lu not support", phy->id); 321 return -EINVAL; 322 } 323 324 property_enable(rphy->grf, &port_cfg->phy_sus, true); 325 326 return 0; 327 } 328 329 static int rockchip_usb2phy_power_on(struct phy *phy) 330 { 331 struct udevice *vbus = NULL; 332 int ret; 333 334 vbus = rockchip_usb2phy_check_vbus(phy); 335 if (vbus) { 336 ret = regulator_set_enable(vbus, true); 337 if (ret) { 338 pr_err("%s: Failed to en VBus supply\n", __func__); 339 return ret; 340 } 341 } 342 343 return 0; 344 } 345 346 static int rockchip_usb2phy_power_off(struct phy *phy) 347 { 348 struct udevice *vbus = NULL; 349 int ret; 350 351 vbus = rockchip_usb2phy_check_vbus(phy); 352 if (vbus) { 353 ret = regulator_set_enable(vbus, false); 354 if (ret) { 355 pr_err("%s: Failed to dis VBus supply\n", __func__); 356 return ret; 357 } 358 } 359 360 return 0; 361 } 362 363 static int rockchip_usb2phy_of_xlate(struct phy *phy, 364 struct ofnode_phandle_args *args) 365 { 366 const char *dev_name = phy->dev->name; 367 struct udevice *parent = phy->dev->parent; 368 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 369 370 if (!strcasecmp(dev_name, "host-port")) { 371 phy->id = USB2PHY_PORT_HOST; 372 device_get_supply_regulator(phy->dev, "phy-supply", 373 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 374 } else if (!strcasecmp(dev_name, "otg-port")) { 375 phy->id = USB2PHY_PORT_OTG; 376 device_get_supply_regulator(phy->dev, "phy-supply", 377 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 378 } else { 379 pr_err("%s: invalid dev name\n", __func__); 380 return -EINVAL; 381 } 382 383 return 0; 384 } 385 386 static int rockchip_usb2phy_bind(struct udevice *dev) 387 { 388 struct udevice *child; 389 ofnode subnode; 390 const char *node_name; 391 int ret; 392 393 dev_for_each_subnode(subnode, dev) { 394 if (!ofnode_valid(subnode)) { 395 debug("%s: %s subnode not found", __func__, dev->name); 396 return -ENXIO; 397 } 398 399 node_name = ofnode_get_name(subnode); 400 debug("%s: subnode %s\n", __func__, node_name); 401 402 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 403 node_name, subnode, &child); 404 if (ret) { 405 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 406 __func__, node_name); 407 return ret; 408 } 409 } 410 411 return 0; 412 } 413 414 static int rockchip_usb2phy_probe(struct udevice *dev) 415 { 416 const struct rockchip_usb2phy_cfg *phy_cfgs; 417 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 418 u32 reg, index; 419 420 rphy->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 421 422 /* get phy power reset control */ 423 if (reset_get_by_name(dev, "u2phy", rphy->reset)) { 424 pr_err("can't get phy power reset for %s", dev->name); 425 return -EINVAL; 426 } 427 428 if (rphy->grf <= 0) { 429 dev_err(dev, "get syscon grf failed\n"); 430 return -EINVAL; 431 } 432 433 if (ofnode_read_u32(dev_ofnode(dev), "reg", ®)) { 434 dev_err(dev, "could not read reg\n"); 435 return -EINVAL; 436 } 437 438 phy_cfgs = 439 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 440 if (!phy_cfgs) { 441 dev_err(dev, "unable to get phy_cfgs\n"); 442 return -EINVAL; 443 } 444 445 /* find out a proper config which can be matched with dt. */ 446 index = 0; 447 do { 448 if (phy_cfgs[index].reg == reg) { 449 rphy->phy_cfg = &phy_cfgs[index]; 450 break; 451 } 452 } while (!phy_cfgs[index++].last); 453 454 if (!rphy->phy_cfg) { 455 dev_err(dev, "no phy-config can be matched\n"); 456 return -EINVAL; 457 } 458 459 if (rphy->phy_cfg->phy_tuning) 460 rphy->phy_cfg->phy_tuning(rphy); 461 462 return 0; 463 } 464 465 static int rv1126_usb2phy_tuning(struct rockchip_usb2phy *rphy) 466 { 467 return 0; 468 } 469 470 static struct phy_ops rockchip_usb2phy_ops = { 471 .init = rockchip_usb2phy_init, 472 .exit = rockchip_usb2phy_exit, 473 .power_on = rockchip_usb2phy_power_on, 474 .power_off = rockchip_usb2phy_power_off, 475 .of_xlate = rockchip_usb2phy_of_xlate, 476 }; 477 478 static const struct rockchip_usb2phy_cfg rv1126_phy_cfgs[] = { 479 { 480 .reg = 0xff4c0000, 481 .num_ports = 1, 482 .phy_tuning = rv1126_usb2phy_tuning, 483 .clkout_ctl = { 0x10230, 14, 14, 0, 1 }, 484 .port_cfgs = { 485 [USB2PHY_PORT_OTG] = { 486 .bypass_otgsuspendm = { 0x10234, 12, 12, 0, 1 }, 487 .bvalidfall_det_en = { 0x10300, 3, 3, 0, 1 }, 488 .bvalidfall_det_st = { 0x10304, 3, 3, 0, 1 }, 489 .bvalidfall_det_clr = { 0x10308, 3, 3, 0, 1 }, 490 .bvalidrise_det_en = { 0x10300, 2, 2, 0, 1 }, 491 .bvalidrise_det_st = { 0x10304, 2, 2, 0, 1 }, 492 .bvalidrise_det_clr = { 0x10308, 2, 2, 0, 1 }, 493 .disconfall_det_en = { 0x10300, 7, 7, 0, 1 }, 494 .disconfall_det_st = { 0x10304, 7, 7, 0, 1 }, 495 .disconfall_det_clr = { 0x10308, 7, 7, 0, 1 }, 496 .disconrise_det_en = { 0x10300, 6, 6, 0, 1 }, 497 .disconrise_det_st = { 0x10304, 6, 6, 0, 1 }, 498 .disconrise_det_clr = { 0x10308, 6, 6, 0, 1 }, 499 .idfall_det_en = { 0x10300, 5, 5, 0, 1 }, 500 .idfall_det_st = { 0x10304, 5, 5, 0, 1 }, 501 .idfall_det_clr = { 0x10308, 5, 5, 0, 1 }, 502 .idpullup = { 0x10230, 11, 11, 0, 1 }, 503 .idrise_det_en = { 0x10300, 4, 4, 0, 1 }, 504 .idrise_det_st = { 0x10304, 4, 4, 0, 1 }, 505 .idrise_det_clr = { 0x10308, 4, 4, 0, 1 }, 506 .ls_det_en = { 0x10300, 0, 0, 0, 1 }, 507 .ls_det_st = { 0x10304, 0, 0, 0, 1 }, 508 .ls_det_clr = { 0x10308, 0, 0, 0, 1 }, 509 .phy_sus = { 0x10230, 8, 0, 0x052, 0x1d9 }, 510 .utmi_bvalid = { 0x10248, 9, 9, 0, 1 }, 511 .utmi_iddig = { 0x10248, 6, 6, 0, 1 }, 512 .utmi_hostdet = { 0x10248, 7, 7, 0, 1 }, 513 } 514 }, 515 .chg_det = { 516 .chg_en = { 0x10234, 14, 14, 0, 1 }, 517 .chg_rst = { 0x10234, 15, 15, 0, 1 }, 518 .chg_valid = { 0x10248, 12, 12, 0, 1 }, 519 .phy_connect = { 0x10248, 13, 13, 0, 1 }, 520 }, 521 }, 522 { 523 .reg = 0xff4c8000, 524 .num_ports = 1, 525 .phy_tuning = rv1126_usb2phy_tuning, 526 .clkout_ctl = { 0x10238, 9, 9, 0, 1 }, 527 .port_cfgs = { 528 [USB2PHY_PORT_HOST] = { 529 .disconfall_det_en = { 0x10300, 9, 9, 0, 1 }, 530 .disconfall_det_st = { 0x10304, 9, 9, 0, 1 }, 531 .disconfall_det_clr = { 0x10308, 9, 9, 0, 1 }, 532 .disconrise_det_en = { 0x10300, 8, 8, 0, 1 }, 533 .disconrise_det_st = { 0x10304, 8, 8, 0, 1 }, 534 .disconrise_det_clr = { 0x10308, 8, 8, 0, 1 }, 535 .ls_det_en = { 0x10300, 1, 1, 0, 1 }, 536 .ls_det_st = { 0x10304, 1, 1, 0, 1 }, 537 .ls_det_clr = { 0x10308, 1, 1, 0, 1 }, 538 .phy_sus = { 0x10238, 3, 0, 0x2, 0x9 }, 539 .utmi_hostdet = { 0x10248, 23, 23, 0, 1 }, 540 } 541 }, 542 .chg_det = { 543 .chg_en = { 0x10238, 7, 7, 0, 1 }, 544 .chg_rst = { 0x10238, 8, 8, 0, 1 }, 545 .chg_valid = { 0x10248, 28, 28, 0, 1 }, 546 .phy_connect = { 0x10248, 29, 29, 0, 1 }, 547 }, 548 .last = true, 549 }, 550 }; 551 552 static const struct udevice_id rockchip_usb2phy_ids[] = { 553 { .compatible = "rockchip,rv1126-usb2phy", .data = (ulong)&rv1126_phy_cfgs }, 554 { } 555 }; 556 557 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 558 .name = "rockchip_usb2phy_port", 559 .id = UCLASS_PHY, 560 .ops = &rockchip_usb2phy_ops, 561 }; 562 563 U_BOOT_DRIVER(rockchip_usb2phy) = { 564 .name = "rockchip_usb2phy", 565 .id = UCLASS_PHY, 566 .of_match = rockchip_usb2phy_ids, 567 .probe = rockchip_usb2phy_probe, 568 .bind = rockchip_usb2phy_bind, 569 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 570 }; 571