1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip USB2.0 PHY with Naneng IP block driver 4 * 5 * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <dm/lists.h> 11 #include <generic-phy.h> 12 #include <syscon.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #include <reset-uclass.h> 16 #include <power/regulator.h> 17 18 #define U2PHY_BIT_WRITEABLE_SHIFT 16 19 20 struct rockchip_usb2phy; 21 22 enum power_supply_type { 23 POWER_SUPPLY_TYPE_UNKNOWN = 0, 24 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 25 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 26 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 27 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 28 }; 29 30 enum rockchip_usb2phy_port_id { 31 USB2PHY_PORT_OTG, 32 USB2PHY_PORT_HOST, 33 USB2PHY_NUM_PORTS, 34 }; 35 36 struct usb2phy_reg { 37 u32 offset; 38 u32 bitend; 39 u32 bitstart; 40 u32 disable; 41 u32 enable; 42 }; 43 44 /** 45 * struct rockchip_chg_det_reg: usb charger detect registers 46 * @chg_valid: charge valid signal. 47 * @phy_connect: PHY start handshake signal. 48 * @chg_en: charge detector enable signal. 49 * @chg_rst: charge detector reset signal, active high. 50 */ 51 struct rockchip_chg_det_reg { 52 struct usb2phy_reg chg_valid; 53 struct usb2phy_reg phy_connect; 54 struct usb2phy_reg chg_en; 55 struct usb2phy_reg chg_rst; 56 }; 57 58 /** 59 * struct rockchip_usb2phy_port_cfg: usb phy port configuration. 60 * @bypass_otgsuspendm: otg-suspendm bypass control register. 61 * 0: iddig; 1: grf. 62 * @bvalidfall_det_en: vbus valid fall detection enable register. 63 * @bvalidfall_det_st: vbus valid fall detection status register. 64 * @bvalidfall_det_clr: vbus valid fall detection clear register. 65 * @bvalidrise_det_en: vbus valid rise detection enable register. 66 * @bvalidrise_det_st: vbus valid rise detection status register. 67 * @bvalidrise_det_clr: vbus valid rise detection clear register. 68 * @disconfall_det_en: host connect detection enable register. 69 * @disconfall_det_st: host connect detection status register. 70 * @disconfall_det_clr: host connect detection clear register. 71 * @disconrise_det_en: host disconnect detection enable register. 72 * @disconrise_det_st: host disconnect detection status register. 73 * @disconrise_det_clr: host disconnect detection clear register. 74 * @idfall_det_en: id fall detection enable register. 75 * @idfall_det_st: id fall detection state register. 76 * @idfall_det_clr: id fall detection clear register. 77 * @idpullup: id pin pullup or pulldown control register. 78 * @idrise_det_en: id rise detection enable register. 79 * @idrise_det_st: id rise detection state register. 80 * @idrise_det_clr: id rise detection clear register. 81 * @ls_det_en: linestate detection enable register. 82 * @ls_det_st: linestate detection state register. 83 * @ls_det_clr: linestate detection clear register. 84 * @phy_sus: phy suspend register. 85 * @utmi_bvalid: utmi vbus bvalid status register. 86 * @utmi_iddig: otg port id pin status register. 87 * @utmi_hostdet: utmi host disconnect status register. 88 */ 89 struct rockchip_usb2phy_port_cfg { 90 struct usb2phy_reg bypass_otgsuspendm; 91 struct usb2phy_reg bvalidfall_det_en; 92 struct usb2phy_reg bvalidfall_det_st; 93 struct usb2phy_reg bvalidfall_det_clr; 94 struct usb2phy_reg bvalidrise_det_en; 95 struct usb2phy_reg bvalidrise_det_st; 96 struct usb2phy_reg bvalidrise_det_clr; 97 struct usb2phy_reg disconfall_det_en; 98 struct usb2phy_reg disconfall_det_st; 99 struct usb2phy_reg disconfall_det_clr; 100 struct usb2phy_reg disconrise_det_en; 101 struct usb2phy_reg disconrise_det_st; 102 struct usb2phy_reg disconrise_det_clr; 103 struct usb2phy_reg idfall_det_en; 104 struct usb2phy_reg idfall_det_st; 105 struct usb2phy_reg idfall_det_clr; 106 struct usb2phy_reg idpullup; 107 struct usb2phy_reg idrise_det_en; 108 struct usb2phy_reg idrise_det_st; 109 struct usb2phy_reg idrise_det_clr; 110 struct usb2phy_reg ls_det_en; 111 struct usb2phy_reg ls_det_st; 112 struct usb2phy_reg ls_det_clr; 113 struct usb2phy_reg phy_sus; 114 struct usb2phy_reg utmi_bvalid; 115 struct usb2phy_reg utmi_iddig; 116 struct usb2phy_reg utmi_hostdet; 117 }; 118 119 /** 120 * struct rockchip_usb2phy_cfg: usb phy configuration. 121 * @reg: the address offset of grf for usb-phy config. 122 * @num_ports: specify how many ports that the phy has. 123 * @phy_tuning: phy default parameters tuning. 124 * @clkout_ctl: keep on/turn off output clk of phy. 125 * @port_cfgs: ports register configuration, assigned by driver data. 126 * @chg_det: charger detection registers. 127 * @last: indicate the last one. 128 */ 129 struct rockchip_usb2phy_cfg { 130 unsigned int reg; 131 unsigned int num_ports; 132 int (*phy_tuning)(struct rockchip_usb2phy *rphy); 133 struct usb2phy_reg clkout_ctl; 134 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 135 const struct rockchip_chg_det_reg chg_det; 136 bool last; 137 }; 138 139 /** 140 * struct rockchip_usb2phy: usb2.0 phy driver data. 141 * @grf: General Register Files register base. 142 * @reset: power reset signal for phy. 143 * @vbus_supply: vbus supply for usb host. 144 * @phy_cfg: phy register configuration, assigned by driver data. 145 */ 146 struct rockchip_usb2phy { 147 void __iomem *grf; 148 struct reset_ctl *reset; 149 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 150 const struct rockchip_usb2phy_cfg *phy_cfg; 151 }; 152 153 static inline int property_enable(void __iomem *base, 154 const struct usb2phy_reg *reg, bool en) 155 { 156 u32 val, mask, tmp; 157 158 tmp = en ? reg->enable : reg->disable; 159 mask = GENMASK(reg->bitend, reg->bitstart); 160 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 161 162 writel(val, base + reg->offset); 163 164 return 0; 165 } 166 167 static inline bool property_enabled(void __iomem *base, 168 const struct usb2phy_reg *reg) 169 { 170 u32 tmp, orig; 171 u32 mask = GENMASK(reg->bitend, reg->bitstart); 172 173 orig = readl(base + reg->offset); 174 175 tmp = (orig & mask) >> reg->bitstart; 176 177 return tmp == reg->enable; 178 } 179 180 static const char *chg_to_string(enum power_supply_type chg_type) 181 { 182 switch (chg_type) { 183 case POWER_SUPPLY_TYPE_USB: 184 return "USB_SDP_CHARGER"; 185 case POWER_SUPPLY_TYPE_USB_DCP: 186 return "USB_DCP_CHARGER"; 187 case POWER_SUPPLY_TYPE_USB_CDP: 188 return "USB_CDP_CHARGER"; 189 case POWER_SUPPLY_TYPE_USB_FLOATING: 190 return "USB_FLOATING_CHARGER"; 191 default: 192 return "INVALID_CHARGER"; 193 } 194 } 195 196 int rockchip_chg_get_type(void) 197 { 198 const struct rockchip_usb2phy_port_cfg *port_cfg; 199 enum power_supply_type chg_type; 200 struct rockchip_usb2phy *rphy; 201 struct udevice *udev; 202 bool chg_valid, phy_connect; 203 int cnt; 204 int ret; 205 206 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 207 if (ret == -ENODEV) { 208 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 209 if (ret) { 210 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 211 return ret; 212 } 213 } 214 215 rphy = dev_get_priv(udev); 216 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 217 218 /* Check USB-Vbus status first */ 219 if (!property_enabled(rphy->grf, &port_cfg->utmi_bvalid)) { 220 pr_info("%s: no charger found\n", __func__); 221 return POWER_SUPPLY_TYPE_UNKNOWN; 222 } 223 224 reset_assert(rphy->reset); 225 226 /* CHG_RST is set to 1'b0 to start charge detection */ 227 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, true); 228 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, false); 229 230 for (cnt = 0; cnt < 12; cnt++) { 231 mdelay(100); 232 233 chg_valid = property_enabled(rphy->grf, 234 &rphy->phy_cfg->chg_det.chg_valid); 235 phy_connect = 236 property_enabled(rphy->grf, 237 &rphy->phy_cfg->chg_det.phy_connect); 238 chg_type = (chg_valid << 1) | phy_connect; 239 240 if (chg_type) 241 goto compeleted; 242 } 243 244 compeleted: 245 debug("charger = %s\n", chg_to_string(chg_type)); 246 247 mdelay(1); 248 reset_deassert(rphy->reset); 249 /* disable the chg detection module */ 250 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, true); 251 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, false); 252 253 return chg_type; 254 } 255 256 int rockchip_u2phy_vbus_detect(void) 257 { 258 int chg_type; 259 260 chg_type = rockchip_chg_get_type(); 261 262 return (chg_type == POWER_SUPPLY_TYPE_USB || 263 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 264 } 265 266 static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy) 267 { 268 struct udevice *parent = phy->dev->parent; 269 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 270 const struct rockchip_usb2phy_port_cfg *port_cfg; 271 void __iomem *base = rphy->grf; 272 struct udevice *vbus = NULL; 273 bool iddig = true; 274 275 if (phy->id == USB2PHY_PORT_HOST) { 276 vbus = rphy->vbus_supply[USB2PHY_PORT_HOST]; 277 } else if (phy->id == USB2PHY_PORT_OTG) { 278 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 279 if (port_cfg->utmi_iddig.offset) { 280 iddig = property_enabled(base, &port_cfg->utmi_iddig); 281 if (!iddig) 282 vbus = rphy->vbus_supply[USB2PHY_PORT_OTG]; 283 } 284 } 285 286 return vbus; 287 } 288 289 static int rockchip_usb2phy_init(struct phy *phy) 290 { 291 struct udevice *parent = phy->dev->parent; 292 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 293 const struct rockchip_usb2phy_port_cfg *port_cfg; 294 295 if (phy->id == USB2PHY_PORT_OTG) { 296 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 297 } else if (phy->id == USB2PHY_PORT_HOST) { 298 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 299 } else { 300 dev_err(phy->dev, "phy id %lu not support", phy->id); 301 return -EINVAL; 302 } 303 304 property_enable(rphy->grf, &port_cfg->phy_sus, false); 305 306 /* waiting for the utmi_clk to become stable */ 307 udelay(2000); 308 309 return 0; 310 } 311 312 static int rockchip_usb2phy_exit(struct phy *phy) 313 { 314 struct udevice *parent = phy->dev->parent; 315 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 316 const struct rockchip_usb2phy_port_cfg *port_cfg; 317 318 if (phy->id == USB2PHY_PORT_OTG) { 319 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 320 } else if (phy->id == USB2PHY_PORT_HOST) { 321 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 322 } else { 323 dev_err(phy->dev, "phy id %lu not support", phy->id); 324 return -EINVAL; 325 } 326 327 property_enable(rphy->grf, &port_cfg->phy_sus, true); 328 329 return 0; 330 } 331 332 static int rockchip_usb2phy_power_on(struct phy *phy) 333 { 334 struct udevice *vbus = NULL; 335 int ret; 336 337 vbus = rockchip_usb2phy_check_vbus(phy); 338 if (vbus) { 339 ret = regulator_set_enable(vbus, true); 340 if (ret) { 341 pr_err("%s: Failed to en VBus supply\n", __func__); 342 return ret; 343 } 344 } 345 346 return 0; 347 } 348 349 static int rockchip_usb2phy_power_off(struct phy *phy) 350 { 351 struct udevice *vbus = NULL; 352 int ret; 353 354 vbus = rockchip_usb2phy_check_vbus(phy); 355 if (vbus) { 356 ret = regulator_set_enable(vbus, false); 357 if (ret) { 358 pr_err("%s: Failed to dis VBus supply\n", __func__); 359 return ret; 360 } 361 } 362 363 return 0; 364 } 365 366 static int rockchip_usb2phy_of_xlate(struct phy *phy, 367 struct ofnode_phandle_args *args) 368 { 369 const char *dev_name = phy->dev->name; 370 struct udevice *parent = phy->dev->parent; 371 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 372 373 if (!strcasecmp(dev_name, "host-port")) { 374 phy->id = USB2PHY_PORT_HOST; 375 device_get_supply_regulator(phy->dev, "phy-supply", 376 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 377 } else if (!strcasecmp(dev_name, "otg-port")) { 378 phy->id = USB2PHY_PORT_OTG; 379 device_get_supply_regulator(phy->dev, "phy-supply", 380 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 381 } else { 382 pr_err("%s: invalid dev name\n", __func__); 383 return -EINVAL; 384 } 385 386 return 0; 387 } 388 389 static int rockchip_usb2phy_bind(struct udevice *dev) 390 { 391 struct udevice *child; 392 ofnode subnode; 393 const char *node_name; 394 int ret; 395 396 dev_for_each_subnode(subnode, dev) { 397 if (!ofnode_valid(subnode)) { 398 debug("%s: %s subnode not found", __func__, dev->name); 399 return -ENXIO; 400 } 401 402 node_name = ofnode_get_name(subnode); 403 debug("%s: subnode %s\n", __func__, node_name); 404 405 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 406 node_name, subnode, &child); 407 if (ret) { 408 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 409 __func__, node_name); 410 return ret; 411 } 412 } 413 414 return 0; 415 } 416 417 static int rockchip_usb2phy_probe(struct udevice *dev) 418 { 419 const struct rockchip_usb2phy_cfg *phy_cfgs; 420 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 421 u32 reg, index; 422 423 rphy->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 424 425 /* get phy power reset control */ 426 if (reset_get_by_name(dev, "u2phy", rphy->reset)) { 427 pr_err("can't get phy power reset for %s", dev->name); 428 return -EINVAL; 429 } 430 431 if (rphy->grf <= 0) { 432 dev_err(dev, "get syscon grf failed\n"); 433 return -EINVAL; 434 } 435 436 if (ofnode_read_u32(dev_ofnode(dev), "reg", ®)) { 437 dev_err(dev, "could not read reg\n"); 438 return -EINVAL; 439 } 440 441 phy_cfgs = 442 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 443 if (!phy_cfgs) { 444 dev_err(dev, "unable to get phy_cfgs\n"); 445 return -EINVAL; 446 } 447 448 /* find out a proper config which can be matched with dt. */ 449 index = 0; 450 do { 451 if (phy_cfgs[index].reg == reg) { 452 rphy->phy_cfg = &phy_cfgs[index]; 453 break; 454 } 455 } while (!phy_cfgs[index++].last); 456 457 if (!rphy->phy_cfg) { 458 dev_err(dev, "no phy-config can be matched\n"); 459 return -EINVAL; 460 } 461 462 if (rphy->phy_cfg->phy_tuning) 463 rphy->phy_cfg->phy_tuning(rphy); 464 465 return 0; 466 } 467 468 static int rv1126_usb2phy_tuning(struct rockchip_usb2phy *rphy) 469 { 470 return 0; 471 } 472 473 static struct phy_ops rockchip_usb2phy_ops = { 474 .init = rockchip_usb2phy_init, 475 .exit = rockchip_usb2phy_exit, 476 .power_on = rockchip_usb2phy_power_on, 477 .power_off = rockchip_usb2phy_power_off, 478 .of_xlate = rockchip_usb2phy_of_xlate, 479 }; 480 481 static const struct rockchip_usb2phy_cfg rv1126_phy_cfgs[] = { 482 { 483 .reg = 0xff4c0000, 484 .num_ports = 1, 485 .phy_tuning = rv1126_usb2phy_tuning, 486 .clkout_ctl = { 0x10230, 14, 14, 0, 1 }, 487 .port_cfgs = { 488 [USB2PHY_PORT_OTG] = { 489 .bypass_otgsuspendm = { 0x10234, 12, 12, 0, 1 }, 490 .bvalidfall_det_en = { 0x10300, 3, 3, 0, 1 }, 491 .bvalidfall_det_st = { 0x10304, 3, 3, 0, 1 }, 492 .bvalidfall_det_clr = { 0x10308, 3, 3, 0, 1 }, 493 .bvalidrise_det_en = { 0x10300, 2, 2, 0, 1 }, 494 .bvalidrise_det_st = { 0x10304, 2, 2, 0, 1 }, 495 .bvalidrise_det_clr = { 0x10308, 2, 2, 0, 1 }, 496 .disconfall_det_en = { 0x10300, 7, 7, 0, 1 }, 497 .disconfall_det_st = { 0x10304, 7, 7, 0, 1 }, 498 .disconfall_det_clr = { 0x10308, 7, 7, 0, 1 }, 499 .disconrise_det_en = { 0x10300, 6, 6, 0, 1 }, 500 .disconrise_det_st = { 0x10304, 6, 6, 0, 1 }, 501 .disconrise_det_clr = { 0x10308, 6, 6, 0, 1 }, 502 .idfall_det_en = { 0x10300, 5, 5, 0, 1 }, 503 .idfall_det_st = { 0x10304, 5, 5, 0, 1 }, 504 .idfall_det_clr = { 0x10308, 5, 5, 0, 1 }, 505 .idpullup = { 0x10230, 11, 11, 0, 1 }, 506 .idrise_det_en = { 0x10300, 4, 4, 0, 1 }, 507 .idrise_det_st = { 0x10304, 4, 4, 0, 1 }, 508 .idrise_det_clr = { 0x10308, 4, 4, 0, 1 }, 509 .ls_det_en = { 0x10300, 0, 0, 0, 1 }, 510 .ls_det_st = { 0x10304, 0, 0, 0, 1 }, 511 .ls_det_clr = { 0x10308, 0, 0, 0, 1 }, 512 .phy_sus = { 0x10230, 8, 0, 0x052, 0x1d9 }, 513 .utmi_bvalid = { 0x10248, 9, 9, 0, 1 }, 514 .utmi_iddig = { 0x10248, 6, 6, 0, 1 }, 515 .utmi_hostdet = { 0x10248, 7, 7, 0, 1 }, 516 } 517 }, 518 .chg_det = { 519 .chg_en = { 0x10234, 14, 14, 0, 1 }, 520 .chg_rst = { 0x10234, 15, 15, 0, 1 }, 521 .chg_valid = { 0x10248, 12, 12, 0, 1 }, 522 .phy_connect = { 0x10248, 13, 13, 0, 1 }, 523 }, 524 }, 525 { 526 .reg = 0xff4c8000, 527 .num_ports = 1, 528 .phy_tuning = rv1126_usb2phy_tuning, 529 .clkout_ctl = { 0x10238, 9, 9, 0, 1 }, 530 .port_cfgs = { 531 [USB2PHY_PORT_HOST] = { 532 .disconfall_det_en = { 0x10300, 9, 9, 0, 1 }, 533 .disconfall_det_st = { 0x10304, 9, 9, 0, 1 }, 534 .disconfall_det_clr = { 0x10308, 9, 9, 0, 1 }, 535 .disconrise_det_en = { 0x10300, 8, 8, 0, 1 }, 536 .disconrise_det_st = { 0x10304, 8, 8, 0, 1 }, 537 .disconrise_det_clr = { 0x10308, 8, 8, 0, 1 }, 538 .ls_det_en = { 0x10300, 1, 1, 0, 1 }, 539 .ls_det_st = { 0x10304, 1, 1, 0, 1 }, 540 .ls_det_clr = { 0x10308, 1, 1, 0, 1 }, 541 .phy_sus = { 0x10238, 3, 0, 0x2, 0x9 }, 542 .utmi_hostdet = { 0x10248, 23, 23, 0, 1 }, 543 } 544 }, 545 .chg_det = { 546 .chg_en = { 0x10238, 7, 7, 0, 1 }, 547 .chg_rst = { 0x10238, 8, 8, 0, 1 }, 548 .chg_valid = { 0x10248, 28, 28, 0, 1 }, 549 .phy_connect = { 0x10248, 29, 29, 0, 1 }, 550 }, 551 .last = true, 552 }, 553 }; 554 555 static const struct udevice_id rockchip_usb2phy_ids[] = { 556 { .compatible = "rockchip,rv1126-usb2phy", .data = (ulong)&rv1126_phy_cfgs }, 557 { } 558 }; 559 560 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 561 .name = "rockchip_usb2phy_port", 562 .id = UCLASS_PHY, 563 .ops = &rockchip_usb2phy_ops, 564 }; 565 566 U_BOOT_DRIVER(rockchip_usb2phy) = { 567 .name = "rockchip_usb2phy", 568 .id = UCLASS_PHY, 569 .of_match = rockchip_usb2phy_ids, 570 .probe = rockchip_usb2phy_probe, 571 .bind = rockchip_usb2phy_bind, 572 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 573 }; 574