1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dt-bindings/phy/phy.h> 13 #include <generic-phy.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <regmap.h> 18 #include <reset-uclass.h> 19 #include <linux/iopoll.h> 20 21 #define BIT_WRITEABLE_SHIFT 16 22 23 struct rockchip_combphy_priv; 24 25 struct combphy_reg { 26 u32 offset; 27 u16 bitend; 28 u16 bitstart; 29 u16 disable; 30 u16 enable; 31 }; 32 33 struct rockchip_combphy_grfcfg { 34 struct combphy_reg pcie_mode_set; 35 struct combphy_reg usb_mode_set; 36 struct combphy_reg sgmii_mode_set; 37 struct combphy_reg qsgmii_mode_set; 38 struct combphy_reg pipe_rxterm_set; 39 struct combphy_reg pipe_txelec_set; 40 struct combphy_reg pipe_txcomp_set; 41 struct combphy_reg pipe_clk_24m; 42 struct combphy_reg pipe_clk_25m; 43 struct combphy_reg pipe_clk_100m; 44 struct combphy_reg pipe_phymode_sel; 45 struct combphy_reg pipe_rate_sel; 46 struct combphy_reg pipe_rxterm_sel; 47 struct combphy_reg pipe_txelec_sel; 48 struct combphy_reg pipe_txcomp_sel; 49 struct combphy_reg pipe_clk_ext; 50 struct combphy_reg pipe_sel_usb; 51 struct combphy_reg pipe_sel_qsgmii; 52 struct combphy_reg pipe_phy_status; 53 struct combphy_reg con0_for_pcie; 54 struct combphy_reg con1_for_pcie; 55 struct combphy_reg con2_for_pcie; 56 struct combphy_reg con3_for_pcie; 57 struct combphy_reg con0_for_sata; 58 struct combphy_reg con1_for_sata; 59 struct combphy_reg con2_for_sata; 60 struct combphy_reg con3_for_sata; 61 struct combphy_reg pipe_con0_for_sata; 62 struct combphy_reg pipe_con1_for_sata; 63 struct combphy_reg pipe_sgmii_mac_sel; 64 struct combphy_reg pipe_xpcs_phy_ready; 65 struct combphy_reg u3otg0_port_en; 66 struct combphy_reg u3otg1_port_en; 67 struct combphy_reg u3otg0_pipe_clk_sel; 68 struct combphy_reg pipe_phy_grf_reset; 69 }; 70 71 struct rockchip_combphy_cfg { 72 const struct rockchip_combphy_grfcfg *grfcfg; 73 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 74 }; 75 76 struct rockchip_combphy_priv { 77 u32 mode; 78 void __iomem *mmio; 79 struct udevice *dev; 80 struct regmap *pipe_grf; 81 struct regmap *phy_grf; 82 struct phy *phy; 83 struct reset_ctl phy_rst; 84 struct clk ref_clk; 85 const struct rockchip_combphy_cfg *cfg; 86 }; 87 88 static int param_write(struct regmap *base, 89 const struct combphy_reg *reg, bool en) 90 { 91 u32 val, mask, tmp; 92 93 tmp = en ? reg->enable : reg->disable; 94 mask = GENMASK(reg->bitend, reg->bitstart); 95 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 96 97 return regmap_write(base, reg->offset, val); 98 } 99 100 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) 101 { 102 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 103 u32 mask, val; 104 105 mask = GENMASK(cfg->pipe_phy_status.bitend, 106 cfg->pipe_phy_status.bitstart); 107 108 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); 109 val = (val & mask) >> cfg->pipe_phy_status.bitstart; 110 111 return val; 112 } 113 114 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) 115 { 116 int ret = 0; 117 118 if (priv->cfg->combphy_cfg) { 119 ret = priv->cfg->combphy_cfg(priv); 120 if (ret) { 121 dev_err(priv->dev, "failed to init phy for pcie\n"); 122 return ret; 123 } 124 } 125 126 return ret; 127 } 128 129 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) 130 { 131 int ret = 0; 132 133 if (priv->cfg->combphy_cfg) { 134 ret = priv->cfg->combphy_cfg(priv); 135 if (ret) { 136 dev_err(priv->dev, "failed to init phy for usb3\n"); 137 return ret; 138 } 139 } 140 141 return ret; 142 } 143 144 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) 145 { 146 int ret = 0; 147 148 if (priv->cfg->combphy_cfg) { 149 ret = priv->cfg->combphy_cfg(priv); 150 if (ret) { 151 dev_err(priv->dev, "failed to init phy for sata\n"); 152 return ret; 153 } 154 } 155 156 return ret; 157 } 158 159 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) 160 { 161 int ret = 0; 162 163 if (priv->cfg->combphy_cfg) { 164 ret = priv->cfg->combphy_cfg(priv); 165 if (ret) { 166 dev_err(priv->dev, "failed to init phy for sgmii\n"); 167 return ret; 168 } 169 } 170 171 return ret; 172 } 173 174 int rockchip_combphy_usb3_uboot_init(void) 175 { 176 struct udevice *udev; 177 struct rockchip_combphy_priv *priv; 178 const struct rockchip_combphy_grfcfg *cfg; 179 u32 val; 180 int ret; 181 182 ret = uclass_get_device_by_driver(UCLASS_PHY, 183 DM_GET_DRIVER(rockchip_naneng_combphy), 184 &udev); 185 if (ret) { 186 pr_err("%s: get usb3-phy node failed: %d\n", __func__, ret); 187 return ret; 188 } 189 190 priv = dev_get_priv(udev); 191 priv->mode = PHY_TYPE_USB3; 192 cfg = priv->cfg->grfcfg; 193 194 rockchip_combphy_usb3_init(priv); 195 reset_deassert(&priv->phy_rst); 196 197 if (cfg->pipe_phy_grf_reset.enable) 198 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 199 200 if (priv->mode == PHY_TYPE_USB3) { 201 ret = readx_poll_timeout(rockchip_combphy_is_ready, 202 priv, val, 203 val == cfg->pipe_phy_status.enable, 204 1000); 205 if (ret) { 206 dev_err(priv->dev, "wait phy status ready timeout\n"); 207 param_write(priv->phy_grf, &cfg->usb_mode_set, false); 208 if (cfg->u3otg0_pipe_clk_sel.disable) 209 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, false); 210 return ret; 211 } 212 } 213 214 /* Select clk_usb3otg0_pipe for source clk */ 215 if (cfg->u3otg0_pipe_clk_sel.disable) 216 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, true); 217 218 return ret; 219 } 220 221 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) 222 { 223 switch (priv->mode) { 224 case PHY_TYPE_PCIE: 225 rockchip_combphy_pcie_init(priv); 226 break; 227 case PHY_TYPE_USB3: 228 rockchip_combphy_usb3_init(priv); 229 break; 230 case PHY_TYPE_SATA: 231 rockchip_combphy_sata_init(priv); 232 break; 233 case PHY_TYPE_SGMII: 234 case PHY_TYPE_QSGMII: 235 return rockchip_combphy_sgmii_init(priv); 236 default: 237 dev_err(priv->dev, "incompatible PHY type\n"); 238 return -EINVAL; 239 } 240 241 return 0; 242 } 243 244 static int rockchip_combphy_init(struct phy *phy) 245 { 246 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 247 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 248 int ret; 249 250 ret = clk_enable(&priv->ref_clk); 251 if (ret < 0 && ret != -ENOSYS) 252 return ret; 253 254 ret = rockchip_combphy_set_mode(priv); 255 if (ret) 256 goto err_clk; 257 258 reset_deassert(&priv->phy_rst); 259 260 if (cfg->pipe_phy_grf_reset.enable) 261 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 262 263 return 0; 264 265 err_clk: 266 clk_disable(&priv->ref_clk); 267 268 return ret; 269 } 270 271 static int rockchip_combphy_exit(struct phy *phy) 272 { 273 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 274 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 275 276 if (cfg->pipe_phy_grf_reset.enable) 277 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); 278 279 reset_assert(&priv->phy_rst); 280 clk_disable(&priv->ref_clk); 281 282 return 0; 283 } 284 285 static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) 286 { 287 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 288 289 if (args->args_count != 1) { 290 pr_err("invalid number of arguments\n"); 291 return -EINVAL; 292 } 293 294 priv->mode = args->args[0]; 295 296 return 0; 297 } 298 299 static const struct phy_ops rochchip_combphy_ops = { 300 .init = rockchip_combphy_init, 301 .exit = rockchip_combphy_exit, 302 .of_xlate = rockchip_combphy_xlate, 303 }; 304 305 static int rockchip_combphy_parse_dt(struct udevice *dev, 306 struct rockchip_combphy_priv *priv) 307 { 308 struct udevice *syscon; 309 int ret; 310 u32 vals[4]; 311 312 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); 313 if (ret) { 314 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap ret= %d\n", ret); 315 return ret; 316 } 317 priv->pipe_grf = syscon_get_regmap(syscon); 318 319 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); 320 if (ret) { 321 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 322 return ret; 323 } 324 priv->phy_grf = syscon_get_regmap(syscon); 325 326 ret = clk_get_by_index(dev, 0, &priv->ref_clk); 327 if (ret) { 328 dev_err(dev, "failed to find ref clock\n"); 329 return PTR_ERR(&priv->ref_clk); 330 } 331 332 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); 333 if (ret) { 334 dev_err(dev, "no phy reset control specified\n"); 335 return ret; 336 } 337 338 if (!dev_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", 339 vals, ARRAY_SIZE(vals))) 340 regmap_write(priv->pipe_grf, vals[0], 341 (GENMASK(vals[2], vals[1]) << 16) | vals[3]); 342 343 return 0; 344 } 345 346 static int rockchip_combphy_probe(struct udevice *udev) 347 { 348 struct rockchip_combphy_priv *priv = dev_get_priv(udev); 349 const struct rockchip_combphy_cfg *phy_cfg; 350 351 priv->mmio = (void __iomem *)dev_read_addr(udev); 352 if (IS_ERR(priv->mmio)) 353 return PTR_ERR(priv->mmio); 354 355 phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); 356 if (!phy_cfg) { 357 dev_err(udev, "No OF match data provided\n"); 358 return -EINVAL; 359 } 360 361 priv->dev = udev; 362 priv->mode = PHY_TYPE_SATA; 363 priv->cfg = phy_cfg; 364 365 return rockchip_combphy_parse_dt(udev, priv); 366 } 367 368 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) 369 { 370 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 371 u32 val; 372 373 switch (priv->mode) { 374 case PHY_TYPE_PCIE: 375 /* Set SSC downward spread spectrum */ 376 val = readl(priv->mmio + 0x18); 377 val &= ~GENMASK(5, 4); 378 val |= 0x01 << 4; 379 writel(val, priv->mmio + 0x18); 380 381 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 382 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 383 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 384 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 385 break; 386 case PHY_TYPE_USB3: 387 /* Set SSC downward spread spectrum */ 388 val = readl(priv->mmio + 0x18); 389 val &= ~GENMASK(5, 4); 390 val |= 0x01 << 4; 391 writel(val, priv->mmio + 0x18); 392 393 /* Enable adaptive CTLE for USB3.0 Rx */ 394 val = readl(priv->mmio + 0x200); 395 val &= ~GENMASK(17, 17); 396 val |= 0x01; 397 writel(val, priv->mmio + 0x200); 398 399 /* Set Rx squelch input filler bandwidth */ 400 val = readl(priv->mmio + 0x20c); 401 val &= ~GENMASK(2, 0); 402 val |= 0x06; 403 writel(val, priv->mmio + 0x20c); 404 405 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 406 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 407 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 408 break; 409 default: 410 dev_err(priv->dev, "incompatible PHY type\n"); 411 return -EINVAL; 412 } 413 414 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 415 if (priv->mode == PHY_TYPE_PCIE) { 416 /* PLL KVCO tuning fine */ 417 val = readl(priv->mmio + 0x18); 418 val &= ~(0x7 << 10); 419 val |= 0x2 << 10; 420 writel(val, priv->mmio + 0x18); 421 422 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ 423 val = readl(priv->mmio + 0x108); 424 val &= ~(0x7f7); 425 val |= 0x4f0; 426 writel(val, priv->mmio + 0x108); 427 } 428 429 return 0; 430 } 431 432 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { 433 /* pipe-phy-grf */ 434 .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 }, 435 .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 }, 436 .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 }, 437 .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 }, 438 .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 }, 439 .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 }, 440 .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 }, 441 .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 }, 442 .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 }, 443 .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 }, 444 .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 }, 445 .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 }, 446 .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 }, 447 .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 }, 448 .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 }, 449 .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 }, 450 /* pipe-grf */ 451 .u3otg0_pipe_clk_sel = { 0x40044, 7, 7, 0x01, 0x00 }, 452 .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 }, 453 }; 454 455 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { 456 .grfcfg = &rk3528_combphy_grfcfgs, 457 .combphy_cfg = rk3528_combphy_cfg, 458 }; 459 460 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) 461 { 462 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 463 u32 val; 464 465 switch (priv->mode) { 466 case PHY_TYPE_PCIE: 467 /* Set SSC downward spread spectrum */ 468 val = readl(priv->mmio + (0x1f << 2)); 469 val &= ~GENMASK(5, 4); 470 val |= 0x01 << 4; 471 writel(val, priv->mmio + 0x7c); 472 473 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 474 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 475 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 476 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 477 break; 478 case PHY_TYPE_USB3: 479 /* Set SSC downward spread spectrum */ 480 val = readl(priv->mmio + (0x1f << 2)); 481 val &= ~GENMASK(5, 4); 482 val |= 0x01 << 4; 483 writel(val, priv->mmio + 0x7c); 484 485 /* Enable adaptive CTLE for USB3.0 Rx */ 486 val = readl(priv->mmio + (0x0e << 2)); 487 val &= ~GENMASK(0, 0); 488 val |= 0x01; 489 writel(val, priv->mmio + (0x0e << 2)); 490 491 /* Set PLL KVCO fine tuning signals */ 492 val = readl(priv->mmio + (0x20 << 2)); 493 val &= ~(0x7 << 2); 494 val |= 0x2 << 2; 495 writel(val, priv->mmio + (0x20 << 2)); 496 497 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 498 writel(0x4, priv->mmio + (0xb << 2)); 499 500 /* Set PLL input clock divider 1/2 */ 501 val = readl(priv->mmio + (0x5 << 2)); 502 val &= ~(0x3 << 6); 503 val |= 0x1 << 6; 504 writel(val, priv->mmio + (0x5 << 2)); 505 506 /* Set PLL loop divider */ 507 writel(0x32, priv->mmio + (0x11 << 2)); 508 509 /* Set PLL KVCO to min and set PLL charge pump current to max */ 510 writel(0xf0, priv->mmio + (0xa << 2)); 511 512 /* Set Rx squelch input filler bandwidth */ 513 writel(0x0e, priv->mmio + (0x14 << 2)); 514 515 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 516 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 517 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 518 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 519 break; 520 default: 521 pr_err("%s, phy-type %d\n", __func__, priv->mode); 522 return -EINVAL; 523 } 524 525 clk_set_rate(&priv->ref_clk, 100000000); 526 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 527 528 if (priv->mode == PHY_TYPE_PCIE) { 529 /* PLL KVCO tuning fine */ 530 val = readl(priv->mmio + (0x20 << 2)); 531 val &= ~(0x7 << 2); 532 val |= 0x2 << 2; 533 writel(val, priv->mmio + (0x20 << 2)); 534 535 /* Enable controlling random jitter, aka RMJ */ 536 writel(0x4, priv->mmio + (0xb << 2)); 537 538 val = readl(priv->mmio + (0x5 << 2)); 539 val &= ~(0x3 << 6); 540 val |= 0x1 << 6; 541 writel(val, priv->mmio + (0x5 << 2)); 542 543 writel(0x32, priv->mmio + (0x11 << 2)); 544 writel(0xf0, priv->mmio + (0xa << 2)); 545 } 546 547 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 548 val = readl(priv->mmio + (0x7 << 2)); 549 val |= BIT(4); 550 writel(val, priv->mmio + (0x7 << 2)); 551 } 552 553 return 0; 554 } 555 556 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { 557 /* pipe-phy-grf */ 558 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 559 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 560 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 561 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 562 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 563 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 564 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 565 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 566 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 567 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 568 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 569 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 570 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 571 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 572 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 573 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 574 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 575 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 576 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 577 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 578 /* pipe-grf */ 579 .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 }, 580 }; 581 582 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { 583 .grfcfg = &rk3562_combphy_grfcfgs, 584 .combphy_cfg = rk3562_combphy_cfg, 585 }; 586 587 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 588 { 589 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 590 u32 val; 591 592 switch (priv->mode) { 593 case PHY_TYPE_PCIE: 594 /* Set SSC downward spread spectrum */ 595 val = readl(priv->mmio + (0x1f << 2)); 596 val &= ~GENMASK(5, 4); 597 val |= 0x01 << 4; 598 writel(val, priv->mmio + 0x7c); 599 600 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 601 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 602 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 603 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 604 break; 605 case PHY_TYPE_USB3: 606 /* Set SSC downward spread spectrum */ 607 val = readl(priv->mmio + (0x1f << 2)); 608 val &= ~GENMASK(5, 4); 609 val |= 0x01 << 4; 610 writel(val, priv->mmio + 0x7c); 611 612 /* Enable adaptive CTLE for USB3.0 Rx */ 613 val = readl(priv->mmio + (0x0e << 2)); 614 val &= ~GENMASK(0, 0); 615 val |= 0x01; 616 writel(val, priv->mmio + (0x0e << 2)); 617 618 /* Set PLL KVCO fine tuning signals */ 619 val = readl(priv->mmio + (0x20 << 2)); 620 val &= ~(0x7 << 2); 621 val |= 0x2 << 2; 622 writel(val, priv->mmio + (0x20 << 2)); 623 624 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 625 writel(0x4, priv->mmio + (0xb << 2)); 626 627 /* Set PLL input clock divider 1/2 */ 628 val = readl(priv->mmio + (0x5 << 2)); 629 val &= ~(0x3 << 6); 630 val |= 0x1 << 6; 631 writel(val, priv->mmio + (0x5 << 2)); 632 633 /* Set PLL loop divider */ 634 writel(0x32, priv->mmio + (0x11 << 2)); 635 636 /* Set PLL KVCO to min and set PLL charge pump current to max */ 637 writel(0xf0, priv->mmio + (0xa << 2)); 638 639 /* Set Rx squelch input filler bandwidth */ 640 writel(0x0e, priv->mmio + (0x14 << 2)); 641 642 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 643 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 644 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 645 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 646 break; 647 case PHY_TYPE_SATA: 648 writel(0x41, priv->mmio + 0x38); 649 writel(0x8F, priv->mmio + 0x18); 650 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 651 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 652 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 653 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 654 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 655 break; 656 case PHY_TYPE_SGMII: 657 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 658 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 659 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 660 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 661 break; 662 case PHY_TYPE_QSGMII: 663 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 664 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 665 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 666 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 667 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 668 break; 669 default: 670 pr_err("%s, phy-type %d\n", __func__, priv->mode); 671 return -EINVAL; 672 } 673 674 /* The default ref clock is 25Mhz */ 675 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 676 677 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 678 val = readl(priv->mmio + (0x7 << 2)); 679 val |= BIT(4); 680 writel(val, priv->mmio + (0x7 << 2)); 681 } 682 683 return 0; 684 } 685 686 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 687 /* pipe-phy-grf */ 688 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 689 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 690 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 691 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 692 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 693 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 694 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 695 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 696 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 697 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 698 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 699 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 700 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 701 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 702 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 703 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 704 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 705 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 706 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 707 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 708 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 709 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 710 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 711 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 712 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 713 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 714 /* pipe-grf */ 715 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 716 .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, 717 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 718 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 719 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 720 }; 721 722 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 723 .grfcfg = &rk3568_combphy_grfcfgs, 724 .combphy_cfg = rk3568_combphy_cfg, 725 }; 726 727 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 728 { 729 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 730 u32 val; 731 732 switch (priv->mode) { 733 case PHY_TYPE_PCIE: 734 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 735 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 736 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 737 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 738 break; 739 case PHY_TYPE_USB3: 740 /* Set SSC downward spread spectrum */ 741 val = readl(priv->mmio + (0x1f << 2)); 742 val &= ~GENMASK(5, 4); 743 val |= 0x01 << 4; 744 writel(val, priv->mmio + 0x7c); 745 746 /* Enable adaptive CTLE for USB3.0 Rx */ 747 val = readl(priv->mmio + (0x0e << 2)); 748 val &= ~GENMASK(0, 0); 749 val |= 0x01; 750 writel(val, priv->mmio + (0x0e << 2)); 751 752 /* Set PLL KVCO fine tuning signals */ 753 val = readl(priv->mmio + (0x20 << 2)); 754 val &= ~(0x7 << 2); 755 val |= 0x2 << 2; 756 writel(val, priv->mmio + (0x20 << 2)); 757 758 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 759 writel(0x4, priv->mmio + (0xb << 2)); 760 761 /* Set PLL input clock divider 1/2 */ 762 val = readl(priv->mmio + (0x5 << 2)); 763 val &= ~(0x3 << 6); 764 val |= 0x1 << 6; 765 writel(val, priv->mmio + (0x5 << 2)); 766 767 /* Set PLL loop divider */ 768 writel(0x32, priv->mmio + (0x11 << 2)); 769 770 /* Set PLL KVCO to min and set PLL charge pump current to max */ 771 writel(0xf0, priv->mmio + (0xa << 2)); 772 773 /* Set Rx squelch input filler bandwidth */ 774 writel(0x0d, priv->mmio + (0x14 << 2)); 775 776 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 777 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 778 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 779 break; 780 case PHY_TYPE_SATA: 781 /* Enable adaptive CTLE for SATA Rx */ 782 val = readl(priv->mmio + (0x0e << 2)); 783 val &= ~GENMASK(0, 0); 784 val |= 0x01; 785 writel(val, priv->mmio + (0x0e << 2)); 786 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 787 writel(0x8F, priv->mmio + (0x06 << 2)); 788 789 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 790 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 791 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 792 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 793 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 794 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 795 break; 796 case PHY_TYPE_SGMII: 797 case PHY_TYPE_QSGMII: 798 default: 799 dev_err(priv->dev, "incompatible PHY type\n"); 800 return -EINVAL; 801 } 802 803 /* 100MHz refclock signal is good */ 804 clk_set_rate(&priv->ref_clk, 100000000); 805 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 806 if (priv->mode == PHY_TYPE_PCIE) { 807 /* PLL KVCO tuning fine */ 808 val = readl(priv->mmio + (0x20 << 2)); 809 val &= ~GENMASK(4, 2); 810 val |= 0x4 << 2; 811 writel(val, priv->mmio + (0x20 << 2)); 812 813 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 814 val = 0x4c; 815 writel(val, priv->mmio + (0x1b << 2)); 816 817 /* Set up su_trim: T3 */ 818 val = 0xb0; 819 writel(val, priv->mmio + (0xa << 2)); 820 val = 0x47; 821 writel(val, priv->mmio + (0xb << 2)); 822 val = 0x57; 823 writel(val, priv->mmio + (0xd << 2)); 824 } 825 826 return 0; 827 } 828 829 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 830 /* pipe-phy-grf */ 831 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 832 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 833 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 834 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 835 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 836 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 837 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 838 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 839 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 840 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 841 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 842 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 843 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 844 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 845 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 846 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 847 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 848 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 849 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 850 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 851 /* pipe-grf */ 852 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 853 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 854 }; 855 856 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 857 .grfcfg = &rk3588_combphy_grfcfgs, 858 .combphy_cfg = rk3588_combphy_cfg, 859 }; 860 861 static const struct udevice_id rockchip_combphy_ids[] = { 862 { 863 .compatible = "rockchip,rk3528-naneng-combphy", 864 .data = (ulong)&rk3528_combphy_cfgs 865 }, 866 { 867 .compatible = "rockchip,rk3562-naneng-combphy", 868 .data = (ulong)&rk3562_combphy_cfgs 869 }, 870 { 871 .compatible = "rockchip,rk3568-naneng-combphy", 872 .data = (ulong)&rk3568_combphy_cfgs 873 }, 874 { 875 .compatible = "rockchip,rk3588-naneng-combphy", 876 .data = (ulong)&rk3588_combphy_cfgs 877 }, 878 { } 879 }; 880 881 U_BOOT_DRIVER(rockchip_naneng_combphy) = { 882 .name = "naneng-combphy", 883 .id = UCLASS_PHY, 884 .of_match = rockchip_combphy_ids, 885 .ops = &rochchip_combphy_ops, 886 .probe = rockchip_combphy_probe, 887 .priv_auto_alloc_size = sizeof(struct rockchip_combphy_priv), 888 }; 889