1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dm/uclass-internal.h> 13 #include <dt-bindings/phy/phy.h> 14 #include <generic-phy.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <regmap.h> 19 #include <reset-uclass.h> 20 #include <linux/iopoll.h> 21 22 #define BIT_WRITEABLE_SHIFT 16 23 24 struct rockchip_combphy_priv; 25 26 struct combphy_reg { 27 u32 offset; 28 u16 bitend; 29 u16 bitstart; 30 u16 disable; 31 u16 enable; 32 }; 33 34 struct rockchip_combphy_grfcfg { 35 struct combphy_reg pcie_mode_set; 36 struct combphy_reg usb_mode_set; 37 struct combphy_reg sgmii_mode_set; 38 struct combphy_reg qsgmii_mode_set; 39 struct combphy_reg pipe_rxterm_set; 40 struct combphy_reg pipe_txelec_set; 41 struct combphy_reg pipe_txcomp_set; 42 struct combphy_reg pipe_clk_24m; 43 struct combphy_reg pipe_clk_25m; 44 struct combphy_reg pipe_clk_100m; 45 struct combphy_reg pipe_phymode_sel; 46 struct combphy_reg pipe_rate_sel; 47 struct combphy_reg pipe_rxterm_sel; 48 struct combphy_reg pipe_txelec_sel; 49 struct combphy_reg pipe_txcomp_sel; 50 struct combphy_reg pipe_clk_ext; 51 struct combphy_reg pipe_sel_usb; 52 struct combphy_reg pipe_sel_qsgmii; 53 struct combphy_reg pipe_phy_status; 54 struct combphy_reg con0_for_pcie; 55 struct combphy_reg con1_for_pcie; 56 struct combphy_reg con2_for_pcie; 57 struct combphy_reg con3_for_pcie; 58 struct combphy_reg con0_for_sata; 59 struct combphy_reg con1_for_sata; 60 struct combphy_reg con2_for_sata; 61 struct combphy_reg con3_for_sata; 62 struct combphy_reg pipe_con0_for_sata; 63 struct combphy_reg pipe_con1_for_sata; 64 struct combphy_reg pipe_sgmii_mac_sel; 65 struct combphy_reg pipe_xpcs_phy_ready; 66 struct combphy_reg u3otg0_port_en; 67 struct combphy_reg u3otg1_port_en; 68 struct combphy_reg u3otg0_pipe_clk_sel; 69 struct combphy_reg pipe_phy_grf_reset; 70 }; 71 72 struct rockchip_combphy_cfg { 73 const struct rockchip_combphy_grfcfg *grfcfg; 74 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 75 }; 76 77 struct rockchip_combphy_priv { 78 u32 mode; 79 void __iomem *mmio; 80 struct udevice *dev; 81 struct regmap *pipe_grf; 82 struct regmap *phy_grf; 83 struct phy *phy; 84 struct reset_ctl phy_rst; 85 struct clk ref_clk; 86 const struct rockchip_combphy_cfg *cfg; 87 }; 88 89 static int param_write(struct regmap *base, 90 const struct combphy_reg *reg, bool en) 91 { 92 u32 val, mask, tmp; 93 94 tmp = en ? reg->enable : reg->disable; 95 mask = GENMASK(reg->bitend, reg->bitstart); 96 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 97 98 return regmap_write(base, reg->offset, val); 99 } 100 101 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) 102 { 103 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 104 u32 mask, val; 105 106 mask = GENMASK(cfg->pipe_phy_status.bitend, 107 cfg->pipe_phy_status.bitstart); 108 109 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); 110 val = (val & mask) >> cfg->pipe_phy_status.bitstart; 111 112 return val; 113 } 114 115 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) 116 { 117 int ret = 0; 118 119 if (priv->cfg->combphy_cfg) { 120 ret = priv->cfg->combphy_cfg(priv); 121 if (ret) { 122 dev_err(priv->dev, "failed to init phy for pcie\n"); 123 return ret; 124 } 125 } 126 127 return ret; 128 } 129 130 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) 131 { 132 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 133 int ret = 0; 134 135 if (dev_read_bool(priv->dev, "rockchip,dis-u3otg0-port")) { 136 ret = param_write(priv->pipe_grf, &cfg->u3otg0_port_en, false); 137 return ret; 138 } else if (dev_read_bool(priv->dev, "rockchip,dis-u3otg1-port")) { 139 param_write(priv->pipe_grf, &cfg->u3otg1_port_en, false); 140 #ifdef CONFIG_ROCKCHIP_RK3576 141 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 142 #endif 143 return ret; 144 } 145 146 if (priv->cfg->combphy_cfg) { 147 ret = priv->cfg->combphy_cfg(priv); 148 if (ret) { 149 dev_err(priv->dev, "failed to init phy for usb3\n"); 150 return ret; 151 } 152 } 153 154 return ret; 155 } 156 157 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) 158 { 159 int ret = 0; 160 161 if (priv->cfg->combphy_cfg) { 162 ret = priv->cfg->combphy_cfg(priv); 163 if (ret) { 164 dev_err(priv->dev, "failed to init phy for sata\n"); 165 return ret; 166 } 167 } 168 169 return ret; 170 } 171 172 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) 173 { 174 int ret = 0; 175 176 if (priv->cfg->combphy_cfg) { 177 ret = priv->cfg->combphy_cfg(priv); 178 if (ret) { 179 dev_err(priv->dev, "failed to init phy for sgmii\n"); 180 return ret; 181 } 182 } 183 184 return ret; 185 } 186 187 int rockchip_combphy_usb3_uboot_init(fdt_addr_t phy_addr) 188 { 189 struct udevice *udev = NULL; 190 struct udevice *dev; 191 struct uclass *uc; 192 const struct driver *find_drv; 193 struct rockchip_combphy_priv *priv; 194 const struct rockchip_combphy_grfcfg *cfg; 195 u32 val; 196 int ret = 0; 197 198 ret = uclass_get(UCLASS_PHY, &uc); 199 if (ret) 200 return ret; 201 202 find_drv = DM_GET_DRIVER(rockchip_naneng_combphy); 203 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 204 if (dev->driver == find_drv && dev_read_addr(dev) == phy_addr) { 205 ret = uclass_get_device_tail(dev, 0, &udev); 206 break; 207 } 208 } 209 210 if (!udev || ret) { 211 ret = ret ? ret : -ENODEV; 212 pr_err("%s: get usb3-phy node failed: %d\n", __func__, ret); 213 return ret; 214 } 215 216 priv = dev_get_priv(udev); 217 priv->mode = PHY_TYPE_USB3; 218 cfg = priv->cfg->grfcfg; 219 220 rockchip_combphy_usb3_init(priv); 221 reset_deassert(&priv->phy_rst); 222 223 if (cfg->pipe_phy_grf_reset.enable) 224 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 225 226 if (priv->mode == PHY_TYPE_USB3) { 227 ret = readx_poll_timeout(rockchip_combphy_is_ready, 228 priv, val, 229 val == cfg->pipe_phy_status.enable, 230 1000); 231 if (ret) { 232 dev_err(priv->dev, "wait phy status ready timeout\n"); 233 param_write(priv->phy_grf, &cfg->usb_mode_set, false); 234 if (cfg->u3otg0_pipe_clk_sel.disable) 235 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, false); 236 return ret; 237 } 238 } 239 240 /* Select clk_usb3otg0_pipe for source clk */ 241 if (cfg->u3otg0_pipe_clk_sel.disable) 242 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, true); 243 244 return ret; 245 } 246 247 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) 248 { 249 switch (priv->mode) { 250 case PHY_TYPE_PCIE: 251 rockchip_combphy_pcie_init(priv); 252 break; 253 case PHY_TYPE_USB3: 254 rockchip_combphy_usb3_init(priv); 255 break; 256 case PHY_TYPE_SATA: 257 rockchip_combphy_sata_init(priv); 258 break; 259 case PHY_TYPE_SGMII: 260 case PHY_TYPE_QSGMII: 261 return rockchip_combphy_sgmii_init(priv); 262 default: 263 dev_err(priv->dev, "incompatible PHY type\n"); 264 return -EINVAL; 265 } 266 267 return 0; 268 } 269 270 static int rockchip_combphy_init(struct phy *phy) 271 { 272 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 273 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 274 int ret; 275 276 ret = clk_enable(&priv->ref_clk); 277 if (ret < 0 && ret != -ENOSYS) 278 return ret; 279 280 ret = rockchip_combphy_set_mode(priv); 281 if (ret) 282 goto err_clk; 283 284 reset_deassert(&priv->phy_rst); 285 286 if (cfg->pipe_phy_grf_reset.enable) 287 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 288 289 return 0; 290 291 err_clk: 292 clk_disable(&priv->ref_clk); 293 294 return ret; 295 } 296 297 static int rockchip_combphy_exit(struct phy *phy) 298 { 299 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 300 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 301 302 if (cfg->pipe_phy_grf_reset.enable) 303 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); 304 305 reset_assert(&priv->phy_rst); 306 clk_disable(&priv->ref_clk); 307 308 return 0; 309 } 310 311 static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) 312 { 313 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 314 315 if (args->args_count != 1) { 316 pr_err("invalid number of arguments\n"); 317 return -EINVAL; 318 } 319 320 priv->mode = args->args[0]; 321 322 return 0; 323 } 324 325 static const struct phy_ops rochchip_combphy_ops = { 326 .init = rockchip_combphy_init, 327 .exit = rockchip_combphy_exit, 328 .of_xlate = rockchip_combphy_xlate, 329 }; 330 331 static int rockchip_combphy_parse_dt(struct udevice *dev, 332 struct rockchip_combphy_priv *priv) 333 { 334 struct udevice *syscon; 335 int ret; 336 u32 vals[4]; 337 338 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); 339 if (ret) { 340 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap ret= %d\n", ret); 341 return ret; 342 } 343 priv->pipe_grf = syscon_get_regmap(syscon); 344 345 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); 346 if (ret) { 347 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 348 return ret; 349 } 350 priv->phy_grf = syscon_get_regmap(syscon); 351 352 ret = clk_get_by_index(dev, 0, &priv->ref_clk); 353 if (ret) { 354 dev_err(dev, "failed to find ref clock\n"); 355 return PTR_ERR(&priv->ref_clk); 356 } 357 358 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); 359 if (ret) { 360 dev_err(dev, "no phy reset control specified\n"); 361 return ret; 362 } 363 364 if (!dev_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", 365 vals, ARRAY_SIZE(vals))) 366 regmap_write(priv->pipe_grf, vals[0], 367 (GENMASK(vals[2], vals[1]) << 16) | vals[3]); 368 369 return 0; 370 } 371 372 static int rockchip_combphy_probe(struct udevice *udev) 373 { 374 struct rockchip_combphy_priv *priv = dev_get_priv(udev); 375 const struct rockchip_combphy_cfg *phy_cfg; 376 377 priv->mmio = (void __iomem *)dev_read_addr(udev); 378 if (IS_ERR(priv->mmio)) 379 return PTR_ERR(priv->mmio); 380 381 phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); 382 if (!phy_cfg) { 383 dev_err(udev, "No OF match data provided\n"); 384 return -EINVAL; 385 } 386 387 priv->dev = udev; 388 priv->mode = PHY_TYPE_SATA; 389 priv->cfg = phy_cfg; 390 391 return rockchip_combphy_parse_dt(udev, priv); 392 } 393 394 #ifdef CONFIG_ROCKCHIP_RK3528 395 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) 396 { 397 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 398 u32 val; 399 400 switch (priv->mode) { 401 case PHY_TYPE_PCIE: 402 /* Set SSC downward spread spectrum */ 403 val = readl(priv->mmio + 0x18); 404 val &= ~GENMASK(5, 4); 405 val |= 0x01 << 4; 406 writel(val, priv->mmio + 0x18); 407 408 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 409 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 410 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 411 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 412 break; 413 case PHY_TYPE_USB3: 414 /* Set SSC downward spread spectrum */ 415 val = readl(priv->mmio + 0x18); 416 val &= ~GENMASK(5, 4); 417 val |= 0x01 << 4; 418 writel(val, priv->mmio + 0x18); 419 420 /* Enable adaptive CTLE for USB3.0 Rx */ 421 val = readl(priv->mmio + 0x200); 422 val &= ~GENMASK(17, 17); 423 val |= 0x01; 424 writel(val, priv->mmio + 0x200); 425 426 /* Set Rx squelch input filler bandwidth */ 427 val = readl(priv->mmio + 0x20c); 428 val &= ~GENMASK(2, 0); 429 val |= 0x06; 430 writel(val, priv->mmio + 0x20c); 431 432 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 433 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 434 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 435 break; 436 default: 437 dev_err(priv->dev, "incompatible PHY type\n"); 438 return -EINVAL; 439 } 440 441 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 442 if (priv->mode == PHY_TYPE_PCIE) { 443 /* PLL KVCO tuning fine */ 444 val = readl(priv->mmio + 0x18); 445 val &= ~(0x7 << 10); 446 val |= 0x2 << 10; 447 writel(val, priv->mmio + 0x18); 448 449 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ 450 val = readl(priv->mmio + 0x108); 451 val &= ~(0x7f7); 452 val |= 0x4f0; 453 writel(val, priv->mmio + 0x108); 454 } 455 456 return 0; 457 } 458 459 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { 460 /* pipe-phy-grf */ 461 .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 }, 462 .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 }, 463 .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 }, 464 .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 }, 465 .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 }, 466 .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 }, 467 .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 }, 468 .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 }, 469 .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 }, 470 .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 }, 471 .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 }, 472 .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 }, 473 .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 }, 474 .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 }, 475 .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 }, 476 .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 }, 477 /* pipe-grf */ 478 .u3otg0_pipe_clk_sel = { 0x40044, 7, 7, 0x01, 0x00 }, 479 .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 }, 480 }; 481 482 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { 483 .grfcfg = &rk3528_combphy_grfcfgs, 484 .combphy_cfg = rk3528_combphy_cfg, 485 }; 486 #endif 487 488 #ifdef CONFIG_ROCKCHIP_RK3562 489 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) 490 { 491 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 492 u32 val; 493 494 switch (priv->mode) { 495 case PHY_TYPE_PCIE: 496 /* Set SSC downward spread spectrum */ 497 val = readl(priv->mmio + (0x1f << 2)); 498 val &= ~GENMASK(5, 4); 499 val |= 0x01 << 4; 500 writel(val, priv->mmio + 0x7c); 501 502 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 503 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 504 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 505 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 506 break; 507 case PHY_TYPE_USB3: 508 /* Set SSC downward spread spectrum */ 509 val = readl(priv->mmio + (0x1f << 2)); 510 val &= ~GENMASK(5, 4); 511 val |= 0x01 << 4; 512 writel(val, priv->mmio + 0x7c); 513 514 /* Enable adaptive CTLE for USB3.0 Rx */ 515 val = readl(priv->mmio + (0x0e << 2)); 516 val &= ~GENMASK(0, 0); 517 val |= 0x01; 518 writel(val, priv->mmio + (0x0e << 2)); 519 520 /* Set PLL KVCO fine tuning signals */ 521 val = readl(priv->mmio + (0x20 << 2)); 522 val &= ~(0x7 << 2); 523 val |= 0x2 << 2; 524 writel(val, priv->mmio + (0x20 << 2)); 525 526 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 527 writel(0x4, priv->mmio + (0xb << 2)); 528 529 /* Set PLL input clock divider 1/2 */ 530 val = readl(priv->mmio + (0x5 << 2)); 531 val &= ~(0x3 << 6); 532 val |= 0x1 << 6; 533 writel(val, priv->mmio + (0x5 << 2)); 534 535 /* Set PLL loop divider */ 536 writel(0x32, priv->mmio + (0x11 << 2)); 537 538 /* Set PLL KVCO to min and set PLL charge pump current to max */ 539 writel(0xf0, priv->mmio + (0xa << 2)); 540 541 /* Set Rx squelch input filler bandwidth */ 542 writel(0x0e, priv->mmio + (0x14 << 2)); 543 544 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 545 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 546 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 547 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 548 break; 549 default: 550 pr_err("%s, phy-type %d\n", __func__, priv->mode); 551 return -EINVAL; 552 } 553 554 clk_set_rate(&priv->ref_clk, 100000000); 555 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 556 557 if (priv->mode == PHY_TYPE_PCIE) { 558 /* PLL KVCO tuning fine */ 559 val = readl(priv->mmio + (0x20 << 2)); 560 val &= ~(0x7 << 2); 561 val |= 0x2 << 2; 562 writel(val, priv->mmio + (0x20 << 2)); 563 564 /* Enable controlling random jitter, aka RMJ */ 565 writel(0x4, priv->mmio + (0xb << 2)); 566 567 val = readl(priv->mmio + (0x5 << 2)); 568 val &= ~(0x3 << 6); 569 val |= 0x1 << 6; 570 writel(val, priv->mmio + (0x5 << 2)); 571 572 writel(0x32, priv->mmio + (0x11 << 2)); 573 writel(0xf0, priv->mmio + (0xa << 2)); 574 } 575 576 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 577 val = readl(priv->mmio + (0x7 << 2)); 578 val |= BIT(4); 579 writel(val, priv->mmio + (0x7 << 2)); 580 } 581 582 return 0; 583 } 584 585 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { 586 /* pipe-phy-grf */ 587 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 588 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 589 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 590 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 591 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 592 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 593 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 594 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 595 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 596 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 597 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 598 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 599 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 600 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 601 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 602 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 603 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 604 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 605 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 606 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 607 /* pipe-grf */ 608 .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 }, 609 }; 610 611 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { 612 .grfcfg = &rk3562_combphy_grfcfgs, 613 .combphy_cfg = rk3562_combphy_cfg, 614 }; 615 #endif 616 617 #ifdef CONFIG_ROCKCHIP_RK3568 618 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 619 { 620 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 621 u32 val; 622 623 switch (priv->mode) { 624 case PHY_TYPE_PCIE: 625 /* Set SSC downward spread spectrum */ 626 val = readl(priv->mmio + (0x1f << 2)); 627 val &= ~GENMASK(5, 4); 628 val |= 0x01 << 4; 629 writel(val, priv->mmio + 0x7c); 630 631 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 632 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 633 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 634 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 635 break; 636 case PHY_TYPE_USB3: 637 /* Set SSC downward spread spectrum */ 638 val = readl(priv->mmio + (0x1f << 2)); 639 val &= ~GENMASK(5, 4); 640 val |= 0x01 << 4; 641 writel(val, priv->mmio + 0x7c); 642 643 /* Enable adaptive CTLE for USB3.0 Rx */ 644 val = readl(priv->mmio + (0x0e << 2)); 645 val &= ~GENMASK(0, 0); 646 val |= 0x01; 647 writel(val, priv->mmio + (0x0e << 2)); 648 649 /* Set PLL KVCO fine tuning signals */ 650 val = readl(priv->mmio + (0x20 << 2)); 651 val &= ~(0x7 << 2); 652 val |= 0x2 << 2; 653 writel(val, priv->mmio + (0x20 << 2)); 654 655 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 656 writel(0x4, priv->mmio + (0xb << 2)); 657 658 /* Set PLL input clock divider 1/2 */ 659 val = readl(priv->mmio + (0x5 << 2)); 660 val &= ~(0x3 << 6); 661 val |= 0x1 << 6; 662 writel(val, priv->mmio + (0x5 << 2)); 663 664 /* Set PLL loop divider */ 665 writel(0x32, priv->mmio + (0x11 << 2)); 666 667 /* Set PLL KVCO to min and set PLL charge pump current to max */ 668 writel(0xf0, priv->mmio + (0xa << 2)); 669 670 /* Set Rx squelch input filler bandwidth */ 671 writel(0x0e, priv->mmio + (0x14 << 2)); 672 673 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 674 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 675 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 676 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 677 break; 678 case PHY_TYPE_SATA: 679 writel(0x41, priv->mmio + 0x38); 680 writel(0x8F, priv->mmio + 0x18); 681 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 682 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 683 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 684 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 685 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 686 break; 687 case PHY_TYPE_SGMII: 688 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 689 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 690 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 691 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 692 break; 693 case PHY_TYPE_QSGMII: 694 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 695 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 696 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 697 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 698 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 699 break; 700 default: 701 pr_err("%s, phy-type %d\n", __func__, priv->mode); 702 return -EINVAL; 703 } 704 705 /* The default ref clock is 25Mhz */ 706 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 707 708 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 709 val = readl(priv->mmio + (0x7 << 2)); 710 val |= BIT(4); 711 writel(val, priv->mmio + (0x7 << 2)); 712 } 713 714 return 0; 715 } 716 717 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 718 /* pipe-phy-grf */ 719 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 720 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 721 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 722 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 723 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 724 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 725 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 726 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 727 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 728 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 729 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 730 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 731 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 732 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 733 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 734 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 735 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 736 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 737 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 738 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 739 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 740 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 741 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 742 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 743 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 744 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 745 /* pipe-grf */ 746 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 747 .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, 748 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 749 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 750 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 751 }; 752 753 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 754 .grfcfg = &rk3568_combphy_grfcfgs, 755 .combphy_cfg = rk3568_combphy_cfg, 756 }; 757 #endif 758 759 #ifdef CONFIG_ROCKCHIP_RK3588 760 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 761 { 762 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 763 u32 val; 764 765 switch (priv->mode) { 766 case PHY_TYPE_PCIE: 767 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 768 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 769 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 770 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 771 break; 772 case PHY_TYPE_USB3: 773 /* Set SSC downward spread spectrum */ 774 val = readl(priv->mmio + (0x1f << 2)); 775 val &= ~GENMASK(5, 4); 776 val |= 0x01 << 4; 777 writel(val, priv->mmio + 0x7c); 778 779 /* Enable adaptive CTLE for USB3.0 Rx */ 780 val = readl(priv->mmio + (0x0e << 2)); 781 val &= ~GENMASK(0, 0); 782 val |= 0x01; 783 writel(val, priv->mmio + (0x0e << 2)); 784 785 /* Set PLL KVCO fine tuning signals */ 786 val = readl(priv->mmio + (0x20 << 2)); 787 val &= ~(0x7 << 2); 788 val |= 0x2 << 2; 789 writel(val, priv->mmio + (0x20 << 2)); 790 791 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 792 writel(0x4, priv->mmio + (0xb << 2)); 793 794 /* Set PLL input clock divider 1/2 */ 795 val = readl(priv->mmio + (0x5 << 2)); 796 val &= ~(0x3 << 6); 797 val |= 0x1 << 6; 798 writel(val, priv->mmio + (0x5 << 2)); 799 800 /* Set PLL loop divider */ 801 writel(0x32, priv->mmio + (0x11 << 2)); 802 803 /* Set PLL KVCO to min and set PLL charge pump current to max */ 804 writel(0xf0, priv->mmio + (0xa << 2)); 805 806 /* Set Rx squelch input filler bandwidth */ 807 writel(0x0d, priv->mmio + (0x14 << 2)); 808 809 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 810 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 811 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 812 break; 813 case PHY_TYPE_SATA: 814 /* Enable adaptive CTLE for SATA Rx */ 815 val = readl(priv->mmio + (0x0e << 2)); 816 val &= ~GENMASK(0, 0); 817 val |= 0x01; 818 writel(val, priv->mmio + (0x0e << 2)); 819 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 820 writel(0x8F, priv->mmio + (0x06 << 2)); 821 822 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 823 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 824 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 825 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 826 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 827 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 828 break; 829 case PHY_TYPE_SGMII: 830 case PHY_TYPE_QSGMII: 831 default: 832 dev_err(priv->dev, "incompatible PHY type\n"); 833 return -EINVAL; 834 } 835 836 /* 100MHz refclock signal is good */ 837 clk_set_rate(&priv->ref_clk, 100000000); 838 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 839 if (priv->mode == PHY_TYPE_PCIE) { 840 /* PLL KVCO tuning fine */ 841 val = readl(priv->mmio + (0x20 << 2)); 842 val &= ~GENMASK(4, 2); 843 val |= 0x4 << 2; 844 writel(val, priv->mmio + (0x20 << 2)); 845 846 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 847 val = 0x4c; 848 writel(val, priv->mmio + (0x1b << 2)); 849 850 /* Set up su_trim: T3 */ 851 val = 0xb0; 852 writel(val, priv->mmio + (0xa << 2)); 853 val = 0x47; 854 writel(val, priv->mmio + (0xb << 2)); 855 val = 0x57; 856 writel(val, priv->mmio + (0xd << 2)); 857 } 858 859 return 0; 860 } 861 862 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 863 /* pipe-phy-grf */ 864 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 865 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 866 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 867 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 868 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 869 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 870 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 871 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 872 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 873 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 874 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 875 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 876 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 877 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 878 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 879 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 880 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 881 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 882 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 883 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 884 /* pipe-grf */ 885 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 886 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 887 }; 888 889 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 890 .grfcfg = &rk3588_combphy_grfcfgs, 891 .combphy_cfg = rk3588_combphy_cfg, 892 }; 893 #endif 894 895 896 #ifdef CONFIG_ROCKCHIP_RK3576 897 static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) 898 { 899 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 900 u32 val; 901 902 switch (priv->mode) { 903 case PHY_TYPE_PCIE: 904 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 905 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 906 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 907 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 908 break; 909 case PHY_TYPE_USB3: 910 /* Set SSC downward spread spectrum */ 911 val = readl(priv->mmio + (0x1f << 2)); 912 val &= ~GENMASK(5, 4); 913 val |= 0x01 << 4; 914 writel(val, priv->mmio + 0x7c); 915 916 /* Enable adaptive CTLE for USB3.0 Rx */ 917 val = readl(priv->mmio + (0x0e << 2)); 918 val &= ~GENMASK(0, 0); 919 val |= 0x01; 920 writel(val, priv->mmio + (0x0e << 2)); 921 922 /* Set PLL KVCO fine tuning signals */ 923 val = readl(priv->mmio + (0x20 << 2)); 924 val &= ~(0x7 << 2); 925 val |= 0x2 << 2; 926 writel(val, priv->mmio + (0x20 << 2)); 927 928 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 929 writel(0x4, priv->mmio + (0xb << 2)); 930 931 /* Set PLL input clock divider 1/2 */ 932 val = readl(priv->mmio + (0x5 << 2)); 933 val &= ~(0x3 << 6); 934 val |= 0x1 << 6; 935 writel(val, priv->mmio + (0x5 << 2)); 936 937 /* Set PLL loop divider */ 938 writel(0x32, priv->mmio + (0x11 << 2)); 939 940 /* Set PLL KVCO to min and set PLL charge pump current to max */ 941 writel(0xf0, priv->mmio + (0xa << 2)); 942 943 /* Set Rx squelch input filler bandwidth */ 944 writel(0x0d, priv->mmio + (0x14 << 2)); 945 946 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 947 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 948 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 949 break; 950 case PHY_TYPE_SATA: 951 /* Enable adaptive CTLE for SATA Rx */ 952 val = readl(priv->mmio + (0x0e << 2)); 953 val &= ~GENMASK(0, 0); 954 val |= 0x01; 955 writel(val, priv->mmio + (0x0e << 2)); 956 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 957 writel(0x8F, priv->mmio + (0x06 << 2)); 958 959 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 960 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 961 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 962 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 963 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 964 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 965 break; 966 case PHY_TYPE_SGMII: 967 case PHY_TYPE_QSGMII: 968 default: 969 dev_err(priv->dev, "incompatible PHY type\n"); 970 return -EINVAL; 971 } 972 973 /* 100MHz refclock signal is good */ 974 clk_set_rate(&priv->ref_clk, 100000000); 975 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 976 if (priv->mode == PHY_TYPE_PCIE) { 977 /* gate_tx_pck_sel length select work for L1SS */ 978 writel(0xc0, priv->mmio + 0x74); 979 980 /* PLL KVCO tuning fine */ 981 val = readl(priv->mmio + (0x20 << 2)); 982 val &= ~(0x7 << 2); 983 val |= 0x2 << 2; 984 writel(val, priv->mmio + (0x20 << 2)); 985 986 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 987 writel(0x4c, priv->mmio + (0x1b << 2)); 988 989 /* Set up su_trim: T3_P1 650mv */ 990 writel(0x90, priv->mmio + (0xa << 2)); 991 writel(0x43, priv->mmio + (0xb << 2)); 992 writel(0x88, priv->mmio + (0xc << 2)); 993 writel(0x56, priv->mmio + (0xd << 2)); 994 } 995 996 return 0; 997 } 998 999 static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { 1000 /* pipe-phy-grf */ 1001 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 1002 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 1003 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 1004 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 1005 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 1006 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, 1007 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 1008 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 1009 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 1010 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 1011 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 1012 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 1013 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 1014 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 1015 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 1016 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 1017 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 1018 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 1019 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 1020 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 1021 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 1022 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 1023 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 1024 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 1025 /* php-grf */ 1026 .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, 1027 .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, 1028 .u3otg1_port_en = { 0x0038, 15, 0, 0x0181, 0x1100 }, 1029 }; 1030 1031 static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { 1032 .grfcfg = &rk3576_combphy_grfcfgs, 1033 .combphy_cfg = rk3576_combphy_cfg, 1034 }; 1035 #endif 1036 1037 static const struct udevice_id rockchip_combphy_ids[] = { 1038 #ifdef CONFIG_ROCKCHIP_RK3528 1039 { 1040 .compatible = "rockchip,rk3528-naneng-combphy", 1041 .data = (ulong)&rk3528_combphy_cfgs 1042 }, 1043 #endif 1044 #ifdef CONFIG_ROCKCHIP_RK3562 1045 { 1046 .compatible = "rockchip,rk3562-naneng-combphy", 1047 .data = (ulong)&rk3562_combphy_cfgs 1048 }, 1049 #endif 1050 #ifdef CONFIG_ROCKCHIP_RK3568 1051 { 1052 .compatible = "rockchip,rk3568-naneng-combphy", 1053 .data = (ulong)&rk3568_combphy_cfgs 1054 }, 1055 #endif 1056 #ifdef CONFIG_ROCKCHIP_RK3588 1057 { 1058 .compatible = "rockchip,rk3588-naneng-combphy", 1059 .data = (ulong)&rk3588_combphy_cfgs 1060 }, 1061 #endif 1062 #ifdef CONFIG_ROCKCHIP_RK3576 1063 { 1064 .compatible = "rockchip,rk3576-naneng-combphy", 1065 .data = (ulong)&rk3576_combphy_cfgs 1066 }, 1067 #endif 1068 { } 1069 }; 1070 1071 U_BOOT_DRIVER(rockchip_naneng_combphy) = { 1072 .name = "naneng-combphy", 1073 .id = UCLASS_PHY, 1074 .of_match = rockchip_combphy_ids, 1075 .ops = &rochchip_combphy_ops, 1076 .probe = rockchip_combphy_probe, 1077 .priv_auto_alloc_size = sizeof(struct rockchip_combphy_priv), 1078 }; 1079