1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dm/uclass-internal.h> 13 #include <dt-bindings/phy/phy.h> 14 #include <generic-phy.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <regmap.h> 19 #include <reset-uclass.h> 20 #include <linux/iopoll.h> 21 22 #define BIT_WRITEABLE_SHIFT 16 23 24 struct rockchip_combphy_priv; 25 26 struct combphy_reg { 27 u32 offset; 28 u16 bitend; 29 u16 bitstart; 30 u16 disable; 31 u16 enable; 32 }; 33 34 struct rockchip_combphy_grfcfg { 35 struct combphy_reg pcie_mode_set; 36 struct combphy_reg usb_mode_set; 37 struct combphy_reg sgmii_mode_set; 38 struct combphy_reg qsgmii_mode_set; 39 struct combphy_reg pipe_rxterm_set; 40 struct combphy_reg pipe_txelec_set; 41 struct combphy_reg pipe_txcomp_set; 42 struct combphy_reg pipe_clk_24m; 43 struct combphy_reg pipe_clk_25m; 44 struct combphy_reg pipe_clk_100m; 45 struct combphy_reg pipe_phymode_sel; 46 struct combphy_reg pipe_rate_sel; 47 struct combphy_reg pipe_rxterm_sel; 48 struct combphy_reg pipe_txelec_sel; 49 struct combphy_reg pipe_txcomp_sel; 50 struct combphy_reg pipe_clk_ext; 51 struct combphy_reg pipe_sel_usb; 52 struct combphy_reg pipe_sel_qsgmii; 53 struct combphy_reg pipe_phy_status; 54 struct combphy_reg con0_for_pcie; 55 struct combphy_reg con1_for_pcie; 56 struct combphy_reg con2_for_pcie; 57 struct combphy_reg con3_for_pcie; 58 struct combphy_reg con0_for_sata; 59 struct combphy_reg con1_for_sata; 60 struct combphy_reg con2_for_sata; 61 struct combphy_reg con3_for_sata; 62 struct combphy_reg pipe_con0_for_sata; 63 struct combphy_reg pipe_con1_for_sata; 64 struct combphy_reg pipe_sgmii_mac_sel; 65 struct combphy_reg pipe_xpcs_phy_ready; 66 struct combphy_reg u3otg0_port_en; 67 struct combphy_reg u3otg1_port_en; 68 struct combphy_reg u3otg0_pipe_clk_sel; 69 struct combphy_reg pipe_phy_grf_reset; 70 }; 71 72 struct rockchip_combphy_cfg { 73 const struct rockchip_combphy_grfcfg *grfcfg; 74 bool force_det_out; /* Tx detect Rx errata */ 75 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 76 }; 77 78 struct rockchip_combphy_priv { 79 u32 mode; 80 void __iomem *mmio; 81 struct udevice *dev; 82 struct regmap *pipe_grf; 83 struct regmap *phy_grf; 84 struct phy *phy; 85 struct reset_ctl phy_rst; 86 struct clk ref_clk; 87 const struct rockchip_combphy_cfg *cfg; 88 }; 89 90 static int param_write(struct regmap *base, 91 const struct combphy_reg *reg, bool en) 92 { 93 u32 val, mask, tmp; 94 95 tmp = en ? reg->enable : reg->disable; 96 mask = GENMASK(reg->bitend, reg->bitstart); 97 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 98 99 return regmap_write(base, reg->offset, val); 100 } 101 102 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) 103 { 104 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 105 u32 mask, val; 106 107 mask = GENMASK(cfg->pipe_phy_status.bitend, 108 cfg->pipe_phy_status.bitstart); 109 110 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); 111 val = (val & mask) >> cfg->pipe_phy_status.bitstart; 112 113 return val; 114 } 115 116 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) 117 { 118 int ret = 0; 119 u32 val; 120 121 if (priv->cfg->combphy_cfg) { 122 ret = priv->cfg->combphy_cfg(priv); 123 if (ret) { 124 dev_err(priv->dev, "failed to init phy for pcie\n"); 125 return ret; 126 } 127 } 128 129 if (priv->cfg->force_det_out) { 130 val = readl(priv->mmio + (0x19 << 2)); 131 val |= BIT(5); 132 writel(val, priv->mmio + (0x19 << 2)); 133 } 134 135 return ret; 136 } 137 138 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) 139 { 140 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 141 int ret = 0; 142 143 if (dev_read_bool(priv->dev, "rockchip,dis-u3otg0-port")) { 144 ret = param_write(priv->pipe_grf, &cfg->u3otg0_port_en, false); 145 return ret; 146 } else if (dev_read_bool(priv->dev, "rockchip,dis-u3otg1-port")) { 147 param_write(priv->pipe_grf, &cfg->u3otg1_port_en, false); 148 #ifdef CONFIG_ROCKCHIP_RK3576 149 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 150 #endif 151 return ret; 152 } 153 154 if (priv->cfg->combphy_cfg) { 155 ret = priv->cfg->combphy_cfg(priv); 156 if (ret) { 157 dev_err(priv->dev, "failed to init phy for usb3\n"); 158 return ret; 159 } 160 } 161 162 return ret; 163 } 164 165 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) 166 { 167 int ret = 0; 168 169 if (priv->cfg->combphy_cfg) { 170 ret = priv->cfg->combphy_cfg(priv); 171 if (ret) { 172 dev_err(priv->dev, "failed to init phy for sata\n"); 173 return ret; 174 } 175 } 176 177 return ret; 178 } 179 180 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) 181 { 182 int ret = 0; 183 184 if (priv->cfg->combphy_cfg) { 185 ret = priv->cfg->combphy_cfg(priv); 186 if (ret) { 187 dev_err(priv->dev, "failed to init phy for sgmii\n"); 188 return ret; 189 } 190 } 191 192 return ret; 193 } 194 195 int rockchip_combphy_usb3_uboot_init(fdt_addr_t phy_addr) 196 { 197 struct udevice *udev = NULL; 198 struct udevice *dev; 199 struct uclass *uc; 200 const struct driver *find_drv; 201 struct rockchip_combphy_priv *priv; 202 const struct rockchip_combphy_grfcfg *cfg; 203 u32 val; 204 int ret = 0; 205 206 ret = uclass_get(UCLASS_PHY, &uc); 207 if (ret) 208 return ret; 209 210 find_drv = DM_GET_DRIVER(rockchip_naneng_combphy); 211 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 212 if (dev->driver == find_drv && dev_read_addr(dev) == phy_addr) { 213 ret = uclass_get_device_tail(dev, 0, &udev); 214 break; 215 } 216 } 217 218 if (!udev || ret) { 219 ret = ret ? ret : -ENODEV; 220 pr_err("%s: get usb3-phy node failed: %d\n", __func__, ret); 221 return ret; 222 } 223 224 priv = dev_get_priv(udev); 225 priv->mode = PHY_TYPE_USB3; 226 cfg = priv->cfg->grfcfg; 227 228 rockchip_combphy_usb3_init(priv); 229 reset_deassert(&priv->phy_rst); 230 231 if (cfg->pipe_phy_grf_reset.enable) 232 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 233 234 if (priv->mode == PHY_TYPE_USB3) { 235 ret = readx_poll_timeout(rockchip_combphy_is_ready, 236 priv, val, 237 val == cfg->pipe_phy_status.enable, 238 1000); 239 if (ret) { 240 dev_err(priv->dev, "wait phy status ready timeout\n"); 241 param_write(priv->phy_grf, &cfg->usb_mode_set, false); 242 if (cfg->u3otg0_pipe_clk_sel.disable) 243 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, false); 244 return ret; 245 } 246 } 247 248 /* Select clk_usb3otg0_pipe for source clk */ 249 if (cfg->u3otg0_pipe_clk_sel.disable) 250 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, true); 251 252 return ret; 253 } 254 255 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) 256 { 257 switch (priv->mode) { 258 case PHY_TYPE_PCIE: 259 rockchip_combphy_pcie_init(priv); 260 break; 261 case PHY_TYPE_USB3: 262 rockchip_combphy_usb3_init(priv); 263 break; 264 case PHY_TYPE_SATA: 265 rockchip_combphy_sata_init(priv); 266 break; 267 case PHY_TYPE_SGMII: 268 case PHY_TYPE_QSGMII: 269 return rockchip_combphy_sgmii_init(priv); 270 default: 271 dev_err(priv->dev, "incompatible PHY type\n"); 272 return -EINVAL; 273 } 274 275 return 0; 276 } 277 278 static int rockchip_combphy_init(struct phy *phy) 279 { 280 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 281 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 282 int ret; 283 284 ret = clk_enable(&priv->ref_clk); 285 if (ret < 0 && ret != -ENOSYS) 286 return ret; 287 288 ret = rockchip_combphy_set_mode(priv); 289 if (ret) 290 goto err_clk; 291 292 reset_deassert(&priv->phy_rst); 293 294 if (cfg->pipe_phy_grf_reset.enable) 295 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 296 297 return 0; 298 299 err_clk: 300 clk_disable(&priv->ref_clk); 301 302 return ret; 303 } 304 305 static int rockchip_combphy_exit(struct phy *phy) 306 { 307 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 308 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 309 310 if (cfg->pipe_phy_grf_reset.enable) 311 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); 312 313 reset_assert(&priv->phy_rst); 314 clk_disable(&priv->ref_clk); 315 316 return 0; 317 } 318 319 static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) 320 { 321 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 322 323 if (args->args_count != 1) { 324 pr_err("invalid number of arguments\n"); 325 return -EINVAL; 326 } 327 328 priv->mode = args->args[0]; 329 330 return 0; 331 } 332 333 static const struct phy_ops rochchip_combphy_ops = { 334 .init = rockchip_combphy_init, 335 .exit = rockchip_combphy_exit, 336 .of_xlate = rockchip_combphy_xlate, 337 }; 338 339 static int rockchip_combphy_parse_dt(struct udevice *dev, 340 struct rockchip_combphy_priv *priv) 341 { 342 struct udevice *syscon; 343 int ret; 344 u32 vals[4]; 345 346 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); 347 if (ret) { 348 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap ret= %d\n", ret); 349 return ret; 350 } 351 priv->pipe_grf = syscon_get_regmap(syscon); 352 353 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); 354 if (ret) { 355 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 356 return ret; 357 } 358 priv->phy_grf = syscon_get_regmap(syscon); 359 360 ret = clk_get_by_index(dev, 0, &priv->ref_clk); 361 if (ret) { 362 dev_err(dev, "failed to find ref clock\n"); 363 return PTR_ERR(&priv->ref_clk); 364 } 365 366 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); 367 if (ret) { 368 dev_err(dev, "no phy reset control specified\n"); 369 return ret; 370 } 371 372 if (!dev_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", 373 vals, ARRAY_SIZE(vals))) 374 regmap_write(priv->pipe_grf, vals[0], 375 (GENMASK(vals[2], vals[1]) << 16) | vals[3]); 376 377 return 0; 378 } 379 380 static int rockchip_combphy_probe(struct udevice *udev) 381 { 382 struct rockchip_combphy_priv *priv = dev_get_priv(udev); 383 const struct rockchip_combphy_cfg *phy_cfg; 384 385 priv->mmio = (void __iomem *)dev_read_addr(udev); 386 if (IS_ERR(priv->mmio)) 387 return PTR_ERR(priv->mmio); 388 389 phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); 390 if (!phy_cfg) { 391 dev_err(udev, "No OF match data provided\n"); 392 return -EINVAL; 393 } 394 395 priv->dev = udev; 396 priv->mode = PHY_TYPE_SATA; 397 priv->cfg = phy_cfg; 398 399 return rockchip_combphy_parse_dt(udev, priv); 400 } 401 402 #ifdef CONFIG_ROCKCHIP_RK3528 403 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) 404 { 405 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 406 u32 val; 407 408 switch (priv->mode) { 409 case PHY_TYPE_PCIE: 410 /* Set SSC downward spread spectrum */ 411 val = readl(priv->mmio + 0x18); 412 val &= ~GENMASK(5, 4); 413 val |= 0x01 << 4; 414 writel(val, priv->mmio + 0x18); 415 416 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 417 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 418 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 419 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 420 break; 421 case PHY_TYPE_USB3: 422 /* Set SSC downward spread spectrum */ 423 val = readl(priv->mmio + 0x18); 424 val &= ~GENMASK(5, 4); 425 val |= 0x01 << 4; 426 writel(val, priv->mmio + 0x18); 427 428 /* Enable adaptive CTLE for USB3.0 Rx */ 429 val = readl(priv->mmio + 0x200); 430 val &= ~GENMASK(17, 17); 431 val |= 0x01; 432 writel(val, priv->mmio + 0x200); 433 434 /* Set Rx squelch input filler bandwidth */ 435 val = readl(priv->mmio + 0x20c); 436 val &= ~GENMASK(2, 0); 437 val |= 0x06; 438 writel(val, priv->mmio + 0x20c); 439 440 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 441 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 442 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 443 break; 444 default: 445 dev_err(priv->dev, "incompatible PHY type\n"); 446 return -EINVAL; 447 } 448 449 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 450 if (priv->mode == PHY_TYPE_PCIE) { 451 /* PLL KVCO tuning fine */ 452 val = readl(priv->mmio + 0x18); 453 val &= ~(0x7 << 10); 454 val |= 0x2 << 10; 455 writel(val, priv->mmio + 0x18); 456 457 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ 458 val = readl(priv->mmio + 0x108); 459 val &= ~(0x7f7); 460 val |= 0x4f0; 461 writel(val, priv->mmio + 0x108); 462 } 463 464 return 0; 465 } 466 467 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { 468 /* pipe-phy-grf */ 469 .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 }, 470 .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 }, 471 .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 }, 472 .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 }, 473 .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 }, 474 .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 }, 475 .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 }, 476 .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 }, 477 .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 }, 478 .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 }, 479 .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 }, 480 .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 }, 481 .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 }, 482 .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 }, 483 .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 }, 484 .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 }, 485 /* pipe-grf */ 486 .u3otg0_pipe_clk_sel = { 0x40044, 7, 7, 0x01, 0x00 }, 487 .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 }, 488 }; 489 490 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { 491 .grfcfg = &rk3528_combphy_grfcfgs, 492 .combphy_cfg = rk3528_combphy_cfg, 493 }; 494 #endif 495 496 #ifdef CONFIG_ROCKCHIP_RK3562 497 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) 498 { 499 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 500 u32 val; 501 502 switch (priv->mode) { 503 case PHY_TYPE_PCIE: 504 /* Set SSC downward spread spectrum */ 505 val = readl(priv->mmio + (0x1f << 2)); 506 val &= ~GENMASK(5, 4); 507 val |= 0x01 << 4; 508 writel(val, priv->mmio + 0x7c); 509 510 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 511 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 512 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 513 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 514 break; 515 case PHY_TYPE_USB3: 516 /* Set SSC downward spread spectrum */ 517 val = readl(priv->mmio + (0x1f << 2)); 518 val &= ~GENMASK(5, 4); 519 val |= 0x01 << 4; 520 writel(val, priv->mmio + 0x7c); 521 522 /* Enable adaptive CTLE for USB3.0 Rx */ 523 val = readl(priv->mmio + (0x0e << 2)); 524 val &= ~GENMASK(0, 0); 525 val |= 0x01; 526 writel(val, priv->mmio + (0x0e << 2)); 527 528 /* Set PLL KVCO fine tuning signals */ 529 val = readl(priv->mmio + (0x20 << 2)); 530 val &= ~(0x7 << 2); 531 val |= 0x2 << 2; 532 writel(val, priv->mmio + (0x20 << 2)); 533 534 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 535 writel(0x4, priv->mmio + (0xb << 2)); 536 537 /* Set PLL input clock divider 1/2 */ 538 val = readl(priv->mmio + (0x5 << 2)); 539 val &= ~(0x3 << 6); 540 val |= 0x1 << 6; 541 writel(val, priv->mmio + (0x5 << 2)); 542 543 /* Set PLL loop divider */ 544 writel(0x32, priv->mmio + (0x11 << 2)); 545 546 /* Set PLL KVCO to min and set PLL charge pump current to max */ 547 writel(0xf0, priv->mmio + (0xa << 2)); 548 549 /* Set Rx squelch input filler bandwidth */ 550 writel(0x0e, priv->mmio + (0x14 << 2)); 551 552 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 553 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 554 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 555 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 556 break; 557 default: 558 pr_err("%s, phy-type %d\n", __func__, priv->mode); 559 return -EINVAL; 560 } 561 562 clk_set_rate(&priv->ref_clk, 100000000); 563 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 564 565 if (priv->mode == PHY_TYPE_PCIE) { 566 /* PLL KVCO tuning fine */ 567 val = readl(priv->mmio + (0x20 << 2)); 568 val &= ~(0x7 << 2); 569 val |= 0x2 << 2; 570 writel(val, priv->mmio + (0x20 << 2)); 571 572 /* Enable controlling random jitter, aka RMJ */ 573 writel(0x4, priv->mmio + (0xb << 2)); 574 575 val = readl(priv->mmio + (0x5 << 2)); 576 val &= ~(0x3 << 6); 577 val |= 0x1 << 6; 578 writel(val, priv->mmio + (0x5 << 2)); 579 580 writel(0x32, priv->mmio + (0x11 << 2)); 581 writel(0xf0, priv->mmio + (0xa << 2)); 582 } 583 584 if (dev_read_bool(priv->dev, "rockchip,ext-refclk")) { 585 param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 586 if (priv->mode == PHY_TYPE_PCIE) { 587 val = readl(priv->mmio + (0xc << 2)); 588 val |= 0x3 << 4 | 0x1 << 7; 589 writel(val, priv->mmio + (0xc << 2)); 590 591 val = readl(priv->mmio + (0xd << 2)); 592 val |= 0x1; 593 writel(val, priv->mmio + (0xd << 2)); 594 } 595 } 596 597 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 598 val = readl(priv->mmio + (0x7 << 2)); 599 val |= BIT(4); 600 writel(val, priv->mmio + (0x7 << 2)); 601 } 602 603 return 0; 604 } 605 606 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { 607 /* pipe-phy-grf */ 608 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 609 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 610 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 611 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 612 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 613 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 614 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 615 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 616 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 617 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 618 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 619 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 620 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 621 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 622 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 623 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 624 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 625 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 626 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 627 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 628 /* pipe-grf */ 629 .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 }, 630 }; 631 632 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { 633 .grfcfg = &rk3562_combphy_grfcfgs, 634 .combphy_cfg = rk3562_combphy_cfg, 635 .force_det_out = true, 636 }; 637 #endif 638 639 #ifdef CONFIG_ROCKCHIP_RK3568 640 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 641 { 642 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 643 u32 val; 644 645 switch (priv->mode) { 646 case PHY_TYPE_PCIE: 647 /* Set SSC downward spread spectrum */ 648 val = readl(priv->mmio + (0x1f << 2)); 649 val &= ~GENMASK(5, 4); 650 val |= 0x01 << 4; 651 writel(val, priv->mmio + 0x7c); 652 653 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 654 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 655 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 656 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 657 break; 658 case PHY_TYPE_USB3: 659 /* Set SSC downward spread spectrum */ 660 val = readl(priv->mmio + (0x1f << 2)); 661 val &= ~GENMASK(5, 4); 662 val |= 0x01 << 4; 663 writel(val, priv->mmio + 0x7c); 664 665 /* Enable adaptive CTLE for USB3.0 Rx */ 666 val = readl(priv->mmio + (0x0e << 2)); 667 val &= ~GENMASK(0, 0); 668 val |= 0x01; 669 writel(val, priv->mmio + (0x0e << 2)); 670 671 /* Set PLL KVCO fine tuning signals */ 672 val = readl(priv->mmio + (0x20 << 2)); 673 val &= ~(0x7 << 2); 674 val |= 0x2 << 2; 675 writel(val, priv->mmio + (0x20 << 2)); 676 677 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 678 writel(0x4, priv->mmio + (0xb << 2)); 679 680 /* Set PLL input clock divider 1/2 */ 681 val = readl(priv->mmio + (0x5 << 2)); 682 val &= ~(0x3 << 6); 683 val |= 0x1 << 6; 684 writel(val, priv->mmio + (0x5 << 2)); 685 686 /* Set PLL loop divider */ 687 writel(0x32, priv->mmio + (0x11 << 2)); 688 689 /* Set PLL KVCO to min and set PLL charge pump current to max */ 690 writel(0xf0, priv->mmio + (0xa << 2)); 691 692 /* Set Rx squelch input filler bandwidth */ 693 writel(0x0e, priv->mmio + (0x14 << 2)); 694 695 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 696 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 697 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 698 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 699 break; 700 case PHY_TYPE_SATA: 701 writel(0x41, priv->mmio + 0x38); 702 writel(0x8F, priv->mmio + 0x18); 703 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 704 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 705 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 706 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 707 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 708 break; 709 case PHY_TYPE_SGMII: 710 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 711 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 712 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 713 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 714 break; 715 case PHY_TYPE_QSGMII: 716 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 717 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 718 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 719 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 720 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 721 break; 722 default: 723 pr_err("%s, phy-type %d\n", __func__, priv->mode); 724 return -EINVAL; 725 } 726 727 /* The default ref clock is 25Mhz */ 728 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 729 730 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 731 val = readl(priv->mmio + (0x7 << 2)); 732 val |= BIT(4); 733 writel(val, priv->mmio + (0x7 << 2)); 734 } 735 736 return 0; 737 } 738 739 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 740 /* pipe-phy-grf */ 741 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 742 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 743 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 744 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 745 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 746 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 747 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 748 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 749 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 750 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 751 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 752 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 753 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 754 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 755 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 756 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 757 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 758 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 759 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 760 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 761 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 762 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 763 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 764 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 765 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 766 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 767 /* pipe-grf */ 768 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 769 .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, 770 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 771 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 772 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 773 }; 774 775 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 776 .grfcfg = &rk3568_combphy_grfcfgs, 777 .combphy_cfg = rk3568_combphy_cfg, 778 .force_det_out = true, 779 }; 780 #endif 781 782 #ifdef CONFIG_ROCKCHIP_RK3588 783 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 784 { 785 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 786 u32 val; 787 788 switch (priv->mode) { 789 case PHY_TYPE_PCIE: 790 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 791 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 792 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 793 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 794 break; 795 case PHY_TYPE_USB3: 796 /* Set SSC downward spread spectrum */ 797 val = readl(priv->mmio + (0x1f << 2)); 798 val &= ~GENMASK(5, 4); 799 val |= 0x01 << 4; 800 writel(val, priv->mmio + 0x7c); 801 802 /* Enable adaptive CTLE for USB3.0 Rx */ 803 val = readl(priv->mmio + (0x0e << 2)); 804 val &= ~GENMASK(0, 0); 805 val |= 0x01; 806 writel(val, priv->mmio + (0x0e << 2)); 807 808 /* Set PLL KVCO fine tuning signals */ 809 val = readl(priv->mmio + (0x20 << 2)); 810 val &= ~(0x7 << 2); 811 val |= 0x2 << 2; 812 writel(val, priv->mmio + (0x20 << 2)); 813 814 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 815 writel(0x4, priv->mmio + (0xb << 2)); 816 817 /* Set PLL input clock divider 1/2 */ 818 val = readl(priv->mmio + (0x5 << 2)); 819 val &= ~(0x3 << 6); 820 val |= 0x1 << 6; 821 writel(val, priv->mmio + (0x5 << 2)); 822 823 /* Set PLL loop divider */ 824 writel(0x32, priv->mmio + (0x11 << 2)); 825 826 /* Set PLL KVCO to min and set PLL charge pump current to max */ 827 writel(0xf0, priv->mmio + (0xa << 2)); 828 829 /* Set Rx squelch input filler bandwidth */ 830 writel(0x0d, priv->mmio + (0x14 << 2)); 831 832 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 833 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 834 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 835 break; 836 case PHY_TYPE_SATA: 837 /* Enable adaptive CTLE for SATA Rx */ 838 val = readl(priv->mmio + (0x0e << 2)); 839 val &= ~GENMASK(0, 0); 840 val |= 0x01; 841 writel(val, priv->mmio + (0x0e << 2)); 842 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 843 writel(0x8F, priv->mmio + (0x06 << 2)); 844 845 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 846 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 847 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 848 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 849 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 850 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 851 break; 852 case PHY_TYPE_SGMII: 853 case PHY_TYPE_QSGMII: 854 default: 855 dev_err(priv->dev, "incompatible PHY type\n"); 856 return -EINVAL; 857 } 858 859 /* 100MHz refclock signal is good */ 860 clk_set_rate(&priv->ref_clk, 100000000); 861 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 862 if (priv->mode == PHY_TYPE_PCIE) { 863 /* PLL KVCO tuning fine */ 864 val = readl(priv->mmio + (0x20 << 2)); 865 val &= ~GENMASK(4, 2); 866 val |= 0x4 << 2; 867 writel(val, priv->mmio + (0x20 << 2)); 868 869 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 870 val = 0x4c; 871 writel(val, priv->mmio + (0x1b << 2)); 872 873 /* Set up su_trim: T3 */ 874 val = 0xb0; 875 writel(val, priv->mmio + (0xa << 2)); 876 val = 0x47; 877 writel(val, priv->mmio + (0xb << 2)); 878 val = 0x57; 879 writel(val, priv->mmio + (0xd << 2)); 880 } 881 882 return 0; 883 } 884 885 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 886 /* pipe-phy-grf */ 887 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 888 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 889 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 890 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 891 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 892 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 893 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 894 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 895 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 896 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 897 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 898 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 899 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 900 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 901 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 902 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 903 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 904 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 905 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 906 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 907 /* pipe-grf */ 908 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 909 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 910 }; 911 912 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 913 .grfcfg = &rk3588_combphy_grfcfgs, 914 .combphy_cfg = rk3588_combphy_cfg, 915 .force_det_out = true, 916 }; 917 #endif 918 919 920 #ifdef CONFIG_ROCKCHIP_RK3576 921 static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) 922 { 923 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 924 u32 val; 925 926 switch (priv->mode) { 927 case PHY_TYPE_PCIE: 928 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 929 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 930 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 931 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 932 break; 933 case PHY_TYPE_USB3: 934 /* Set SSC downward spread spectrum */ 935 val = readl(priv->mmio + (0x1f << 2)); 936 val &= ~GENMASK(5, 4); 937 val |= 0x01 << 4; 938 writel(val, priv->mmio + 0x7c); 939 940 /* Enable adaptive CTLE for USB3.0 Rx */ 941 val = readl(priv->mmio + (0x0e << 2)); 942 val &= ~GENMASK(0, 0); 943 val |= 0x01; 944 writel(val, priv->mmio + (0x0e << 2)); 945 946 /* Set PLL KVCO fine tuning signals */ 947 val = readl(priv->mmio + (0x20 << 2)); 948 val &= ~(0x7 << 2); 949 val |= 0x2 << 2; 950 writel(val, priv->mmio + (0x20 << 2)); 951 952 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 953 writel(0x4, priv->mmio + (0xb << 2)); 954 955 /* Set PLL input clock divider 1/2 */ 956 val = readl(priv->mmio + (0x5 << 2)); 957 val &= ~(0x3 << 6); 958 val |= 0x1 << 6; 959 writel(val, priv->mmio + (0x5 << 2)); 960 961 /* Set PLL loop divider */ 962 writel(0x32, priv->mmio + (0x11 << 2)); 963 964 /* Set PLL KVCO to min and set PLL charge pump current to max */ 965 writel(0xf0, priv->mmio + (0xa << 2)); 966 967 /* Set Rx squelch input filler bandwidth */ 968 writel(0x0d, priv->mmio + (0x14 << 2)); 969 970 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 971 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 972 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 973 break; 974 case PHY_TYPE_SATA: 975 /* Enable adaptive CTLE for SATA Rx */ 976 val = readl(priv->mmio + (0x0e << 2)); 977 val &= ~GENMASK(0, 0); 978 val |= 0x01; 979 writel(val, priv->mmio + (0x0e << 2)); 980 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 981 writel(0x8F, priv->mmio + (0x06 << 2)); 982 983 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 984 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 985 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 986 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 987 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 988 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 989 break; 990 case PHY_TYPE_SGMII: 991 case PHY_TYPE_QSGMII: 992 default: 993 dev_err(priv->dev, "incompatible PHY type\n"); 994 return -EINVAL; 995 } 996 997 /* 100MHz refclock signal is good */ 998 clk_set_rate(&priv->ref_clk, 100000000); 999 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 1000 if (priv->mode == PHY_TYPE_PCIE) { 1001 /* gate_tx_pck_sel length select work for L1SS */ 1002 writel(0xc0, priv->mmio + 0x74); 1003 1004 /* PLL KVCO tuning fine */ 1005 val = readl(priv->mmio + (0x20 << 2)); 1006 val &= ~(0x7 << 2); 1007 val |= 0x2 << 2; 1008 writel(val, priv->mmio + (0x20 << 2)); 1009 1010 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 1011 writel(0x4c, priv->mmio + (0x1b << 2)); 1012 1013 /* Set up su_trim: T3_P1 650mv */ 1014 writel(0x90, priv->mmio + (0xa << 2)); 1015 writel(0x43, priv->mmio + (0xb << 2)); 1016 writel(0x88, priv->mmio + (0xc << 2)); 1017 writel(0x56, priv->mmio + (0xd << 2)); 1018 } 1019 1020 return 0; 1021 } 1022 1023 static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { 1024 /* pipe-phy-grf */ 1025 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 1026 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 1027 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 1028 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 1029 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 1030 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, 1031 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 1032 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 1033 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 1034 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 1035 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 1036 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 1037 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 1038 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 1039 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 1040 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 1041 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 1042 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 1043 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 1044 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 1045 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 1046 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 1047 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 1048 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 1049 /* php-grf */ 1050 .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, 1051 .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, 1052 .u3otg1_port_en = { 0x0038, 15, 0, 0x0181, 0x1100 }, 1053 }; 1054 1055 static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { 1056 .grfcfg = &rk3576_combphy_grfcfgs, 1057 .combphy_cfg = rk3576_combphy_cfg, 1058 }; 1059 #endif 1060 1061 static const struct udevice_id rockchip_combphy_ids[] = { 1062 #ifdef CONFIG_ROCKCHIP_RK3528 1063 { 1064 .compatible = "rockchip,rk3528-naneng-combphy", 1065 .data = (ulong)&rk3528_combphy_cfgs 1066 }, 1067 #endif 1068 #ifdef CONFIG_ROCKCHIP_RK3562 1069 { 1070 .compatible = "rockchip,rk3562-naneng-combphy", 1071 .data = (ulong)&rk3562_combphy_cfgs 1072 }, 1073 #endif 1074 #ifdef CONFIG_ROCKCHIP_RK3568 1075 { 1076 .compatible = "rockchip,rk3568-naneng-combphy", 1077 .data = (ulong)&rk3568_combphy_cfgs 1078 }, 1079 #endif 1080 #ifdef CONFIG_ROCKCHIP_RK3588 1081 { 1082 .compatible = "rockchip,rk3588-naneng-combphy", 1083 .data = (ulong)&rk3588_combphy_cfgs 1084 }, 1085 #endif 1086 #ifdef CONFIG_ROCKCHIP_RK3576 1087 { 1088 .compatible = "rockchip,rk3576-naneng-combphy", 1089 .data = (ulong)&rk3576_combphy_cfgs 1090 }, 1091 #endif 1092 { } 1093 }; 1094 1095 U_BOOT_DRIVER(rockchip_naneng_combphy) = { 1096 .name = "naneng-combphy", 1097 .id = UCLASS_PHY, 1098 .of_match = rockchip_combphy_ids, 1099 .ops = &rochchip_combphy_ops, 1100 .probe = rockchip_combphy_probe, 1101 .priv_auto_alloc_size = sizeof(struct rockchip_combphy_priv), 1102 }; 1103