1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dm/uclass-internal.h> 13 #include <dt-bindings/phy/phy.h> 14 #include <generic-phy.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <regmap.h> 19 #include <reset-uclass.h> 20 #include <linux/iopoll.h> 21 22 #define BIT_WRITEABLE_SHIFT 16 23 24 struct rockchip_combphy_priv; 25 26 struct combphy_reg { 27 u32 offset; 28 u16 bitend; 29 u16 bitstart; 30 u16 disable; 31 u16 enable; 32 }; 33 34 struct rockchip_combphy_grfcfg { 35 struct combphy_reg pcie_mode_set; 36 struct combphy_reg usb_mode_set; 37 struct combphy_reg sgmii_mode_set; 38 struct combphy_reg qsgmii_mode_set; 39 struct combphy_reg pipe_rxterm_set; 40 struct combphy_reg pipe_txelec_set; 41 struct combphy_reg pipe_txcomp_set; 42 struct combphy_reg pipe_clk_24m; 43 struct combphy_reg pipe_clk_25m; 44 struct combphy_reg pipe_clk_100m; 45 struct combphy_reg pipe_phymode_sel; 46 struct combphy_reg pipe_rate_sel; 47 struct combphy_reg pipe_rxterm_sel; 48 struct combphy_reg pipe_txelec_sel; 49 struct combphy_reg pipe_txcomp_sel; 50 struct combphy_reg pipe_clk_ext; 51 struct combphy_reg pipe_sel_usb; 52 struct combphy_reg pipe_sel_qsgmii; 53 struct combphy_reg pipe_phy_status; 54 struct combphy_reg con0_for_pcie; 55 struct combphy_reg con1_for_pcie; 56 struct combphy_reg con2_for_pcie; 57 struct combphy_reg con3_for_pcie; 58 struct combphy_reg con0_for_sata; 59 struct combphy_reg con1_for_sata; 60 struct combphy_reg con2_for_sata; 61 struct combphy_reg con3_for_sata; 62 struct combphy_reg pipe_con0_for_sata; 63 struct combphy_reg pipe_con1_for_sata; 64 struct combphy_reg pipe_sgmii_mac_sel; 65 struct combphy_reg pipe_xpcs_phy_ready; 66 struct combphy_reg u3otg0_clamp_dis; 67 struct combphy_reg u3otg0_port_en; 68 struct combphy_reg u3otg1_port_en; 69 struct combphy_reg u3otg0_pipe_clk_sel; 70 struct combphy_reg pipe_phy_grf_reset; 71 }; 72 73 struct rockchip_combphy_cfg { 74 const struct rockchip_combphy_grfcfg *grfcfg; 75 bool force_det_out; /* Tx detect Rx errata */ 76 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 77 }; 78 79 struct rockchip_combphy_priv { 80 u32 mode; 81 void __iomem *mmio; 82 struct udevice *dev; 83 struct regmap *pipe_grf; 84 struct regmap *phy_grf; 85 struct phy *phy; 86 struct reset_ctl phy_rst; 87 struct clk ref_clk; 88 const struct rockchip_combphy_cfg *cfg; 89 }; 90 91 static int param_write(struct regmap *base, 92 const struct combphy_reg *reg, bool en) 93 { 94 u32 val, mask, tmp; 95 96 tmp = en ? reg->enable : reg->disable; 97 mask = GENMASK(reg->bitend, reg->bitstart); 98 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 99 100 return regmap_write(base, reg->offset, val); 101 } 102 103 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) 104 { 105 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 106 u32 mask, val; 107 108 mask = GENMASK(cfg->pipe_phy_status.bitend, 109 cfg->pipe_phy_status.bitstart); 110 111 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); 112 val = (val & mask) >> cfg->pipe_phy_status.bitstart; 113 114 return val; 115 } 116 117 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) 118 { 119 int ret = 0; 120 u32 val; 121 122 if (priv->cfg->combphy_cfg) { 123 ret = priv->cfg->combphy_cfg(priv); 124 if (ret) { 125 dev_err(priv->dev, "failed to init phy for pcie\n"); 126 return ret; 127 } 128 } 129 130 if (priv->cfg->force_det_out) { 131 val = readl(priv->mmio + (0x19 << 2)); 132 val |= BIT(5); 133 writel(val, priv->mmio + (0x19 << 2)); 134 } 135 136 return ret; 137 } 138 139 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) 140 { 141 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 142 int ret = 0; 143 144 if (dev_read_bool(priv->dev, "rockchip,dis-u3otg0-port")) { 145 ret = param_write(priv->pipe_grf, &cfg->u3otg0_port_en, false); 146 return ret; 147 } else if (dev_read_bool(priv->dev, "rockchip,dis-u3otg1-port")) { 148 param_write(priv->pipe_grf, &cfg->u3otg1_port_en, false); 149 #ifdef CONFIG_ROCKCHIP_RK3576 150 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 151 #endif 152 return ret; 153 } else { 154 if (cfg->u3otg0_clamp_dis.enable) 155 param_write(priv->pipe_grf, &cfg->u3otg0_clamp_dis, true); 156 } 157 158 if (priv->cfg->combphy_cfg) { 159 ret = priv->cfg->combphy_cfg(priv); 160 if (ret) { 161 dev_err(priv->dev, "failed to init phy for usb3\n"); 162 return ret; 163 } 164 } 165 166 return ret; 167 } 168 169 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) 170 { 171 int ret = 0; 172 173 if (priv->cfg->combphy_cfg) { 174 ret = priv->cfg->combphy_cfg(priv); 175 if (ret) { 176 dev_err(priv->dev, "failed to init phy for sata\n"); 177 return ret; 178 } 179 } 180 181 return ret; 182 } 183 184 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) 185 { 186 int ret = 0; 187 188 if (priv->cfg->combphy_cfg) { 189 ret = priv->cfg->combphy_cfg(priv); 190 if (ret) { 191 dev_err(priv->dev, "failed to init phy for sgmii\n"); 192 return ret; 193 } 194 } 195 196 return ret; 197 } 198 199 int rockchip_combphy_usb3_uboot_init(fdt_addr_t phy_addr) 200 { 201 struct udevice *udev = NULL; 202 struct udevice *dev; 203 struct uclass *uc; 204 const struct driver *find_drv; 205 struct rockchip_combphy_priv *priv; 206 const struct rockchip_combphy_grfcfg *cfg; 207 u32 val; 208 int ret = 0; 209 210 ret = uclass_get(UCLASS_PHY, &uc); 211 if (ret) 212 return ret; 213 214 find_drv = DM_GET_DRIVER(rockchip_naneng_combphy); 215 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 216 if (dev->driver == find_drv && dev_read_addr(dev) == phy_addr) { 217 ret = uclass_get_device_tail(dev, 0, &udev); 218 break; 219 } 220 } 221 222 if (!udev || ret) { 223 ret = ret ? ret : -ENODEV; 224 pr_err("%s: get usb3-phy node failed: %d\n", __func__, ret); 225 return ret; 226 } 227 228 priv = dev_get_priv(udev); 229 priv->mode = PHY_TYPE_USB3; 230 cfg = priv->cfg->grfcfg; 231 232 rockchip_combphy_usb3_init(priv); 233 reset_deassert(&priv->phy_rst); 234 235 if (cfg->pipe_phy_grf_reset.enable) 236 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 237 238 if (priv->mode == PHY_TYPE_USB3) { 239 ret = readx_poll_timeout(rockchip_combphy_is_ready, 240 priv, val, 241 val == cfg->pipe_phy_status.enable, 242 1000); 243 if (ret) { 244 dev_err(priv->dev, "wait phy status ready timeout\n"); 245 param_write(priv->phy_grf, &cfg->usb_mode_set, false); 246 if (cfg->u3otg0_pipe_clk_sel.disable) 247 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, false); 248 return ret; 249 } 250 } 251 252 /* Select clk_usb3otg0_pipe for source clk */ 253 if (cfg->u3otg0_pipe_clk_sel.disable) 254 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, true); 255 256 return ret; 257 } 258 259 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) 260 { 261 switch (priv->mode) { 262 case PHY_TYPE_PCIE: 263 rockchip_combphy_pcie_init(priv); 264 break; 265 case PHY_TYPE_USB3: 266 rockchip_combphy_usb3_init(priv); 267 break; 268 case PHY_TYPE_SATA: 269 rockchip_combphy_sata_init(priv); 270 break; 271 case PHY_TYPE_SGMII: 272 case PHY_TYPE_QSGMII: 273 return rockchip_combphy_sgmii_init(priv); 274 default: 275 dev_err(priv->dev, "incompatible PHY type\n"); 276 return -EINVAL; 277 } 278 279 return 0; 280 } 281 282 static int rockchip_combphy_init(struct phy *phy) 283 { 284 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 285 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 286 int ret; 287 288 ret = clk_enable(&priv->ref_clk); 289 if (ret < 0 && ret != -ENOSYS) 290 return ret; 291 292 ret = rockchip_combphy_set_mode(priv); 293 if (ret) 294 goto err_clk; 295 296 reset_deassert(&priv->phy_rst); 297 298 if (cfg->pipe_phy_grf_reset.enable) 299 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 300 301 return 0; 302 303 err_clk: 304 clk_disable(&priv->ref_clk); 305 306 return ret; 307 } 308 309 static int rockchip_combphy_exit(struct phy *phy) 310 { 311 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 312 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 313 314 if (cfg->pipe_phy_grf_reset.enable) 315 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); 316 317 reset_assert(&priv->phy_rst); 318 clk_disable(&priv->ref_clk); 319 320 return 0; 321 } 322 323 static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) 324 { 325 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 326 327 if (args->args_count != 1) { 328 pr_err("invalid number of arguments\n"); 329 return -EINVAL; 330 } 331 332 priv->mode = args->args[0]; 333 334 return 0; 335 } 336 337 static const struct phy_ops rochchip_combphy_ops = { 338 .init = rockchip_combphy_init, 339 .exit = rockchip_combphy_exit, 340 .of_xlate = rockchip_combphy_xlate, 341 }; 342 343 static int rockchip_combphy_parse_dt(struct udevice *dev, 344 struct rockchip_combphy_priv *priv) 345 { 346 struct udevice *syscon; 347 int ret; 348 u32 vals[4]; 349 350 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); 351 if (ret) { 352 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap ret= %d\n", ret); 353 return ret; 354 } 355 priv->pipe_grf = syscon_get_regmap(syscon); 356 357 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); 358 if (ret) { 359 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 360 return ret; 361 } 362 priv->phy_grf = syscon_get_regmap(syscon); 363 364 ret = clk_get_by_index(dev, 0, &priv->ref_clk); 365 if (ret) { 366 dev_err(dev, "failed to find ref clock\n"); 367 return PTR_ERR(&priv->ref_clk); 368 } 369 370 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); 371 if (ret) { 372 dev_err(dev, "no phy reset control specified\n"); 373 return ret; 374 } 375 376 if (!dev_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", 377 vals, ARRAY_SIZE(vals))) 378 regmap_write(priv->pipe_grf, vals[0], 379 (GENMASK(vals[2], vals[1]) << 16) | vals[3]); 380 381 return 0; 382 } 383 384 static int rockchip_combphy_probe(struct udevice *udev) 385 { 386 struct rockchip_combphy_priv *priv = dev_get_priv(udev); 387 const struct rockchip_combphy_cfg *phy_cfg; 388 389 priv->mmio = (void __iomem *)dev_read_addr(udev); 390 if (IS_ERR(priv->mmio)) 391 return PTR_ERR(priv->mmio); 392 393 phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); 394 if (!phy_cfg) { 395 dev_err(udev, "No OF match data provided\n"); 396 return -EINVAL; 397 } 398 399 priv->dev = udev; 400 priv->mode = PHY_TYPE_SATA; 401 priv->cfg = phy_cfg; 402 403 return rockchip_combphy_parse_dt(udev, priv); 404 } 405 406 #ifdef CONFIG_ROCKCHIP_RK3528 407 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) 408 { 409 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 410 u32 val; 411 412 switch (priv->mode) { 413 case PHY_TYPE_PCIE: 414 /* Set SSC downward spread spectrum */ 415 val = readl(priv->mmio + 0x18); 416 val &= ~GENMASK(5, 4); 417 val |= 0x01 << 4; 418 writel(val, priv->mmio + 0x18); 419 420 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 421 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 422 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 423 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 424 break; 425 case PHY_TYPE_USB3: 426 /* Set SSC downward spread spectrum */ 427 val = readl(priv->mmio + 0x18); 428 val &= ~GENMASK(5, 4); 429 val |= 0x01 << 4; 430 writel(val, priv->mmio + 0x18); 431 432 /* Enable adaptive CTLE for USB3.0 Rx */ 433 val = readl(priv->mmio + 0x200); 434 val &= ~GENMASK(17, 17); 435 val |= 0x01; 436 writel(val, priv->mmio + 0x200); 437 438 /* Set Rx squelch input filler bandwidth */ 439 val = readl(priv->mmio + 0x20c); 440 val &= ~GENMASK(2, 0); 441 val |= 0x06; 442 writel(val, priv->mmio + 0x20c); 443 444 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 445 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 446 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 447 break; 448 default: 449 dev_err(priv->dev, "incompatible PHY type\n"); 450 return -EINVAL; 451 } 452 453 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 454 if (priv->mode == PHY_TYPE_PCIE) { 455 /* PLL KVCO tuning fine */ 456 val = readl(priv->mmio + 0x18); 457 val &= ~(0x7 << 10); 458 val |= 0x2 << 10; 459 writel(val, priv->mmio + 0x18); 460 461 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ 462 val = readl(priv->mmio + 0x108); 463 val &= ~(0x7f7); 464 val |= 0x4f0; 465 writel(val, priv->mmio + 0x108); 466 } 467 468 return 0; 469 } 470 471 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { 472 /* pipe-phy-grf */ 473 .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 }, 474 .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 }, 475 .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 }, 476 .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 }, 477 .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 }, 478 .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 }, 479 .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 }, 480 .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 }, 481 .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 }, 482 .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 }, 483 .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 }, 484 .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 }, 485 .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 }, 486 .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 }, 487 .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 }, 488 .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 }, 489 /* pipe-grf */ 490 .u3otg0_pipe_clk_sel = { 0x40044, 7, 7, 0x01, 0x00 }, 491 .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 }, 492 }; 493 494 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { 495 .grfcfg = &rk3528_combphy_grfcfgs, 496 .combphy_cfg = rk3528_combphy_cfg, 497 }; 498 #endif 499 500 #ifdef CONFIG_ROCKCHIP_RK3562 501 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) 502 { 503 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 504 u32 val; 505 506 switch (priv->mode) { 507 case PHY_TYPE_PCIE: 508 /* Set SSC downward spread spectrum */ 509 val = readl(priv->mmio + (0x1f << 2)); 510 val &= ~GENMASK(5, 4); 511 val |= 0x01 << 4; 512 writel(val, priv->mmio + 0x7c); 513 514 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 515 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 516 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 517 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 518 break; 519 case PHY_TYPE_USB3: 520 /* Set SSC downward spread spectrum */ 521 val = readl(priv->mmio + (0x1f << 2)); 522 val &= ~GENMASK(5, 4); 523 val |= 0x01 << 4; 524 writel(val, priv->mmio + 0x7c); 525 526 /* Enable adaptive CTLE for USB3.0 Rx */ 527 val = readl(priv->mmio + (0x0e << 2)); 528 val &= ~GENMASK(0, 0); 529 val |= 0x01; 530 writel(val, priv->mmio + (0x0e << 2)); 531 532 /* Set PLL KVCO fine tuning signals */ 533 val = readl(priv->mmio + (0x20 << 2)); 534 val &= ~(0x7 << 2); 535 val |= 0x2 << 2; 536 writel(val, priv->mmio + (0x20 << 2)); 537 538 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 539 writel(0x4, priv->mmio + (0xb << 2)); 540 541 /* Set PLL input clock divider 1/2 */ 542 val = readl(priv->mmio + (0x5 << 2)); 543 val &= ~(0x3 << 6); 544 val |= 0x1 << 6; 545 writel(val, priv->mmio + (0x5 << 2)); 546 547 /* Set PLL loop divider */ 548 writel(0x32, priv->mmio + (0x11 << 2)); 549 550 /* Set PLL KVCO to min and set PLL charge pump current to max */ 551 writel(0xf0, priv->mmio + (0xa << 2)); 552 553 /* Set Rx squelch input filler bandwidth */ 554 writel(0x0e, priv->mmio + (0x14 << 2)); 555 556 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 557 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 558 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 559 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 560 break; 561 default: 562 pr_err("%s, phy-type %d\n", __func__, priv->mode); 563 return -EINVAL; 564 } 565 566 clk_set_rate(&priv->ref_clk, 100000000); 567 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 568 569 if (priv->mode == PHY_TYPE_PCIE) { 570 /* PLL KVCO tuning fine */ 571 val = readl(priv->mmio + (0x20 << 2)); 572 val &= ~(0x7 << 2); 573 val |= 0x2 << 2; 574 writel(val, priv->mmio + (0x20 << 2)); 575 576 /* Enable controlling random jitter, aka RMJ */ 577 writel(0x4, priv->mmio + (0xb << 2)); 578 579 val = readl(priv->mmio + (0x5 << 2)); 580 val &= ~(0x3 << 6); 581 val |= 0x1 << 6; 582 writel(val, priv->mmio + (0x5 << 2)); 583 584 writel(0x32, priv->mmio + (0x11 << 2)); 585 writel(0xf0, priv->mmio + (0xa << 2)); 586 } 587 588 if (dev_read_bool(priv->dev, "rockchip,ext-refclk")) { 589 param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 590 if (priv->mode == PHY_TYPE_PCIE) { 591 val = readl(priv->mmio + (0xc << 2)); 592 val |= 0x3 << 4 | 0x1 << 7; 593 writel(val, priv->mmio + (0xc << 2)); 594 595 val = readl(priv->mmio + (0xd << 2)); 596 val |= 0x1; 597 writel(val, priv->mmio + (0xd << 2)); 598 } 599 } 600 601 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 602 val = readl(priv->mmio + (0x7 << 2)); 603 val |= BIT(4); 604 writel(val, priv->mmio + (0x7 << 2)); 605 } 606 607 return 0; 608 } 609 610 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { 611 /* pipe-phy-grf */ 612 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 613 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 614 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 615 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 616 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 617 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 618 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 619 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 620 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 621 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 622 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 623 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 624 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 625 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 626 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 627 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 628 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 629 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 630 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 631 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 632 /* pipe-grf */ 633 .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 }, 634 }; 635 636 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { 637 .grfcfg = &rk3562_combphy_grfcfgs, 638 .combphy_cfg = rk3562_combphy_cfg, 639 .force_det_out = true, 640 }; 641 #endif 642 643 #ifdef CONFIG_ROCKCHIP_RK3568 644 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 645 { 646 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 647 u32 val; 648 649 switch (priv->mode) { 650 case PHY_TYPE_PCIE: 651 /* Set SSC downward spread spectrum */ 652 val = readl(priv->mmio + (0x1f << 2)); 653 val &= ~GENMASK(5, 4); 654 val |= 0x01 << 4; 655 writel(val, priv->mmio + 0x7c); 656 657 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 658 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 659 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 660 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 661 break; 662 case PHY_TYPE_USB3: 663 /* Set SSC downward spread spectrum */ 664 val = readl(priv->mmio + (0x1f << 2)); 665 val &= ~GENMASK(5, 4); 666 val |= 0x01 << 4; 667 writel(val, priv->mmio + 0x7c); 668 669 /* Enable adaptive CTLE for USB3.0 Rx */ 670 val = readl(priv->mmio + (0x0e << 2)); 671 val &= ~GENMASK(0, 0); 672 val |= 0x01; 673 writel(val, priv->mmio + (0x0e << 2)); 674 675 /* Set PLL KVCO fine tuning signals */ 676 val = readl(priv->mmio + (0x20 << 2)); 677 val &= ~(0x7 << 2); 678 val |= 0x2 << 2; 679 writel(val, priv->mmio + (0x20 << 2)); 680 681 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 682 writel(0x4, priv->mmio + (0xb << 2)); 683 684 /* Set PLL input clock divider 1/2 */ 685 val = readl(priv->mmio + (0x5 << 2)); 686 val &= ~(0x3 << 6); 687 val |= 0x1 << 6; 688 writel(val, priv->mmio + (0x5 << 2)); 689 690 /* Set PLL loop divider */ 691 writel(0x32, priv->mmio + (0x11 << 2)); 692 693 /* Set PLL KVCO to min and set PLL charge pump current to max */ 694 writel(0xf0, priv->mmio + (0xa << 2)); 695 696 /* Set Rx squelch input filler bandwidth */ 697 writel(0x0e, priv->mmio + (0x14 << 2)); 698 699 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 700 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 701 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 702 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 703 break; 704 case PHY_TYPE_SATA: 705 writel(0x41, priv->mmio + 0x38); 706 writel(0x8F, priv->mmio + 0x18); 707 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 708 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 709 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 710 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 711 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 712 break; 713 case PHY_TYPE_SGMII: 714 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 715 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 716 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 717 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 718 break; 719 case PHY_TYPE_QSGMII: 720 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 721 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 722 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 723 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 724 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 725 break; 726 default: 727 pr_err("%s, phy-type %d\n", __func__, priv->mode); 728 return -EINVAL; 729 } 730 731 /* The default ref clock is 25Mhz */ 732 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 733 734 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 735 val = readl(priv->mmio + (0x7 << 2)); 736 val |= BIT(4); 737 writel(val, priv->mmio + (0x7 << 2)); 738 } 739 740 return 0; 741 } 742 743 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 744 /* pipe-phy-grf */ 745 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 746 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 747 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 748 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 749 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 750 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 751 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 752 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 753 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 754 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 755 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 756 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 757 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 758 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 759 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 760 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 761 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 762 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 763 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 764 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 765 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 766 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 767 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 768 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 769 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 770 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 771 /* pipe-grf */ 772 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 773 .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, 774 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 775 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 776 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 777 }; 778 779 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 780 .grfcfg = &rk3568_combphy_grfcfgs, 781 .combphy_cfg = rk3568_combphy_cfg, 782 .force_det_out = true, 783 }; 784 #endif 785 786 #ifdef CONFIG_ROCKCHIP_RK3588 787 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 788 { 789 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 790 u32 val; 791 792 switch (priv->mode) { 793 case PHY_TYPE_PCIE: 794 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 795 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 796 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 797 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 798 break; 799 case PHY_TYPE_USB3: 800 /* Set SSC downward spread spectrum */ 801 val = readl(priv->mmio + (0x1f << 2)); 802 val &= ~GENMASK(5, 4); 803 val |= 0x01 << 4; 804 writel(val, priv->mmio + 0x7c); 805 806 /* Enable adaptive CTLE for USB3.0 Rx */ 807 val = readl(priv->mmio + (0x0e << 2)); 808 val &= ~GENMASK(0, 0); 809 val |= 0x01; 810 writel(val, priv->mmio + (0x0e << 2)); 811 812 /* Set PLL KVCO fine tuning signals */ 813 val = readl(priv->mmio + (0x20 << 2)); 814 val &= ~(0x7 << 2); 815 val |= 0x2 << 2; 816 writel(val, priv->mmio + (0x20 << 2)); 817 818 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 819 writel(0x4, priv->mmio + (0xb << 2)); 820 821 /* Set PLL input clock divider 1/2 */ 822 val = readl(priv->mmio + (0x5 << 2)); 823 val &= ~(0x3 << 6); 824 val |= 0x1 << 6; 825 writel(val, priv->mmio + (0x5 << 2)); 826 827 /* Set PLL loop divider */ 828 writel(0x32, priv->mmio + (0x11 << 2)); 829 830 /* Set PLL KVCO to min and set PLL charge pump current to max */ 831 writel(0xf0, priv->mmio + (0xa << 2)); 832 833 /* Set Rx squelch input filler bandwidth */ 834 writel(0x0d, priv->mmio + (0x14 << 2)); 835 836 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 837 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 838 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 839 break; 840 case PHY_TYPE_SATA: 841 /* Enable adaptive CTLE for SATA Rx */ 842 val = readl(priv->mmio + (0x0e << 2)); 843 val &= ~GENMASK(0, 0); 844 val |= 0x01; 845 writel(val, priv->mmio + (0x0e << 2)); 846 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 847 writel(0x8F, priv->mmio + (0x06 << 2)); 848 849 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 850 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 851 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 852 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 853 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 854 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 855 break; 856 case PHY_TYPE_SGMII: 857 case PHY_TYPE_QSGMII: 858 default: 859 dev_err(priv->dev, "incompatible PHY type\n"); 860 return -EINVAL; 861 } 862 863 /* 100MHz refclock signal is good */ 864 clk_set_rate(&priv->ref_clk, 100000000); 865 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 866 if (priv->mode == PHY_TYPE_PCIE) { 867 /* PLL KVCO tuning fine */ 868 val = readl(priv->mmio + (0x20 << 2)); 869 val &= ~GENMASK(4, 2); 870 val |= 0x4 << 2; 871 writel(val, priv->mmio + (0x20 << 2)); 872 873 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 874 val = 0x4c; 875 writel(val, priv->mmio + (0x1b << 2)); 876 877 /* Set up su_trim: T3 */ 878 val = 0xb0; 879 writel(val, priv->mmio + (0xa << 2)); 880 val = 0x47; 881 writel(val, priv->mmio + (0xb << 2)); 882 val = 0x57; 883 writel(val, priv->mmio + (0xd << 2)); 884 } 885 886 return 0; 887 } 888 889 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 890 /* pipe-phy-grf */ 891 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 892 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 893 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 894 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 895 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 896 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 897 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 898 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 899 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 900 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 901 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 902 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 903 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 904 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 905 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 906 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 907 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 908 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 909 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 910 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 911 /* pipe-grf */ 912 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 913 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 914 }; 915 916 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 917 .grfcfg = &rk3588_combphy_grfcfgs, 918 .combphy_cfg = rk3588_combphy_cfg, 919 .force_det_out = true, 920 }; 921 #endif 922 923 924 #ifdef CONFIG_ROCKCHIP_RK3576 925 static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) 926 { 927 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 928 u32 val; 929 930 switch (priv->mode) { 931 case PHY_TYPE_PCIE: 932 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 933 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 934 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 935 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 936 break; 937 case PHY_TYPE_USB3: 938 /* Set SSC downward spread spectrum */ 939 val = readl(priv->mmio + (0x1f << 2)); 940 val &= ~GENMASK(5, 4); 941 val |= 0x01 << 4; 942 writel(val, priv->mmio + 0x7c); 943 944 /* Enable adaptive CTLE for USB3.0 Rx */ 945 val = readl(priv->mmio + (0x0e << 2)); 946 val &= ~GENMASK(0, 0); 947 val |= 0x01; 948 writel(val, priv->mmio + (0x0e << 2)); 949 950 /* Set PLL KVCO fine tuning signals */ 951 val = readl(priv->mmio + (0x20 << 2)); 952 val &= ~(0x7 << 2); 953 val |= 0x2 << 2; 954 writel(val, priv->mmio + (0x20 << 2)); 955 956 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 957 writel(0x4, priv->mmio + (0xb << 2)); 958 959 /* Set PLL input clock divider 1/2 */ 960 val = readl(priv->mmio + (0x5 << 2)); 961 val &= ~(0x3 << 6); 962 val |= 0x1 << 6; 963 writel(val, priv->mmio + (0x5 << 2)); 964 965 /* Set PLL loop divider */ 966 writel(0x32, priv->mmio + (0x11 << 2)); 967 968 /* Set PLL KVCO to min and set PLL charge pump current to max */ 969 writel(0xf0, priv->mmio + (0xa << 2)); 970 971 /* Set Rx squelch input filler bandwidth */ 972 writel(0x0d, priv->mmio + (0x14 << 2)); 973 974 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 975 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 976 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 977 break; 978 case PHY_TYPE_SATA: 979 /* Enable adaptive CTLE for SATA Rx */ 980 val = readl(priv->mmio + (0x0e << 2)); 981 val &= ~GENMASK(0, 0); 982 val |= 0x01; 983 writel(val, priv->mmio + (0x0e << 2)); 984 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 985 writel(0x8F, priv->mmio + (0x06 << 2)); 986 987 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 988 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 989 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 990 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 991 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 992 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 993 break; 994 case PHY_TYPE_SGMII: 995 case PHY_TYPE_QSGMII: 996 default: 997 dev_err(priv->dev, "incompatible PHY type\n"); 998 return -EINVAL; 999 } 1000 1001 /* 100MHz refclock signal is good */ 1002 clk_set_rate(&priv->ref_clk, 100000000); 1003 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 1004 if (priv->mode == PHY_TYPE_PCIE) { 1005 /* gate_tx_pck_sel length select work for L1SS */ 1006 writel(0xc0, priv->mmio + 0x74); 1007 1008 /* PLL KVCO tuning fine */ 1009 val = readl(priv->mmio + (0x20 << 2)); 1010 val &= ~(0x7 << 2); 1011 val |= 0x2 << 2; 1012 writel(val, priv->mmio + (0x20 << 2)); 1013 1014 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 1015 writel(0x4c, priv->mmio + (0x1b << 2)); 1016 1017 /* Set up su_trim: T3_P1 650mv */ 1018 writel(0x90, priv->mmio + (0xa << 2)); 1019 writel(0x43, priv->mmio + (0xb << 2)); 1020 writel(0x88, priv->mmio + (0xc << 2)); 1021 writel(0x56, priv->mmio + (0xd << 2)); 1022 } 1023 1024 return 0; 1025 } 1026 1027 static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { 1028 /* pipe-phy-grf */ 1029 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 1030 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 1031 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 1032 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 1033 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 1034 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, 1035 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 1036 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 1037 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 1038 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 1039 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 1040 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 1041 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 1042 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 1043 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 1044 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 1045 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 1046 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 1047 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 1048 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 1049 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 1050 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 1051 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 1052 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 1053 /* php-grf */ 1054 .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, 1055 .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, 1056 .u3otg1_port_en = { 0x0038, 15, 0, 0x0181, 0x1100 }, 1057 }; 1058 1059 static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { 1060 .grfcfg = &rk3576_combphy_grfcfgs, 1061 .combphy_cfg = rk3576_combphy_cfg, 1062 }; 1063 #endif 1064 1065 #ifdef CONFIG_ROCKCHIP_RV1126B 1066 static int rv1126b_combphy_cfg(struct rockchip_combphy_priv *priv) 1067 { 1068 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 1069 u32 val; 1070 1071 switch (priv->mode) { 1072 case PHY_TYPE_USB3: 1073 /* Set SSC downward spread spectrum */ 1074 val = readl(priv->mmio + (0x1f << 2)); 1075 val &= ~GENMASK(5, 4); 1076 val |= 0x01 << 4; 1077 writel(val, priv->mmio + 0x7c); 1078 1079 /* Enable adaptive CTLE for USB3.0 Rx */ 1080 val = readl(priv->mmio + (0x0e << 2)); 1081 val &= ~GENMASK(0, 0); 1082 val |= 0x01; 1083 writel(val, priv->mmio + (0x0e << 2)); 1084 1085 /* Set PLL KVCO fine tuning signals */ 1086 val = readl(priv->mmio + (0x20 << 2)); 1087 val &= ~(0x7 << 2); 1088 val |= 0x2 << 2; 1089 writel(val, priv->mmio + (0x20 << 2)); 1090 1091 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 1092 writel(0x4, priv->mmio + (0x0b << 2)); 1093 1094 /* Set PLL input clock divider 1/2 */ 1095 val = readl(priv->mmio + (0x5 << 2)); 1096 val &= ~(0x3 << 6); 1097 val |= 0x1 << 6; 1098 writel(val, priv->mmio + (0x5 << 2)); 1099 1100 /* Set PLL loop divider */ 1101 writel(0x32, priv->mmio + (0x11 << 2)); 1102 1103 /* Set PLL KVCO to min and set PLL charge pump current to max */ 1104 writel(0xf0, priv->mmio + (0x0a << 2)); 1105 1106 /* Set Rx squelch input filler bandwidth */ 1107 writel(0x0e, priv->mmio + (0x14 << 2)); 1108 1109 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 1110 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 1111 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 1112 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 1113 break; 1114 default: 1115 dev_err(priv->dev, "incompatible PHY type\n"); 1116 return -EINVAL; 1117 } 1118 1119 clk_set_rate(&priv->ref_clk, 100000000); 1120 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 1121 1122 return 0; 1123 } 1124 1125 static const struct rockchip_combphy_grfcfg rv1126b_combphy_grfcfgs = { 1126 /* pipe-phy-grf */ 1127 .usb_mode_set = { 0x18000, 5, 0, 0x00, 0x04 }, 1128 .pipe_rxterm_set = { 0x18000, 12, 12, 0x00, 0x01 }, 1129 .pipe_txelec_set = { 0x18004, 1, 1, 0x00, 0x01 }, 1130 .pipe_txcomp_set = { 0x18004, 4, 4, 0x00, 0x01 }, 1131 .pipe_clk_25m = { 0x18004, 14, 13, 0x00, 0x01 }, 1132 .pipe_clk_100m = { 0x18004, 14, 13, 0x00, 0x02 }, 1133 .pipe_phymode_sel = { 0x18008, 1, 1, 0x00, 0x01 }, 1134 .pipe_rate_sel = { 0x18008, 2, 2, 0x00, 0x01 }, 1135 .pipe_rxterm_sel = { 0x18008, 8, 8, 0x00, 0x01 }, 1136 .pipe_txelec_sel = { 0x18008, 12, 12, 0x00, 0x01 }, 1137 .pipe_txcomp_sel = { 0x18008, 15, 15, 0x00, 0x01 }, 1138 .pipe_clk_ext = { 0x1800c, 9, 8, 0x02, 0x01 }, 1139 .pipe_sel_usb = { 0x1800c, 14, 13, 0x00, 0x01 }, 1140 .pipe_phy_status = { 0x18034, 6, 6, 0x01, 0x00 }, 1141 /* peri-grf */ 1142 .u3otg0_port_en = { 0x1003c, 15, 0, 0x0189, 0x1100 }, 1143 /* pmu-grf */ 1144 .u3otg0_clamp_dis = { 0x30000, 14, 14, 0x00, 0x01 }, 1145 }; 1146 1147 static const struct rockchip_combphy_cfg rv1126b_combphy_cfgs = { 1148 .grfcfg = &rv1126b_combphy_grfcfgs, 1149 .combphy_cfg = rv1126b_combphy_cfg, 1150 .force_det_out = true, 1151 }; 1152 #endif 1153 1154 static const struct udevice_id rockchip_combphy_ids[] = { 1155 #ifdef CONFIG_ROCKCHIP_RK3528 1156 { 1157 .compatible = "rockchip,rk3528-naneng-combphy", 1158 .data = (ulong)&rk3528_combphy_cfgs 1159 }, 1160 #endif 1161 #ifdef CONFIG_ROCKCHIP_RK3562 1162 { 1163 .compatible = "rockchip,rk3562-naneng-combphy", 1164 .data = (ulong)&rk3562_combphy_cfgs 1165 }, 1166 #endif 1167 #ifdef CONFIG_ROCKCHIP_RK3568 1168 { 1169 .compatible = "rockchip,rk3568-naneng-combphy", 1170 .data = (ulong)&rk3568_combphy_cfgs 1171 }, 1172 #endif 1173 #ifdef CONFIG_ROCKCHIP_RK3588 1174 { 1175 .compatible = "rockchip,rk3588-naneng-combphy", 1176 .data = (ulong)&rk3588_combphy_cfgs 1177 }, 1178 #endif 1179 #ifdef CONFIG_ROCKCHIP_RK3576 1180 { 1181 .compatible = "rockchip,rk3576-naneng-combphy", 1182 .data = (ulong)&rk3576_combphy_cfgs 1183 }, 1184 #endif 1185 #ifdef CONFIG_ROCKCHIP_RV1126B 1186 { 1187 .compatible = "rockchip,rv1126b-usb3-phy", 1188 .data = (ulong)&rv1126b_combphy_cfgs 1189 }, 1190 #endif 1191 { } 1192 }; 1193 1194 U_BOOT_DRIVER(rockchip_naneng_combphy) = { 1195 .name = "naneng-combphy", 1196 .id = UCLASS_PHY, 1197 .of_match = rockchip_combphy_ids, 1198 .ops = &rochchip_combphy_ops, 1199 .probe = rockchip_combphy_probe, 1200 .priv_auto_alloc_size = sizeof(struct rockchip_combphy_priv), 1201 }; 1202