1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dt-bindings/phy/phy.h> 13 #include <generic-phy.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <regmap.h> 18 #include <reset-uclass.h> 19 #include <linux/iopoll.h> 20 21 #define BIT_WRITEABLE_SHIFT 16 22 23 struct rockchip_combphy_priv; 24 25 struct combphy_reg { 26 u32 offset; 27 u16 bitend; 28 u16 bitstart; 29 u16 disable; 30 u16 enable; 31 }; 32 33 struct rockchip_combphy_grfcfg { 34 struct combphy_reg pcie_mode_set; 35 struct combphy_reg usb_mode_set; 36 struct combphy_reg sgmii_mode_set; 37 struct combphy_reg qsgmii_mode_set; 38 struct combphy_reg pipe_rxterm_set; 39 struct combphy_reg pipe_txelec_set; 40 struct combphy_reg pipe_txcomp_set; 41 struct combphy_reg pipe_clk_24m; 42 struct combphy_reg pipe_clk_25m; 43 struct combphy_reg pipe_clk_100m; 44 struct combphy_reg pipe_phymode_sel; 45 struct combphy_reg pipe_rate_sel; 46 struct combphy_reg pipe_rxterm_sel; 47 struct combphy_reg pipe_txelec_sel; 48 struct combphy_reg pipe_txcomp_sel; 49 struct combphy_reg pipe_clk_ext; 50 struct combphy_reg pipe_sel_usb; 51 struct combphy_reg pipe_sel_qsgmii; 52 struct combphy_reg pipe_phy_status; 53 struct combphy_reg con0_for_pcie; 54 struct combphy_reg con1_for_pcie; 55 struct combphy_reg con2_for_pcie; 56 struct combphy_reg con3_for_pcie; 57 struct combphy_reg con0_for_sata; 58 struct combphy_reg con1_for_sata; 59 struct combphy_reg con2_for_sata; 60 struct combphy_reg con3_for_sata; 61 struct combphy_reg pipe_con0_for_sata; 62 struct combphy_reg pipe_con1_for_sata; 63 struct combphy_reg pipe_sgmii_mac_sel; 64 struct combphy_reg pipe_xpcs_phy_ready; 65 struct combphy_reg u3otg0_port_en; 66 struct combphy_reg u3otg1_port_en; 67 struct combphy_reg u3otg0_pipe_clk_sel; 68 struct combphy_reg pipe_phy_grf_reset; 69 }; 70 71 struct rockchip_combphy_cfg { 72 const struct rockchip_combphy_grfcfg *grfcfg; 73 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 74 }; 75 76 struct rockchip_combphy_priv { 77 u32 mode; 78 void __iomem *mmio; 79 struct udevice *dev; 80 struct regmap *pipe_grf; 81 struct regmap *phy_grf; 82 struct phy *phy; 83 struct reset_ctl phy_rst; 84 struct clk ref_clk; 85 const struct rockchip_combphy_cfg *cfg; 86 }; 87 88 static int param_write(struct regmap *base, 89 const struct combphy_reg *reg, bool en) 90 { 91 u32 val, mask, tmp; 92 93 tmp = en ? reg->enable : reg->disable; 94 mask = GENMASK(reg->bitend, reg->bitstart); 95 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 96 97 return regmap_write(base, reg->offset, val); 98 } 99 100 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) 101 { 102 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 103 u32 mask, val; 104 105 mask = GENMASK(cfg->pipe_phy_status.bitend, 106 cfg->pipe_phy_status.bitstart); 107 108 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); 109 val = (val & mask) >> cfg->pipe_phy_status.bitstart; 110 111 return val; 112 } 113 114 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) 115 { 116 int ret = 0; 117 118 if (priv->cfg->combphy_cfg) { 119 ret = priv->cfg->combphy_cfg(priv); 120 if (ret) { 121 dev_err(priv->dev, "failed to init phy for pcie\n"); 122 return ret; 123 } 124 } 125 126 return ret; 127 } 128 129 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) 130 { 131 int ret = 0; 132 133 if (priv->cfg->combphy_cfg) { 134 ret = priv->cfg->combphy_cfg(priv); 135 if (ret) { 136 dev_err(priv->dev, "failed to init phy for usb3\n"); 137 return ret; 138 } 139 } 140 141 return ret; 142 } 143 144 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) 145 { 146 int ret = 0; 147 148 if (priv->cfg->combphy_cfg) { 149 ret = priv->cfg->combphy_cfg(priv); 150 if (ret) { 151 dev_err(priv->dev, "failed to init phy for sata\n"); 152 return ret; 153 } 154 } 155 156 return ret; 157 } 158 159 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) 160 { 161 int ret = 0; 162 163 if (priv->cfg->combphy_cfg) { 164 ret = priv->cfg->combphy_cfg(priv); 165 if (ret) { 166 dev_err(priv->dev, "failed to init phy for sgmii\n"); 167 return ret; 168 } 169 } 170 171 return ret; 172 } 173 174 int rockchip_combphy_usb3_uboot_init(void) 175 { 176 struct udevice *udev; 177 struct rockchip_combphy_priv *priv; 178 const struct rockchip_combphy_grfcfg *cfg; 179 u32 val; 180 int ret; 181 182 ret = uclass_get_device_by_driver(UCLASS_PHY, 183 DM_GET_DRIVER(rockchip_naneng_combphy), 184 &udev); 185 if (ret) { 186 pr_err("%s: get usb3-phy node failed: %d\n", __func__, ret); 187 return ret; 188 } 189 190 priv = dev_get_priv(udev); 191 priv->mode = PHY_TYPE_USB3; 192 cfg = priv->cfg->grfcfg; 193 194 rockchip_combphy_usb3_init(priv); 195 reset_deassert(&priv->phy_rst); 196 197 if (cfg->pipe_phy_grf_reset.enable) 198 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 199 200 if (priv->mode == PHY_TYPE_USB3) { 201 ret = readx_poll_timeout(rockchip_combphy_is_ready, 202 priv, val, 203 val == cfg->pipe_phy_status.enable, 204 1000); 205 if (ret) { 206 dev_err(priv->dev, "wait phy status ready timeout\n"); 207 param_write(priv->phy_grf, &cfg->usb_mode_set, false); 208 if (cfg->u3otg0_pipe_clk_sel.disable) 209 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, false); 210 return ret; 211 } 212 } 213 214 /* Select clk_usb3otg0_pipe for source clk */ 215 if (cfg->u3otg0_pipe_clk_sel.disable) 216 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, true); 217 218 return ret; 219 } 220 221 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) 222 { 223 switch (priv->mode) { 224 case PHY_TYPE_PCIE: 225 rockchip_combphy_pcie_init(priv); 226 break; 227 case PHY_TYPE_USB3: 228 rockchip_combphy_usb3_init(priv); 229 break; 230 case PHY_TYPE_SATA: 231 rockchip_combphy_sata_init(priv); 232 break; 233 case PHY_TYPE_SGMII: 234 case PHY_TYPE_QSGMII: 235 return rockchip_combphy_sgmii_init(priv); 236 default: 237 dev_err(priv->dev, "incompatible PHY type\n"); 238 return -EINVAL; 239 } 240 241 return 0; 242 } 243 244 static int rockchip_combphy_init(struct phy *phy) 245 { 246 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 247 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 248 int ret; 249 250 ret = clk_enable(&priv->ref_clk); 251 if (ret < 0 && ret != -ENOSYS) 252 return ret; 253 254 ret = rockchip_combphy_set_mode(priv); 255 if (ret) 256 goto err_clk; 257 258 reset_deassert(&priv->phy_rst); 259 260 if (cfg->pipe_phy_grf_reset.enable) 261 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 262 263 return 0; 264 265 err_clk: 266 clk_disable(&priv->ref_clk); 267 268 return ret; 269 } 270 271 static int rockchip_combphy_exit(struct phy *phy) 272 { 273 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 274 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 275 276 if (cfg->pipe_phy_grf_reset.enable) 277 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); 278 279 reset_assert(&priv->phy_rst); 280 clk_disable(&priv->ref_clk); 281 282 return 0; 283 } 284 285 static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) 286 { 287 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 288 289 if (args->args_count != 1) { 290 pr_err("invalid number of arguments\n"); 291 return -EINVAL; 292 } 293 294 priv->mode = args->args[0]; 295 296 return 0; 297 } 298 299 static const struct phy_ops rochchip_combphy_ops = { 300 .init = rockchip_combphy_init, 301 .exit = rockchip_combphy_exit, 302 .of_xlate = rockchip_combphy_xlate, 303 }; 304 305 static int rockchip_combphy_parse_dt(struct udevice *dev, 306 struct rockchip_combphy_priv *priv) 307 { 308 struct udevice *syscon; 309 int ret; 310 u32 vals[4]; 311 312 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); 313 if (ret) { 314 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap ret= %d\n", ret); 315 return ret; 316 } 317 priv->pipe_grf = syscon_get_regmap(syscon); 318 319 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); 320 if (ret) { 321 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 322 return ret; 323 } 324 priv->phy_grf = syscon_get_regmap(syscon); 325 326 ret = clk_get_by_index(dev, 0, &priv->ref_clk); 327 if (ret) { 328 dev_err(dev, "failed to find ref clock\n"); 329 return PTR_ERR(&priv->ref_clk); 330 } 331 332 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); 333 if (ret) { 334 dev_err(dev, "no phy reset control specified\n"); 335 return ret; 336 } 337 338 if (!dev_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", 339 vals, ARRAY_SIZE(vals))) 340 regmap_write(priv->pipe_grf, vals[0], 341 (GENMASK(vals[2], vals[1]) << 16) | vals[3]); 342 343 return 0; 344 } 345 346 static int rockchip_combphy_probe(struct udevice *udev) 347 { 348 struct rockchip_combphy_priv *priv = dev_get_priv(udev); 349 const struct rockchip_combphy_cfg *phy_cfg; 350 351 priv->mmio = (void __iomem *)dev_read_addr(udev); 352 if (IS_ERR(priv->mmio)) 353 return PTR_ERR(priv->mmio); 354 355 phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); 356 if (!phy_cfg) { 357 dev_err(udev, "No OF match data provided\n"); 358 return -EINVAL; 359 } 360 361 priv->dev = udev; 362 priv->mode = PHY_TYPE_SATA; 363 priv->cfg = phy_cfg; 364 365 return rockchip_combphy_parse_dt(udev, priv); 366 } 367 368 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) 369 { 370 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 371 u32 val; 372 373 switch (priv->mode) { 374 case PHY_TYPE_PCIE: 375 /* Set SSC downward spread spectrum */ 376 val = readl(priv->mmio + 0x18); 377 val &= ~GENMASK(5, 4); 378 val |= 0x01 << 4; 379 writel(val, priv->mmio + 0x18); 380 381 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 382 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 383 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 384 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 385 break; 386 case PHY_TYPE_USB3: 387 /* Set SSC downward spread spectrum */ 388 val = readl(priv->mmio + 0x18); 389 val &= ~GENMASK(5, 4); 390 val |= 0x01 << 4; 391 writel(val, priv->mmio + 0x18); 392 393 /* Enable adaptive CTLE for USB3.0 Rx */ 394 val = readl(priv->mmio + 0x200); 395 val &= ~GENMASK(17, 17); 396 val |= 0x01; 397 writel(val, priv->mmio + 0x200); 398 399 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 400 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 401 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 402 break; 403 default: 404 dev_err(priv->dev, "incompatible PHY type\n"); 405 return -EINVAL; 406 } 407 408 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 409 if (priv->mode == PHY_TYPE_PCIE) { 410 /* PLL KVCO tuning fine */ 411 val = readl(priv->mmio + 0x18); 412 val &= ~(0x7 << 10); 413 val |= 0x2 << 10; 414 writel(val, priv->mmio + 0x18); 415 416 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ 417 val = readl(priv->mmio + 0x108); 418 val &= ~(0x7f7); 419 val |= 0x4f0; 420 writel(val, priv->mmio + 0x108); 421 } 422 423 return 0; 424 } 425 426 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { 427 /* pipe-phy-grf */ 428 .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 }, 429 .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 }, 430 .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 }, 431 .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 }, 432 .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 }, 433 .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 }, 434 .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 }, 435 .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 }, 436 .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 }, 437 .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 }, 438 .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 }, 439 .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 }, 440 .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 }, 441 .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 }, 442 .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 }, 443 .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 }, 444 /* pipe-grf */ 445 .u3otg0_pipe_clk_sel = { 0x40044, 7, 7, 0x01, 0x00 }, 446 .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 }, 447 }; 448 449 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { 450 .grfcfg = &rk3528_combphy_grfcfgs, 451 .combphy_cfg = rk3528_combphy_cfg, 452 }; 453 454 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) 455 { 456 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 457 u32 val; 458 459 switch (priv->mode) { 460 case PHY_TYPE_PCIE: 461 /* Set SSC downward spread spectrum */ 462 val = readl(priv->mmio + (0x1f << 2)); 463 val &= ~GENMASK(5, 4); 464 val |= 0x01 << 4; 465 writel(val, priv->mmio + 0x7c); 466 467 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 468 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 469 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 470 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 471 break; 472 case PHY_TYPE_USB3: 473 /* Set SSC downward spread spectrum */ 474 val = readl(priv->mmio + (0x1f << 2)); 475 val &= ~GENMASK(5, 4); 476 val |= 0x01 << 4; 477 writel(val, priv->mmio + 0x7c); 478 479 /* Enable adaptive CTLE for USB3.0 Rx */ 480 val = readl(priv->mmio + (0x0e << 2)); 481 val &= ~GENMASK(0, 0); 482 val |= 0x01; 483 writel(val, priv->mmio + (0x0e << 2)); 484 485 /* Set PLL KVCO fine tuning signals */ 486 val = readl(priv->mmio + (0x20 << 2)); 487 val &= ~(0x7 << 2); 488 val |= 0x2 << 2; 489 writel(val, priv->mmio + (0x20 << 2)); 490 491 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 492 writel(0x4, priv->mmio + (0xb << 2)); 493 494 /* Set PLL input clock divider 1/2 */ 495 val = readl(priv->mmio + (0x5 << 2)); 496 val &= ~(0x3 << 6); 497 val |= 0x1 << 6; 498 writel(val, priv->mmio + (0x5 << 2)); 499 500 /* Set PLL loop divider */ 501 writel(0x32, priv->mmio + (0x11 << 2)); 502 503 /* Set PLL KVCO to min and set PLL charge pump current to max */ 504 writel(0xf0, priv->mmio + (0xa << 2)); 505 506 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 507 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 508 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 509 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 510 break; 511 default: 512 pr_err("%s, phy-type %d\n", __func__, priv->mode); 513 return -EINVAL; 514 } 515 516 clk_set_rate(&priv->ref_clk, 100000000); 517 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 518 519 if (priv->mode == PHY_TYPE_PCIE) { 520 /* PLL KVCO tuning fine */ 521 val = readl(priv->mmio + (0x20 << 2)); 522 val &= ~(0x7 << 2); 523 val |= 0x2 << 2; 524 writel(val, priv->mmio + (0x20 << 2)); 525 526 /* Enable controlling random jitter, aka RMJ */ 527 writel(0x4, priv->mmio + (0xb << 2)); 528 529 val = readl(priv->mmio + (0x5 << 2)); 530 val &= ~(0x3 << 6); 531 val |= 0x1 << 6; 532 writel(val, priv->mmio + (0x5 << 2)); 533 534 writel(0x32, priv->mmio + (0x11 << 2)); 535 writel(0xf0, priv->mmio + (0xa << 2)); 536 } 537 538 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 539 val = readl(priv->mmio + (0x7 << 2)); 540 val |= BIT(4); 541 writel(val, priv->mmio + (0x7 << 2)); 542 } 543 544 return 0; 545 } 546 547 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { 548 /* pipe-phy-grf */ 549 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 550 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 551 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 552 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 553 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 554 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 555 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 556 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 557 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 558 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 559 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 560 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 561 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 562 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 563 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 564 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 565 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 566 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 567 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 568 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 569 /* pipe-grf */ 570 .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 }, 571 }; 572 573 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { 574 .grfcfg = &rk3562_combphy_grfcfgs, 575 .combphy_cfg = rk3562_combphy_cfg, 576 }; 577 578 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 579 { 580 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 581 u32 val; 582 583 switch (priv->mode) { 584 case PHY_TYPE_PCIE: 585 /* Set SSC downward spread spectrum */ 586 val = readl(priv->mmio + (0x1f << 2)); 587 val &= ~GENMASK(5, 4); 588 val |= 0x01 << 4; 589 writel(val, priv->mmio + 0x7c); 590 591 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 592 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 593 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 594 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 595 break; 596 case PHY_TYPE_USB3: 597 /* Set SSC downward spread spectrum */ 598 val = readl(priv->mmio + (0x1f << 2)); 599 val &= ~GENMASK(5, 4); 600 val |= 0x01 << 4; 601 writel(val, priv->mmio + 0x7c); 602 603 /* Enable adaptive CTLE for USB3.0 Rx */ 604 val = readl(priv->mmio + (0x0e << 2)); 605 val &= ~GENMASK(0, 0); 606 val |= 0x01; 607 writel(val, priv->mmio + (0x0e << 2)); 608 609 /* Set PLL KVCO fine tuning signals */ 610 val = readl(priv->mmio + (0x20 << 2)); 611 val &= ~(0x7 << 2); 612 val |= 0x2 << 2; 613 writel(val, priv->mmio + (0x20 << 2)); 614 615 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 616 writel(0x4, priv->mmio + (0xb << 2)); 617 618 /* Set PLL input clock divider 1/2 */ 619 val = readl(priv->mmio + (0x5 << 2)); 620 val &= ~(0x3 << 6); 621 val |= 0x1 << 6; 622 writel(val, priv->mmio + (0x5 << 2)); 623 624 /* Set PLL loop divider */ 625 writel(0x32, priv->mmio + (0x11 << 2)); 626 627 /* Set PLL KVCO to min and set PLL charge pump current to max */ 628 writel(0xf0, priv->mmio + (0xa << 2)); 629 630 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 631 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 632 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 633 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 634 break; 635 case PHY_TYPE_SATA: 636 writel(0x41, priv->mmio + 0x38); 637 writel(0x8F, priv->mmio + 0x18); 638 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 639 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 640 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 641 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 642 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 643 break; 644 case PHY_TYPE_SGMII: 645 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 646 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 647 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 648 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 649 break; 650 case PHY_TYPE_QSGMII: 651 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 652 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 653 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 654 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 655 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 656 break; 657 default: 658 pr_err("%s, phy-type %d\n", __func__, priv->mode); 659 return -EINVAL; 660 } 661 662 /* The default ref clock is 25Mhz */ 663 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 664 665 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 666 val = readl(priv->mmio + (0x7 << 2)); 667 val |= BIT(4); 668 writel(val, priv->mmio + (0x7 << 2)); 669 } 670 671 return 0; 672 } 673 674 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 675 /* pipe-phy-grf */ 676 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 677 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 678 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 679 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 680 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 681 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 682 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 683 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 684 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 685 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 686 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 687 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 688 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 689 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 690 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 691 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 692 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 693 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 694 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 695 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 696 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 697 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 698 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 699 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 700 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 701 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 702 /* pipe-grf */ 703 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 704 .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, 705 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 706 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 707 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 708 }; 709 710 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 711 .grfcfg = &rk3568_combphy_grfcfgs, 712 .combphy_cfg = rk3568_combphy_cfg, 713 }; 714 715 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 716 { 717 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 718 u32 val; 719 720 switch (priv->mode) { 721 case PHY_TYPE_PCIE: 722 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 723 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 724 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 725 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 726 break; 727 case PHY_TYPE_USB3: 728 /* Set SSC downward spread spectrum */ 729 val = readl(priv->mmio + (0x1f << 2)); 730 val &= ~GENMASK(5, 4); 731 val |= 0x01 << 4; 732 writel(val, priv->mmio + 0x7c); 733 734 /* Enable adaptive CTLE for USB3.0 Rx */ 735 val = readl(priv->mmio + (0x0e << 2)); 736 val &= ~GENMASK(0, 0); 737 val |= 0x01; 738 writel(val, priv->mmio + (0x0e << 2)); 739 740 /* Set PLL KVCO fine tuning signals */ 741 val = readl(priv->mmio + (0x20 << 2)); 742 val &= ~(0x7 << 2); 743 val |= 0x2 << 2; 744 writel(val, priv->mmio + (0x20 << 2)); 745 746 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 747 writel(0x4, priv->mmio + (0xb << 2)); 748 749 /* Set PLL input clock divider 1/2 */ 750 val = readl(priv->mmio + (0x5 << 2)); 751 val &= ~(0x3 << 6); 752 val |= 0x1 << 6; 753 writel(val, priv->mmio + (0x5 << 2)); 754 755 /* Set PLL loop divider */ 756 writel(0x32, priv->mmio + (0x11 << 2)); 757 758 /* Set PLL KVCO to min and set PLL charge pump current to max */ 759 writel(0xf0, priv->mmio + (0xa << 2)); 760 761 /* Set Rx squelch input filler bandwidth */ 762 writel(0x0d, priv->mmio + (0x14 << 2)); 763 764 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 765 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 766 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 767 break; 768 case PHY_TYPE_SATA: 769 /* Enable adaptive CTLE for SATA Rx */ 770 val = readl(priv->mmio + (0x0e << 2)); 771 val &= ~GENMASK(0, 0); 772 val |= 0x01; 773 writel(val, priv->mmio + (0x0e << 2)); 774 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 775 writel(0x8F, priv->mmio + (0x06 << 2)); 776 777 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 778 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 779 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 780 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 781 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 782 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 783 break; 784 case PHY_TYPE_SGMII: 785 case PHY_TYPE_QSGMII: 786 default: 787 dev_err(priv->dev, "incompatible PHY type\n"); 788 return -EINVAL; 789 } 790 791 /* 100MHz refclock signal is good */ 792 clk_set_rate(&priv->ref_clk, 100000000); 793 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 794 if (priv->mode == PHY_TYPE_PCIE) { 795 /* PLL KVCO tuning fine */ 796 val = readl(priv->mmio + (0x20 << 2)); 797 val &= ~GENMASK(4, 2); 798 val |= 0x4 << 2; 799 writel(val, priv->mmio + (0x20 << 2)); 800 801 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 802 val = 0x4c; 803 writel(val, priv->mmio + (0x1b << 2)); 804 805 /* Set up su_trim: T3 */ 806 val = 0xb0; 807 writel(val, priv->mmio + (0xa << 2)); 808 val = 0x47; 809 writel(val, priv->mmio + (0xb << 2)); 810 val = 0x57; 811 writel(val, priv->mmio + (0xd << 2)); 812 } 813 814 return 0; 815 } 816 817 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 818 /* pipe-phy-grf */ 819 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 820 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 821 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 822 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 823 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 824 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 825 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 826 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 827 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 828 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 829 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 830 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 831 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 832 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 833 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 834 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 835 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 836 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 837 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 838 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 839 /* pipe-grf */ 840 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 841 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 842 }; 843 844 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 845 .grfcfg = &rk3588_combphy_grfcfgs, 846 .combphy_cfg = rk3588_combphy_cfg, 847 }; 848 849 static const struct udevice_id rockchip_combphy_ids[] = { 850 { 851 .compatible = "rockchip,rk3528-naneng-combphy", 852 .data = (ulong)&rk3528_combphy_cfgs 853 }, 854 { 855 .compatible = "rockchip,rk3562-naneng-combphy", 856 .data = (ulong)&rk3562_combphy_cfgs 857 }, 858 { 859 .compatible = "rockchip,rk3568-naneng-combphy", 860 .data = (ulong)&rk3568_combphy_cfgs 861 }, 862 { 863 .compatible = "rockchip,rk3588-naneng-combphy", 864 .data = (ulong)&rk3588_combphy_cfgs 865 }, 866 { } 867 }; 868 869 U_BOOT_DRIVER(rockchip_naneng_combphy) = { 870 .name = "naneng-combphy", 871 .id = UCLASS_PHY, 872 .of_match = rockchip_combphy_ids, 873 .ops = &rochchip_combphy_ops, 874 .probe = rockchip_combphy_probe, 875 .priv_auto_alloc_size = sizeof(struct rockchip_combphy_priv), 876 }; 877