1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dm/uclass-internal.h> 13 #include <dt-bindings/phy/phy.h> 14 #include <generic-phy.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <regmap.h> 19 #include <reset-uclass.h> 20 #include <linux/iopoll.h> 21 22 #define BIT_WRITEABLE_SHIFT 16 23 24 struct rockchip_combphy_priv; 25 26 struct combphy_reg { 27 u32 offset; 28 u16 bitend; 29 u16 bitstart; 30 u16 disable; 31 u16 enable; 32 }; 33 34 struct rockchip_combphy_grfcfg { 35 struct combphy_reg pcie_mode_set; 36 struct combphy_reg usb_mode_set; 37 struct combphy_reg sgmii_mode_set; 38 struct combphy_reg qsgmii_mode_set; 39 struct combphy_reg pipe_rxterm_set; 40 struct combphy_reg pipe_txelec_set; 41 struct combphy_reg pipe_txcomp_set; 42 struct combphy_reg pipe_clk_24m; 43 struct combphy_reg pipe_clk_25m; 44 struct combphy_reg pipe_clk_100m; 45 struct combphy_reg pipe_phymode_sel; 46 struct combphy_reg pipe_rate_sel; 47 struct combphy_reg pipe_rxterm_sel; 48 struct combphy_reg pipe_txelec_sel; 49 struct combphy_reg pipe_txcomp_sel; 50 struct combphy_reg pipe_clk_ext; 51 struct combphy_reg pipe_sel_usb; 52 struct combphy_reg pipe_sel_qsgmii; 53 struct combphy_reg pipe_phy_status; 54 struct combphy_reg con0_for_pcie; 55 struct combphy_reg con1_for_pcie; 56 struct combphy_reg con2_for_pcie; 57 struct combphy_reg con3_for_pcie; 58 struct combphy_reg con0_for_sata; 59 struct combphy_reg con1_for_sata; 60 struct combphy_reg con2_for_sata; 61 struct combphy_reg con3_for_sata; 62 struct combphy_reg pipe_con0_for_sata; 63 struct combphy_reg pipe_con1_for_sata; 64 struct combphy_reg pipe_sgmii_mac_sel; 65 struct combphy_reg pipe_xpcs_phy_ready; 66 struct combphy_reg u3otg0_port_en; 67 struct combphy_reg u3otg1_port_en; 68 struct combphy_reg u3otg0_pipe_clk_sel; 69 struct combphy_reg pipe_phy_grf_reset; 70 }; 71 72 struct rockchip_combphy_cfg { 73 const struct rockchip_combphy_grfcfg *grfcfg; 74 bool force_det_out; /* Tx detect Rx errata */ 75 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 76 }; 77 78 struct rockchip_combphy_priv { 79 u32 mode; 80 void __iomem *mmio; 81 struct udevice *dev; 82 struct regmap *pipe_grf; 83 struct regmap *phy_grf; 84 struct phy *phy; 85 struct reset_ctl phy_rst; 86 struct clk ref_clk; 87 const struct rockchip_combphy_cfg *cfg; 88 }; 89 90 static int param_write(struct regmap *base, 91 const struct combphy_reg *reg, bool en) 92 { 93 u32 val, mask, tmp; 94 95 tmp = en ? reg->enable : reg->disable; 96 mask = GENMASK(reg->bitend, reg->bitstart); 97 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 98 99 return regmap_write(base, reg->offset, val); 100 } 101 102 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) 103 { 104 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 105 u32 mask, val; 106 107 mask = GENMASK(cfg->pipe_phy_status.bitend, 108 cfg->pipe_phy_status.bitstart); 109 110 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); 111 val = (val & mask) >> cfg->pipe_phy_status.bitstart; 112 113 return val; 114 } 115 116 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) 117 { 118 int ret = 0; 119 u32 val; 120 121 if (priv->cfg->combphy_cfg) { 122 ret = priv->cfg->combphy_cfg(priv); 123 if (ret) { 124 dev_err(priv->dev, "failed to init phy for pcie\n"); 125 return ret; 126 } 127 } 128 129 if (priv->cfg->force_det_out) { 130 val = readl(priv->mmio + (0x19 << 2)); 131 val |= BIT(5); 132 writel(val, priv->mmio + (0x19 << 2)); 133 } 134 135 return ret; 136 } 137 138 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) 139 { 140 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 141 int ret = 0; 142 143 if (dev_read_bool(priv->dev, "rockchip,dis-u3otg0-port")) { 144 ret = param_write(priv->pipe_grf, &cfg->u3otg0_port_en, false); 145 return ret; 146 } else if (dev_read_bool(priv->dev, "rockchip,dis-u3otg1-port")) { 147 param_write(priv->pipe_grf, &cfg->u3otg1_port_en, false); 148 #ifdef CONFIG_ROCKCHIP_RK3576 149 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 150 #endif 151 return ret; 152 } 153 154 if (priv->cfg->combphy_cfg) { 155 ret = priv->cfg->combphy_cfg(priv); 156 if (ret) { 157 dev_err(priv->dev, "failed to init phy for usb3\n"); 158 return ret; 159 } 160 } 161 162 return ret; 163 } 164 165 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) 166 { 167 int ret = 0; 168 169 if (priv->cfg->combphy_cfg) { 170 ret = priv->cfg->combphy_cfg(priv); 171 if (ret) { 172 dev_err(priv->dev, "failed to init phy for sata\n"); 173 return ret; 174 } 175 } 176 177 return ret; 178 } 179 180 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) 181 { 182 int ret = 0; 183 184 if (priv->cfg->combphy_cfg) { 185 ret = priv->cfg->combphy_cfg(priv); 186 if (ret) { 187 dev_err(priv->dev, "failed to init phy for sgmii\n"); 188 return ret; 189 } 190 } 191 192 return ret; 193 } 194 195 int rockchip_combphy_usb3_uboot_init(fdt_addr_t phy_addr) 196 { 197 struct udevice *udev = NULL; 198 struct udevice *dev; 199 struct uclass *uc; 200 const struct driver *find_drv; 201 struct rockchip_combphy_priv *priv; 202 const struct rockchip_combphy_grfcfg *cfg; 203 u32 val; 204 int ret = 0; 205 206 ret = uclass_get(UCLASS_PHY, &uc); 207 if (ret) 208 return ret; 209 210 find_drv = DM_GET_DRIVER(rockchip_naneng_combphy); 211 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 212 if (dev->driver == find_drv && dev_read_addr(dev) == phy_addr) { 213 ret = uclass_get_device_tail(dev, 0, &udev); 214 break; 215 } 216 } 217 218 if (!udev || ret) { 219 ret = ret ? ret : -ENODEV; 220 pr_err("%s: get usb3-phy node failed: %d\n", __func__, ret); 221 return ret; 222 } 223 224 priv = dev_get_priv(udev); 225 priv->mode = PHY_TYPE_USB3; 226 cfg = priv->cfg->grfcfg; 227 228 rockchip_combphy_usb3_init(priv); 229 reset_deassert(&priv->phy_rst); 230 231 if (cfg->pipe_phy_grf_reset.enable) 232 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 233 234 if (priv->mode == PHY_TYPE_USB3) { 235 ret = readx_poll_timeout(rockchip_combphy_is_ready, 236 priv, val, 237 val == cfg->pipe_phy_status.enable, 238 1000); 239 if (ret) { 240 dev_err(priv->dev, "wait phy status ready timeout\n"); 241 param_write(priv->phy_grf, &cfg->usb_mode_set, false); 242 if (cfg->u3otg0_pipe_clk_sel.disable) 243 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, false); 244 return ret; 245 } 246 } 247 248 /* Select clk_usb3otg0_pipe for source clk */ 249 if (cfg->u3otg0_pipe_clk_sel.disable) 250 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, true); 251 252 return ret; 253 } 254 255 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) 256 { 257 switch (priv->mode) { 258 case PHY_TYPE_PCIE: 259 rockchip_combphy_pcie_init(priv); 260 break; 261 case PHY_TYPE_USB3: 262 rockchip_combphy_usb3_init(priv); 263 break; 264 case PHY_TYPE_SATA: 265 rockchip_combphy_sata_init(priv); 266 break; 267 case PHY_TYPE_SGMII: 268 case PHY_TYPE_QSGMII: 269 return rockchip_combphy_sgmii_init(priv); 270 default: 271 dev_err(priv->dev, "incompatible PHY type\n"); 272 return -EINVAL; 273 } 274 275 return 0; 276 } 277 278 static int rockchip_combphy_init(struct phy *phy) 279 { 280 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 281 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 282 int ret; 283 284 ret = clk_enable(&priv->ref_clk); 285 if (ret < 0 && ret != -ENOSYS) 286 return ret; 287 288 ret = rockchip_combphy_set_mode(priv); 289 if (ret) 290 goto err_clk; 291 292 reset_deassert(&priv->phy_rst); 293 294 if (cfg->pipe_phy_grf_reset.enable) 295 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 296 297 return 0; 298 299 err_clk: 300 clk_disable(&priv->ref_clk); 301 302 return ret; 303 } 304 305 static int rockchip_combphy_exit(struct phy *phy) 306 { 307 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 308 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 309 310 if (cfg->pipe_phy_grf_reset.enable) 311 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); 312 313 reset_assert(&priv->phy_rst); 314 clk_disable(&priv->ref_clk); 315 316 return 0; 317 } 318 319 static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) 320 { 321 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 322 323 if (args->args_count != 1) { 324 pr_err("invalid number of arguments\n"); 325 return -EINVAL; 326 } 327 328 priv->mode = args->args[0]; 329 330 return 0; 331 } 332 333 static const struct phy_ops rochchip_combphy_ops = { 334 .init = rockchip_combphy_init, 335 .exit = rockchip_combphy_exit, 336 .of_xlate = rockchip_combphy_xlate, 337 }; 338 339 static int rockchip_combphy_parse_dt(struct udevice *dev, 340 struct rockchip_combphy_priv *priv) 341 { 342 struct udevice *syscon; 343 int ret; 344 u32 vals[4]; 345 346 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); 347 if (ret) { 348 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap ret= %d\n", ret); 349 return ret; 350 } 351 priv->pipe_grf = syscon_get_regmap(syscon); 352 353 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); 354 if (ret) { 355 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 356 return ret; 357 } 358 priv->phy_grf = syscon_get_regmap(syscon); 359 360 ret = clk_get_by_index(dev, 0, &priv->ref_clk); 361 if (ret) { 362 dev_err(dev, "failed to find ref clock\n"); 363 return PTR_ERR(&priv->ref_clk); 364 } 365 366 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); 367 if (ret) { 368 dev_err(dev, "no phy reset control specified\n"); 369 return ret; 370 } 371 372 if (!dev_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", 373 vals, ARRAY_SIZE(vals))) 374 regmap_write(priv->pipe_grf, vals[0], 375 (GENMASK(vals[2], vals[1]) << 16) | vals[3]); 376 377 return 0; 378 } 379 380 static int rockchip_combphy_probe(struct udevice *udev) 381 { 382 struct rockchip_combphy_priv *priv = dev_get_priv(udev); 383 const struct rockchip_combphy_cfg *phy_cfg; 384 385 priv->mmio = (void __iomem *)dev_read_addr(udev); 386 if (IS_ERR(priv->mmio)) 387 return PTR_ERR(priv->mmio); 388 389 phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); 390 if (!phy_cfg) { 391 dev_err(udev, "No OF match data provided\n"); 392 return -EINVAL; 393 } 394 395 priv->dev = udev; 396 priv->mode = PHY_TYPE_SATA; 397 priv->cfg = phy_cfg; 398 399 return rockchip_combphy_parse_dt(udev, priv); 400 } 401 402 #ifdef CONFIG_ROCKCHIP_RK3528 403 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) 404 { 405 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 406 u32 val; 407 408 switch (priv->mode) { 409 case PHY_TYPE_PCIE: 410 /* Set SSC downward spread spectrum */ 411 val = readl(priv->mmio + 0x18); 412 val &= ~GENMASK(5, 4); 413 val |= 0x01 << 4; 414 writel(val, priv->mmio + 0x18); 415 416 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 417 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 418 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 419 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 420 break; 421 case PHY_TYPE_USB3: 422 /* Set SSC downward spread spectrum */ 423 val = readl(priv->mmio + 0x18); 424 val &= ~GENMASK(5, 4); 425 val |= 0x01 << 4; 426 writel(val, priv->mmio + 0x18); 427 428 /* Enable adaptive CTLE for USB3.0 Rx */ 429 val = readl(priv->mmio + 0x200); 430 val &= ~GENMASK(17, 17); 431 val |= 0x01; 432 writel(val, priv->mmio + 0x200); 433 434 /* Set Rx squelch input filler bandwidth */ 435 val = readl(priv->mmio + 0x20c); 436 val &= ~GENMASK(2, 0); 437 val |= 0x06; 438 writel(val, priv->mmio + 0x20c); 439 440 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 441 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 442 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 443 break; 444 default: 445 dev_err(priv->dev, "incompatible PHY type\n"); 446 return -EINVAL; 447 } 448 449 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 450 if (priv->mode == PHY_TYPE_PCIE) { 451 /* PLL KVCO tuning fine */ 452 val = readl(priv->mmio + 0x18); 453 val &= ~(0x7 << 10); 454 val |= 0x2 << 10; 455 writel(val, priv->mmio + 0x18); 456 457 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ 458 val = readl(priv->mmio + 0x108); 459 val &= ~(0x7f7); 460 val |= 0x4f0; 461 writel(val, priv->mmio + 0x108); 462 } 463 464 return 0; 465 } 466 467 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { 468 /* pipe-phy-grf */ 469 .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 }, 470 .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 }, 471 .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 }, 472 .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 }, 473 .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 }, 474 .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 }, 475 .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 }, 476 .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 }, 477 .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 }, 478 .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 }, 479 .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 }, 480 .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 }, 481 .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 }, 482 .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 }, 483 .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 }, 484 .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 }, 485 /* pipe-grf */ 486 .u3otg0_pipe_clk_sel = { 0x40044, 7, 7, 0x01, 0x00 }, 487 .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 }, 488 }; 489 490 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { 491 .grfcfg = &rk3528_combphy_grfcfgs, 492 .combphy_cfg = rk3528_combphy_cfg, 493 }; 494 #endif 495 496 #ifdef CONFIG_ROCKCHIP_RK3562 497 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) 498 { 499 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 500 u32 val; 501 502 switch (priv->mode) { 503 case PHY_TYPE_PCIE: 504 /* Set SSC downward spread spectrum */ 505 val = readl(priv->mmio + (0x1f << 2)); 506 val &= ~GENMASK(5, 4); 507 val |= 0x01 << 4; 508 writel(val, priv->mmio + 0x7c); 509 510 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 511 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 512 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 513 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 514 break; 515 case PHY_TYPE_USB3: 516 /* Set SSC downward spread spectrum */ 517 val = readl(priv->mmio + (0x1f << 2)); 518 val &= ~GENMASK(5, 4); 519 val |= 0x01 << 4; 520 writel(val, priv->mmio + 0x7c); 521 522 /* Enable adaptive CTLE for USB3.0 Rx */ 523 val = readl(priv->mmio + (0x0e << 2)); 524 val &= ~GENMASK(0, 0); 525 val |= 0x01; 526 writel(val, priv->mmio + (0x0e << 2)); 527 528 /* Set PLL KVCO fine tuning signals */ 529 val = readl(priv->mmio + (0x20 << 2)); 530 val &= ~(0x7 << 2); 531 val |= 0x2 << 2; 532 writel(val, priv->mmio + (0x20 << 2)); 533 534 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 535 writel(0x4, priv->mmio + (0xb << 2)); 536 537 /* Set PLL input clock divider 1/2 */ 538 val = readl(priv->mmio + (0x5 << 2)); 539 val &= ~(0x3 << 6); 540 val |= 0x1 << 6; 541 writel(val, priv->mmio + (0x5 << 2)); 542 543 /* Set PLL loop divider */ 544 writel(0x32, priv->mmio + (0x11 << 2)); 545 546 /* Set PLL KVCO to min and set PLL charge pump current to max */ 547 writel(0xf0, priv->mmio + (0xa << 2)); 548 549 /* Set Rx squelch input filler bandwidth */ 550 writel(0x0e, priv->mmio + (0x14 << 2)); 551 552 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 553 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 554 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 555 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 556 break; 557 default: 558 pr_err("%s, phy-type %d\n", __func__, priv->mode); 559 return -EINVAL; 560 } 561 562 clk_set_rate(&priv->ref_clk, 100000000); 563 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 564 565 if (priv->mode == PHY_TYPE_PCIE) { 566 /* PLL KVCO tuning fine */ 567 val = readl(priv->mmio + (0x20 << 2)); 568 val &= ~(0x7 << 2); 569 val |= 0x2 << 2; 570 writel(val, priv->mmio + (0x20 << 2)); 571 572 /* Enable controlling random jitter, aka RMJ */ 573 writel(0x4, priv->mmio + (0xb << 2)); 574 575 val = readl(priv->mmio + (0x5 << 2)); 576 val &= ~(0x3 << 6); 577 val |= 0x1 << 6; 578 writel(val, priv->mmio + (0x5 << 2)); 579 580 writel(0x32, priv->mmio + (0x11 << 2)); 581 writel(0xf0, priv->mmio + (0xa << 2)); 582 } 583 584 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 585 val = readl(priv->mmio + (0x7 << 2)); 586 val |= BIT(4); 587 writel(val, priv->mmio + (0x7 << 2)); 588 } 589 590 return 0; 591 } 592 593 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { 594 /* pipe-phy-grf */ 595 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 596 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 597 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 598 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 599 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 600 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 601 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 602 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 603 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 604 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 605 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 606 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 607 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 608 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 609 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 610 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 611 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 612 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 613 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 614 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 615 /* pipe-grf */ 616 .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 }, 617 }; 618 619 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { 620 .grfcfg = &rk3562_combphy_grfcfgs, 621 .combphy_cfg = rk3562_combphy_cfg, 622 .force_det_out = true, 623 }; 624 #endif 625 626 #ifdef CONFIG_ROCKCHIP_RK3568 627 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 628 { 629 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 630 u32 val; 631 632 switch (priv->mode) { 633 case PHY_TYPE_PCIE: 634 /* Set SSC downward spread spectrum */ 635 val = readl(priv->mmio + (0x1f << 2)); 636 val &= ~GENMASK(5, 4); 637 val |= 0x01 << 4; 638 writel(val, priv->mmio + 0x7c); 639 640 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 641 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 642 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 643 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 644 break; 645 case PHY_TYPE_USB3: 646 /* Set SSC downward spread spectrum */ 647 val = readl(priv->mmio + (0x1f << 2)); 648 val &= ~GENMASK(5, 4); 649 val |= 0x01 << 4; 650 writel(val, priv->mmio + 0x7c); 651 652 /* Enable adaptive CTLE for USB3.0 Rx */ 653 val = readl(priv->mmio + (0x0e << 2)); 654 val &= ~GENMASK(0, 0); 655 val |= 0x01; 656 writel(val, priv->mmio + (0x0e << 2)); 657 658 /* Set PLL KVCO fine tuning signals */ 659 val = readl(priv->mmio + (0x20 << 2)); 660 val &= ~(0x7 << 2); 661 val |= 0x2 << 2; 662 writel(val, priv->mmio + (0x20 << 2)); 663 664 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 665 writel(0x4, priv->mmio + (0xb << 2)); 666 667 /* Set PLL input clock divider 1/2 */ 668 val = readl(priv->mmio + (0x5 << 2)); 669 val &= ~(0x3 << 6); 670 val |= 0x1 << 6; 671 writel(val, priv->mmio + (0x5 << 2)); 672 673 /* Set PLL loop divider */ 674 writel(0x32, priv->mmio + (0x11 << 2)); 675 676 /* Set PLL KVCO to min and set PLL charge pump current to max */ 677 writel(0xf0, priv->mmio + (0xa << 2)); 678 679 /* Set Rx squelch input filler bandwidth */ 680 writel(0x0e, priv->mmio + (0x14 << 2)); 681 682 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 683 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 684 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 685 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 686 break; 687 case PHY_TYPE_SATA: 688 writel(0x41, priv->mmio + 0x38); 689 writel(0x8F, priv->mmio + 0x18); 690 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 691 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 692 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 693 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 694 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 695 break; 696 case PHY_TYPE_SGMII: 697 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 698 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 699 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 700 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 701 break; 702 case PHY_TYPE_QSGMII: 703 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 704 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 705 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 706 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 707 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 708 break; 709 default: 710 pr_err("%s, phy-type %d\n", __func__, priv->mode); 711 return -EINVAL; 712 } 713 714 /* The default ref clock is 25Mhz */ 715 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 716 717 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 718 val = readl(priv->mmio + (0x7 << 2)); 719 val |= BIT(4); 720 writel(val, priv->mmio + (0x7 << 2)); 721 } 722 723 return 0; 724 } 725 726 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 727 /* pipe-phy-grf */ 728 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 729 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 730 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 731 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 732 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 733 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 734 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 735 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 736 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 737 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 738 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 739 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 740 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 741 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 742 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 743 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 744 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 745 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 746 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 747 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 748 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 749 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 750 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 751 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 752 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 753 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 754 /* pipe-grf */ 755 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 756 .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, 757 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 758 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 759 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 760 }; 761 762 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 763 .grfcfg = &rk3568_combphy_grfcfgs, 764 .combphy_cfg = rk3568_combphy_cfg, 765 .force_det_out = true, 766 }; 767 #endif 768 769 #ifdef CONFIG_ROCKCHIP_RK3588 770 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 771 { 772 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 773 u32 val; 774 775 switch (priv->mode) { 776 case PHY_TYPE_PCIE: 777 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 778 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 779 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 780 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 781 break; 782 case PHY_TYPE_USB3: 783 /* Set SSC downward spread spectrum */ 784 val = readl(priv->mmio + (0x1f << 2)); 785 val &= ~GENMASK(5, 4); 786 val |= 0x01 << 4; 787 writel(val, priv->mmio + 0x7c); 788 789 /* Enable adaptive CTLE for USB3.0 Rx */ 790 val = readl(priv->mmio + (0x0e << 2)); 791 val &= ~GENMASK(0, 0); 792 val |= 0x01; 793 writel(val, priv->mmio + (0x0e << 2)); 794 795 /* Set PLL KVCO fine tuning signals */ 796 val = readl(priv->mmio + (0x20 << 2)); 797 val &= ~(0x7 << 2); 798 val |= 0x2 << 2; 799 writel(val, priv->mmio + (0x20 << 2)); 800 801 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 802 writel(0x4, priv->mmio + (0xb << 2)); 803 804 /* Set PLL input clock divider 1/2 */ 805 val = readl(priv->mmio + (0x5 << 2)); 806 val &= ~(0x3 << 6); 807 val |= 0x1 << 6; 808 writel(val, priv->mmio + (0x5 << 2)); 809 810 /* Set PLL loop divider */ 811 writel(0x32, priv->mmio + (0x11 << 2)); 812 813 /* Set PLL KVCO to min and set PLL charge pump current to max */ 814 writel(0xf0, priv->mmio + (0xa << 2)); 815 816 /* Set Rx squelch input filler bandwidth */ 817 writel(0x0d, priv->mmio + (0x14 << 2)); 818 819 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 820 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 821 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 822 break; 823 case PHY_TYPE_SATA: 824 /* Enable adaptive CTLE for SATA Rx */ 825 val = readl(priv->mmio + (0x0e << 2)); 826 val &= ~GENMASK(0, 0); 827 val |= 0x01; 828 writel(val, priv->mmio + (0x0e << 2)); 829 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 830 writel(0x8F, priv->mmio + (0x06 << 2)); 831 832 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 833 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 834 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 835 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 836 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 837 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 838 break; 839 case PHY_TYPE_SGMII: 840 case PHY_TYPE_QSGMII: 841 default: 842 dev_err(priv->dev, "incompatible PHY type\n"); 843 return -EINVAL; 844 } 845 846 /* 100MHz refclock signal is good */ 847 clk_set_rate(&priv->ref_clk, 100000000); 848 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 849 if (priv->mode == PHY_TYPE_PCIE) { 850 /* PLL KVCO tuning fine */ 851 val = readl(priv->mmio + (0x20 << 2)); 852 val &= ~GENMASK(4, 2); 853 val |= 0x4 << 2; 854 writel(val, priv->mmio + (0x20 << 2)); 855 856 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 857 val = 0x4c; 858 writel(val, priv->mmio + (0x1b << 2)); 859 860 /* Set up su_trim: T3 */ 861 val = 0xb0; 862 writel(val, priv->mmio + (0xa << 2)); 863 val = 0x47; 864 writel(val, priv->mmio + (0xb << 2)); 865 val = 0x57; 866 writel(val, priv->mmio + (0xd << 2)); 867 } 868 869 return 0; 870 } 871 872 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 873 /* pipe-phy-grf */ 874 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 875 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 876 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 877 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 878 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 879 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 880 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 881 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 882 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 883 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 884 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 885 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 886 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 887 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 888 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 889 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 890 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 891 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 892 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 893 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 894 /* pipe-grf */ 895 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 896 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 897 }; 898 899 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 900 .grfcfg = &rk3588_combphy_grfcfgs, 901 .combphy_cfg = rk3588_combphy_cfg, 902 .force_det_out = true, 903 }; 904 #endif 905 906 907 #ifdef CONFIG_ROCKCHIP_RK3576 908 static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) 909 { 910 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 911 u32 val; 912 913 switch (priv->mode) { 914 case PHY_TYPE_PCIE: 915 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 916 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 917 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 918 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 919 break; 920 case PHY_TYPE_USB3: 921 /* Set SSC downward spread spectrum */ 922 val = readl(priv->mmio + (0x1f << 2)); 923 val &= ~GENMASK(5, 4); 924 val |= 0x01 << 4; 925 writel(val, priv->mmio + 0x7c); 926 927 /* Enable adaptive CTLE for USB3.0 Rx */ 928 val = readl(priv->mmio + (0x0e << 2)); 929 val &= ~GENMASK(0, 0); 930 val |= 0x01; 931 writel(val, priv->mmio + (0x0e << 2)); 932 933 /* Set PLL KVCO fine tuning signals */ 934 val = readl(priv->mmio + (0x20 << 2)); 935 val &= ~(0x7 << 2); 936 val |= 0x2 << 2; 937 writel(val, priv->mmio + (0x20 << 2)); 938 939 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 940 writel(0x4, priv->mmio + (0xb << 2)); 941 942 /* Set PLL input clock divider 1/2 */ 943 val = readl(priv->mmio + (0x5 << 2)); 944 val &= ~(0x3 << 6); 945 val |= 0x1 << 6; 946 writel(val, priv->mmio + (0x5 << 2)); 947 948 /* Set PLL loop divider */ 949 writel(0x32, priv->mmio + (0x11 << 2)); 950 951 /* Set PLL KVCO to min and set PLL charge pump current to max */ 952 writel(0xf0, priv->mmio + (0xa << 2)); 953 954 /* Set Rx squelch input filler bandwidth */ 955 writel(0x0d, priv->mmio + (0x14 << 2)); 956 957 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 958 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 959 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 960 break; 961 case PHY_TYPE_SATA: 962 /* Enable adaptive CTLE for SATA Rx */ 963 val = readl(priv->mmio + (0x0e << 2)); 964 val &= ~GENMASK(0, 0); 965 val |= 0x01; 966 writel(val, priv->mmio + (0x0e << 2)); 967 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 968 writel(0x8F, priv->mmio + (0x06 << 2)); 969 970 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 971 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 972 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 973 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 974 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 975 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 976 break; 977 case PHY_TYPE_SGMII: 978 case PHY_TYPE_QSGMII: 979 default: 980 dev_err(priv->dev, "incompatible PHY type\n"); 981 return -EINVAL; 982 } 983 984 /* 100MHz refclock signal is good */ 985 clk_set_rate(&priv->ref_clk, 100000000); 986 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 987 if (priv->mode == PHY_TYPE_PCIE) { 988 /* gate_tx_pck_sel length select work for L1SS */ 989 writel(0xc0, priv->mmio + 0x74); 990 991 /* PLL KVCO tuning fine */ 992 val = readl(priv->mmio + (0x20 << 2)); 993 val &= ~(0x7 << 2); 994 val |= 0x2 << 2; 995 writel(val, priv->mmio + (0x20 << 2)); 996 997 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 998 writel(0x4c, priv->mmio + (0x1b << 2)); 999 1000 /* Set up su_trim: T3_P1 650mv */ 1001 writel(0x90, priv->mmio + (0xa << 2)); 1002 writel(0x43, priv->mmio + (0xb << 2)); 1003 writel(0x88, priv->mmio + (0xc << 2)); 1004 writel(0x56, priv->mmio + (0xd << 2)); 1005 } 1006 1007 return 0; 1008 } 1009 1010 static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { 1011 /* pipe-phy-grf */ 1012 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 1013 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 1014 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 1015 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 1016 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 1017 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, 1018 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 1019 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 1020 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 1021 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 1022 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 1023 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 1024 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 1025 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 1026 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 1027 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 1028 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 1029 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 1030 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 1031 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 1032 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 1033 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 1034 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 1035 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 1036 /* php-grf */ 1037 .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, 1038 .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, 1039 .u3otg1_port_en = { 0x0038, 15, 0, 0x0181, 0x1100 }, 1040 }; 1041 1042 static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { 1043 .grfcfg = &rk3576_combphy_grfcfgs, 1044 .combphy_cfg = rk3576_combphy_cfg, 1045 }; 1046 #endif 1047 1048 static const struct udevice_id rockchip_combphy_ids[] = { 1049 #ifdef CONFIG_ROCKCHIP_RK3528 1050 { 1051 .compatible = "rockchip,rk3528-naneng-combphy", 1052 .data = (ulong)&rk3528_combphy_cfgs 1053 }, 1054 #endif 1055 #ifdef CONFIG_ROCKCHIP_RK3562 1056 { 1057 .compatible = "rockchip,rk3562-naneng-combphy", 1058 .data = (ulong)&rk3562_combphy_cfgs 1059 }, 1060 #endif 1061 #ifdef CONFIG_ROCKCHIP_RK3568 1062 { 1063 .compatible = "rockchip,rk3568-naneng-combphy", 1064 .data = (ulong)&rk3568_combphy_cfgs 1065 }, 1066 #endif 1067 #ifdef CONFIG_ROCKCHIP_RK3588 1068 { 1069 .compatible = "rockchip,rk3588-naneng-combphy", 1070 .data = (ulong)&rk3588_combphy_cfgs 1071 }, 1072 #endif 1073 #ifdef CONFIG_ROCKCHIP_RK3576 1074 { 1075 .compatible = "rockchip,rk3576-naneng-combphy", 1076 .data = (ulong)&rk3576_combphy_cfgs 1077 }, 1078 #endif 1079 { } 1080 }; 1081 1082 U_BOOT_DRIVER(rockchip_naneng_combphy) = { 1083 .name = "naneng-combphy", 1084 .id = UCLASS_PHY, 1085 .of_match = rockchip_combphy_ids, 1086 .ops = &rochchip_combphy_ops, 1087 .probe = rockchip_combphy_probe, 1088 .priv_auto_alloc_size = sizeof(struct rockchip_combphy_priv), 1089 }; 1090