1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dt-bindings/phy/phy.h> 13 #include <generic-phy.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <regmap.h> 18 #include <reset-uclass.h> 19 20 #define BIT_WRITEABLE_SHIFT 16 21 22 struct rockchip_combphy_priv; 23 24 struct combphy_reg { 25 u16 offset; 26 u16 bitend; 27 u16 bitstart; 28 u16 disable; 29 u16 enable; 30 }; 31 32 struct rockchip_combphy_grfcfg { 33 struct combphy_reg pcie_mode_set; 34 struct combphy_reg usb_mode_set; 35 struct combphy_reg sgmii_mode_set; 36 struct combphy_reg qsgmii_mode_set; 37 struct combphy_reg pipe_rxterm_set; 38 struct combphy_reg pipe_txelec_set; 39 struct combphy_reg pipe_txcomp_set; 40 struct combphy_reg pipe_clk_25m; 41 struct combphy_reg pipe_clk_100m; 42 struct combphy_reg pipe_phymode_sel; 43 struct combphy_reg pipe_rate_sel; 44 struct combphy_reg pipe_rxterm_sel; 45 struct combphy_reg pipe_txelec_sel; 46 struct combphy_reg pipe_txcomp_sel; 47 struct combphy_reg pipe_clk_ext; 48 struct combphy_reg pipe_sel_usb; 49 struct combphy_reg pipe_sel_qsgmii; 50 struct combphy_reg pipe_phy_status; 51 struct combphy_reg con0_for_pcie; 52 struct combphy_reg con1_for_pcie; 53 struct combphy_reg con2_for_pcie; 54 struct combphy_reg con3_for_pcie; 55 struct combphy_reg con0_for_sata; 56 struct combphy_reg con1_for_sata; 57 struct combphy_reg con2_for_sata; 58 struct combphy_reg con3_for_sata; 59 struct combphy_reg pipe_con0_for_sata; 60 struct combphy_reg pipe_con1_for_sata; 61 struct combphy_reg pipe_sgmii_mac_sel; 62 struct combphy_reg pipe_xpcs_phy_ready; 63 struct combphy_reg u3otg0_port_en; 64 struct combphy_reg u3otg1_port_en; 65 }; 66 67 struct rockchip_combphy_cfg { 68 const struct rockchip_combphy_grfcfg *grfcfg; 69 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 70 }; 71 72 struct rockchip_combphy_priv { 73 u32 mode; 74 void __iomem *mmio; 75 struct udevice *dev; 76 struct regmap *pipe_grf; 77 struct regmap *phy_grf; 78 struct phy *phy; 79 struct reset_ctl phy_rst; 80 struct clk ref_clk; 81 const struct rockchip_combphy_cfg *cfg; 82 }; 83 84 static int param_write(struct regmap *base, 85 const struct combphy_reg *reg, bool en) 86 { 87 u32 val, mask, tmp; 88 89 tmp = en ? reg->enable : reg->disable; 90 mask = GENMASK(reg->bitend, reg->bitstart); 91 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 92 93 return regmap_write(base, reg->offset, val); 94 } 95 96 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) 97 { 98 int ret = 0; 99 100 if (priv->cfg->combphy_cfg) { 101 ret = priv->cfg->combphy_cfg(priv); 102 if (ret) { 103 dev_err(priv->dev, "failed to init phy for pcie\n"); 104 return ret; 105 } 106 } 107 108 return ret; 109 } 110 111 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) 112 { 113 int ret = 0; 114 115 if (priv->cfg->combphy_cfg) { 116 ret = priv->cfg->combphy_cfg(priv); 117 if (ret) { 118 dev_err(priv->dev, "failed to init phy for usb3\n"); 119 return ret; 120 } 121 } 122 123 return ret; 124 } 125 126 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) 127 { 128 int ret = 0; 129 130 if (priv->cfg->combphy_cfg) { 131 ret = priv->cfg->combphy_cfg(priv); 132 if (ret) { 133 dev_err(priv->dev, "failed to init phy for sata\n"); 134 return ret; 135 } 136 } 137 138 return ret; 139 } 140 141 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) 142 { 143 int ret = 0; 144 145 if (priv->cfg->combphy_cfg) { 146 ret = priv->cfg->combphy_cfg(priv); 147 if (ret) { 148 dev_err(priv->dev, "failed to init phy for sgmii\n"); 149 return ret; 150 } 151 } 152 153 return ret; 154 } 155 156 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) 157 { 158 switch (priv->mode) { 159 case PHY_TYPE_PCIE: 160 rockchip_combphy_pcie_init(priv); 161 break; 162 case PHY_TYPE_USB3: 163 rockchip_combphy_usb3_init(priv); 164 break; 165 case PHY_TYPE_SATA: 166 rockchip_combphy_sata_init(priv); 167 break; 168 case PHY_TYPE_SGMII: 169 case PHY_TYPE_QSGMII: 170 return rockchip_combphy_sgmii_init(priv); 171 default: 172 dev_err(priv->dev, "incompatible PHY type\n"); 173 return -EINVAL; 174 } 175 176 return 0; 177 } 178 179 static int rockchip_combphy_init(struct phy *phy) 180 { 181 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 182 int ret; 183 184 ret = clk_enable(&priv->ref_clk); 185 if (ret < 0 && ret != -ENOSYS) 186 return ret; 187 188 ret = rockchip_combphy_set_mode(priv); 189 if (ret) 190 goto err_clk; 191 192 reset_deassert(&priv->phy_rst); 193 194 return 0; 195 196 err_clk: 197 clk_disable(&priv->ref_clk); 198 199 return ret; 200 } 201 202 static int rockchip_combphy_exit(struct phy *phy) 203 { 204 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 205 206 clk_disable(&priv->ref_clk); 207 reset_assert(&priv->phy_rst); 208 209 return 0; 210 } 211 212 static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) 213 { 214 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 215 216 if (args->args_count != 1) { 217 pr_err("invalid number of arguments\n"); 218 return -EINVAL; 219 } 220 221 priv->mode = args->args[0]; 222 223 return 0; 224 } 225 226 static const struct phy_ops rochchip_combphy_ops = { 227 .init = rockchip_combphy_init, 228 .exit = rockchip_combphy_exit, 229 .of_xlate = rockchip_combphy_xlate, 230 }; 231 232 static int rockchip_combphy_parse_dt(struct udevice *dev, 233 struct rockchip_combphy_priv *priv) 234 { 235 struct udevice *syscon; 236 int ret; 237 u32 vals[4]; 238 239 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); 240 if (ret) { 241 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap ret= %d\n", ret); 242 return ret; 243 } 244 priv->pipe_grf = syscon_get_regmap(syscon); 245 246 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); 247 if (ret) { 248 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 249 return ret; 250 } 251 priv->phy_grf = syscon_get_regmap(syscon); 252 253 ret = clk_get_by_index(dev, 0, &priv->ref_clk); 254 if (ret) { 255 dev_err(dev, "failed to find ref clock\n"); 256 return PTR_ERR(&priv->ref_clk); 257 } 258 259 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); 260 if (ret) { 261 dev_err(dev, "no phy reset control specified\n"); 262 return ret; 263 } 264 265 if (!dev_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", 266 vals, ARRAY_SIZE(vals))) 267 regmap_write(priv->pipe_grf, vals[0], 268 (GENMASK(vals[2], vals[1]) << 16) | vals[3]); 269 270 return 0; 271 } 272 273 static int rockchip_combphy_probe(struct udevice *udev) 274 { 275 struct rockchip_combphy_priv *priv = dev_get_priv(udev); 276 const struct rockchip_combphy_cfg *phy_cfg; 277 int ret; 278 279 priv->mmio = (void __iomem *)dev_read_addr(udev); 280 if (IS_ERR(priv->mmio)) 281 return PTR_ERR(priv->mmio); 282 283 phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); 284 if (!phy_cfg) { 285 dev_err(udev, "No OF match data provided\n"); 286 return -EINVAL; 287 } 288 289 priv->dev = udev; 290 priv->mode = PHY_TYPE_SATA; 291 priv->cfg = phy_cfg; 292 293 ret = rockchip_combphy_parse_dt(udev, priv); 294 if (ret) 295 return ret; 296 297 ret = rockchip_combphy_set_mode(priv); 298 299 return ret; 300 } 301 302 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 303 { 304 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 305 u32 val; 306 307 switch (priv->mode) { 308 case PHY_TYPE_PCIE: 309 /* Set SSC downward spread spectrum */ 310 val = readl(priv->mmio + (0x1f << 2)); 311 val &= ~GENMASK(5, 4); 312 val |= 0x01 << 4; 313 writel(val, priv->mmio + 0x7c); 314 315 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 316 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 317 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 318 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 319 break; 320 case PHY_TYPE_USB3: 321 /* Set SSC downward spread spectrum */ 322 val = readl(priv->mmio + (0x1f << 2)); 323 val &= ~GENMASK(5, 4); 324 val |= 0x01 << 4; 325 writel(val, priv->mmio + 0x7c); 326 327 /* Enable adaptive CTLE for USB3.0 Rx */ 328 val = readl(priv->mmio + (0x0e << 2)); 329 val &= ~GENMASK(0, 0); 330 val |= 0x01; 331 writel(val, priv->mmio + (0x0e << 2)); 332 333 /* Set PLL KVCO fine tuning signals */ 334 val = readl(priv->mmio + (0x20 << 2)); 335 val &= ~(0x7 << 2); 336 val |= 0x2 << 2; 337 writel(val, priv->mmio + (0x20 << 2)); 338 339 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 340 writel(0x4, priv->mmio + (0xb << 2)); 341 342 /* Set PLL input clock divider 1/2 */ 343 val = readl(priv->mmio + (0x5 << 2)); 344 val &= ~(0x3 << 6); 345 val |= 0x1 << 6; 346 writel(val, priv->mmio + (0x5 << 2)); 347 348 /* Set PLL loop divider */ 349 writel(0x32, priv->mmio + (0x11 << 2)); 350 351 /* Set PLL KVCO to min and set PLL charge pump current to max */ 352 writel(0xf0, priv->mmio + (0xa << 2)); 353 354 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 355 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 356 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 357 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 358 break; 359 case PHY_TYPE_SATA: 360 writel(0x41, priv->mmio + 0x38); 361 writel(0x8F, priv->mmio + 0x18); 362 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 363 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 364 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 365 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 366 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 367 break; 368 case PHY_TYPE_SGMII: 369 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 370 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 371 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 372 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 373 break; 374 case PHY_TYPE_QSGMII: 375 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 376 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 377 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 378 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 379 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 380 break; 381 default: 382 pr_err("%s, phy-type %d\n", __func__, priv->mode); 383 return -EINVAL; 384 } 385 386 /* The default ref clock is 25Mhz */ 387 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 388 389 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 390 val = readl(priv->mmio + (0x7 << 2)); 391 val |= BIT(4); 392 writel(val, priv->mmio + (0x7 << 2)); 393 } 394 395 return 0; 396 } 397 398 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 399 /* pipe-phy-grf */ 400 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 401 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 402 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 403 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 404 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 405 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 406 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 407 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 408 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 409 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 410 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 411 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 412 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 413 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 414 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 415 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 416 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 417 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 418 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 419 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 420 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 421 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 422 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 423 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 424 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 425 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 426 /* pipe-grf */ 427 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 428 .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, 429 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 430 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 431 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 432 }; 433 434 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 435 .grfcfg = &rk3568_combphy_grfcfgs, 436 .combphy_cfg = rk3568_combphy_cfg, 437 }; 438 439 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 440 { 441 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 442 u32 val; 443 444 switch (priv->mode) { 445 case PHY_TYPE_PCIE: 446 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 447 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 448 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 449 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 450 break; 451 case PHY_TYPE_USB3: 452 /* Set SSC downward spread spectrum */ 453 val = readl(priv->mmio + (0x1f << 2)); 454 val &= ~GENMASK(5, 4); 455 val |= 0x01 << 4; 456 writel(val, priv->mmio + 0x7c); 457 458 /* Enable adaptive CTLE for USB3.0 Rx */ 459 val = readl(priv->mmio + (0x0e << 2)); 460 val &= ~GENMASK(0, 0); 461 val |= 0x01; 462 writel(val, priv->mmio + (0x0e << 2)); 463 464 /* Set PLL KVCO fine tuning signals */ 465 val = readl(priv->mmio + (0x20 << 2)); 466 val &= ~(0x7 << 2); 467 val |= 0x2 << 2; 468 writel(val, priv->mmio + (0x20 << 2)); 469 470 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 471 writel(0x4, priv->mmio + (0xb << 2)); 472 473 /* Set PLL input clock divider 1/2 */ 474 val = readl(priv->mmio + (0x5 << 2)); 475 val &= ~(0x3 << 6); 476 val |= 0x1 << 6; 477 writel(val, priv->mmio + (0x5 << 2)); 478 479 /* Set PLL loop divider */ 480 writel(0x32, priv->mmio + (0x11 << 2)); 481 482 /* Set PLL KVCO to min and set PLL charge pump current to max */ 483 writel(0xf0, priv->mmio + (0xa << 2)); 484 485 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 486 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 487 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 488 break; 489 case PHY_TYPE_SATA: 490 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 491 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 492 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 493 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 494 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 495 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 496 break; 497 case PHY_TYPE_SGMII: 498 case PHY_TYPE_QSGMII: 499 default: 500 dev_err(priv->dev, "incompatible PHY type\n"); 501 return -EINVAL; 502 } 503 504 /* 100MHz refclock signal is good */ 505 clk_set_rate(&priv->ref_clk, 100000000); 506 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 507 if (priv->mode == PHY_TYPE_PCIE) { 508 /* PLL KVCO tuning fine */ 509 val = readl(priv->mmio + (0x20 << 2)); 510 val &= ~GENMASK(4, 2); 511 val |= 0x4 << 2; 512 writel(val, priv->mmio + (0x20 << 2)); 513 514 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 515 val = 0x4c; 516 writel(val, priv->mmio + (0x1b << 2)); 517 518 /* Set up su_trim: T3 */ 519 val = 0xb0; 520 writel(val, priv->mmio + (0xa << 2)); 521 val = 0x47; 522 writel(val, priv->mmio + (0xb << 2)); 523 val = 0x57; 524 writel(val, priv->mmio + (0xd << 2)); 525 } 526 527 return 0; 528 } 529 530 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 531 /* pipe-phy-grf */ 532 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 533 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 534 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 535 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 536 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 537 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 538 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 539 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 540 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 541 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 542 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 543 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 544 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 545 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 546 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 547 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 548 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 549 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 550 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 551 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 552 /* pipe-grf */ 553 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 554 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 555 }; 556 557 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 558 .grfcfg = &rk3588_combphy_grfcfgs, 559 .combphy_cfg = rk3588_combphy_cfg, 560 }; 561 562 static const struct udevice_id rockchip_combphy_ids[] = { 563 { 564 .compatible = "rockchip,rk3568-naneng-combphy", 565 .data = (ulong)&rk3568_combphy_cfgs 566 }, 567 { 568 .compatible = "rockchip,rk3588-naneng-combphy", 569 .data = (ulong)&rk3588_combphy_cfgs 570 }, 571 { } 572 }; 573 574 U_BOOT_DRIVER(rockchip_naneng_combphy) = { 575 .name = "naneng-combphy", 576 .id = UCLASS_PHY, 577 .of_match = rockchip_combphy_ids, 578 .ops = &rochchip_combphy_ops, 579 .probe = rockchip_combphy_probe, 580 .priv_auto_alloc_size = sizeof(struct rockchip_combphy_priv), 581 }; 582