1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dt-bindings/phy/phy.h> 13 #include <generic-phy.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <regmap.h> 18 #include <reset-uclass.h> 19 #include <linux/iopoll.h> 20 21 #define BIT_WRITEABLE_SHIFT 16 22 23 struct rockchip_combphy_priv; 24 25 struct combphy_reg { 26 u32 offset; 27 u16 bitend; 28 u16 bitstart; 29 u16 disable; 30 u16 enable; 31 }; 32 33 struct rockchip_combphy_grfcfg { 34 struct combphy_reg pcie_mode_set; 35 struct combphy_reg usb_mode_set; 36 struct combphy_reg sgmii_mode_set; 37 struct combphy_reg qsgmii_mode_set; 38 struct combphy_reg pipe_rxterm_set; 39 struct combphy_reg pipe_txelec_set; 40 struct combphy_reg pipe_txcomp_set; 41 struct combphy_reg pipe_clk_24m; 42 struct combphy_reg pipe_clk_25m; 43 struct combphy_reg pipe_clk_100m; 44 struct combphy_reg pipe_phymode_sel; 45 struct combphy_reg pipe_rate_sel; 46 struct combphy_reg pipe_rxterm_sel; 47 struct combphy_reg pipe_txelec_sel; 48 struct combphy_reg pipe_txcomp_sel; 49 struct combphy_reg pipe_clk_ext; 50 struct combphy_reg pipe_sel_usb; 51 struct combphy_reg pipe_sel_qsgmii; 52 struct combphy_reg pipe_phy_status; 53 struct combphy_reg con0_for_pcie; 54 struct combphy_reg con1_for_pcie; 55 struct combphy_reg con2_for_pcie; 56 struct combphy_reg con3_for_pcie; 57 struct combphy_reg con0_for_sata; 58 struct combphy_reg con1_for_sata; 59 struct combphy_reg con2_for_sata; 60 struct combphy_reg con3_for_sata; 61 struct combphy_reg pipe_con0_for_sata; 62 struct combphy_reg pipe_con1_for_sata; 63 struct combphy_reg pipe_sgmii_mac_sel; 64 struct combphy_reg pipe_xpcs_phy_ready; 65 struct combphy_reg u3otg0_port_en; 66 struct combphy_reg u3otg1_port_en; 67 struct combphy_reg u3otg0_pipe_clk_sel; 68 struct combphy_reg pipe_phy_grf_reset; 69 }; 70 71 struct rockchip_combphy_cfg { 72 const struct rockchip_combphy_grfcfg *grfcfg; 73 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 74 }; 75 76 struct rockchip_combphy_priv { 77 u32 mode; 78 void __iomem *mmio; 79 struct udevice *dev; 80 struct regmap *pipe_grf; 81 struct regmap *phy_grf; 82 struct phy *phy; 83 struct reset_ctl phy_rst; 84 struct clk ref_clk; 85 const struct rockchip_combphy_cfg *cfg; 86 }; 87 88 static int param_write(struct regmap *base, 89 const struct combphy_reg *reg, bool en) 90 { 91 u32 val, mask, tmp; 92 93 tmp = en ? reg->enable : reg->disable; 94 mask = GENMASK(reg->bitend, reg->bitstart); 95 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 96 97 return regmap_write(base, reg->offset, val); 98 } 99 100 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) 101 { 102 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 103 u32 mask, val; 104 105 mask = GENMASK(cfg->pipe_phy_status.bitend, 106 cfg->pipe_phy_status.bitstart); 107 108 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); 109 val = (val & mask) >> cfg->pipe_phy_status.bitstart; 110 111 return val; 112 } 113 114 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) 115 { 116 int ret = 0; 117 118 if (priv->cfg->combphy_cfg) { 119 ret = priv->cfg->combphy_cfg(priv); 120 if (ret) { 121 dev_err(priv->dev, "failed to init phy for pcie\n"); 122 return ret; 123 } 124 } 125 126 return ret; 127 } 128 129 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) 130 { 131 int ret = 0; 132 133 if (priv->cfg->combphy_cfg) { 134 ret = priv->cfg->combphy_cfg(priv); 135 if (ret) { 136 dev_err(priv->dev, "failed to init phy for usb3\n"); 137 return ret; 138 } 139 } 140 141 return ret; 142 } 143 144 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) 145 { 146 int ret = 0; 147 148 if (priv->cfg->combphy_cfg) { 149 ret = priv->cfg->combphy_cfg(priv); 150 if (ret) { 151 dev_err(priv->dev, "failed to init phy for sata\n"); 152 return ret; 153 } 154 } 155 156 return ret; 157 } 158 159 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) 160 { 161 int ret = 0; 162 163 if (priv->cfg->combphy_cfg) { 164 ret = priv->cfg->combphy_cfg(priv); 165 if (ret) { 166 dev_err(priv->dev, "failed to init phy for sgmii\n"); 167 return ret; 168 } 169 } 170 171 return ret; 172 } 173 174 int rockchip_combphy_usb3_uboot_init(void) 175 { 176 struct udevice *udev; 177 struct rockchip_combphy_priv *priv; 178 const struct rockchip_combphy_grfcfg *cfg; 179 u32 val; 180 int ret; 181 182 ret = uclass_get_device_by_driver(UCLASS_PHY, 183 DM_GET_DRIVER(rockchip_naneng_combphy), 184 &udev); 185 if (ret) { 186 pr_err("%s: get usb3-phy node failed: %d\n", __func__, ret); 187 return ret; 188 } 189 190 priv = dev_get_priv(udev); 191 priv->mode = PHY_TYPE_USB3; 192 cfg = priv->cfg->grfcfg; 193 194 rockchip_combphy_usb3_init(priv); 195 reset_deassert(&priv->phy_rst); 196 197 if (cfg->pipe_phy_grf_reset.enable) 198 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 199 200 if (priv->mode == PHY_TYPE_USB3) { 201 ret = readx_poll_timeout(rockchip_combphy_is_ready, 202 priv, val, 203 val == cfg->pipe_phy_status.enable, 204 1000); 205 if (ret) { 206 dev_err(priv->dev, "wait phy status ready timeout\n"); 207 param_write(priv->phy_grf, &cfg->usb_mode_set, false); 208 if (cfg->u3otg0_pipe_clk_sel.disable) 209 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, false); 210 return ret; 211 } 212 } 213 214 /* Select clk_usb3otg0_pipe for source clk */ 215 if (cfg->u3otg0_pipe_clk_sel.disable) 216 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, true); 217 218 return ret; 219 } 220 221 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) 222 { 223 switch (priv->mode) { 224 case PHY_TYPE_PCIE: 225 rockchip_combphy_pcie_init(priv); 226 break; 227 case PHY_TYPE_USB3: 228 rockchip_combphy_usb3_init(priv); 229 break; 230 case PHY_TYPE_SATA: 231 rockchip_combphy_sata_init(priv); 232 break; 233 case PHY_TYPE_SGMII: 234 case PHY_TYPE_QSGMII: 235 return rockchip_combphy_sgmii_init(priv); 236 default: 237 dev_err(priv->dev, "incompatible PHY type\n"); 238 return -EINVAL; 239 } 240 241 return 0; 242 } 243 244 static int rockchip_combphy_init(struct phy *phy) 245 { 246 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 247 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 248 int ret; 249 250 ret = clk_enable(&priv->ref_clk); 251 if (ret < 0 && ret != -ENOSYS) 252 return ret; 253 254 ret = rockchip_combphy_set_mode(priv); 255 if (ret) 256 goto err_clk; 257 258 reset_deassert(&priv->phy_rst); 259 260 if (cfg->pipe_phy_grf_reset.enable) 261 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 262 263 return 0; 264 265 err_clk: 266 clk_disable(&priv->ref_clk); 267 268 return ret; 269 } 270 271 static int rockchip_combphy_exit(struct phy *phy) 272 { 273 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 274 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 275 276 if (cfg->pipe_phy_grf_reset.enable) 277 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); 278 279 reset_assert(&priv->phy_rst); 280 clk_disable(&priv->ref_clk); 281 282 return 0; 283 } 284 285 static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) 286 { 287 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 288 289 if (args->args_count != 1) { 290 pr_err("invalid number of arguments\n"); 291 return -EINVAL; 292 } 293 294 priv->mode = args->args[0]; 295 296 return 0; 297 } 298 299 static const struct phy_ops rochchip_combphy_ops = { 300 .init = rockchip_combphy_init, 301 .exit = rockchip_combphy_exit, 302 .of_xlate = rockchip_combphy_xlate, 303 }; 304 305 static int rockchip_combphy_parse_dt(struct udevice *dev, 306 struct rockchip_combphy_priv *priv) 307 { 308 struct udevice *syscon; 309 int ret; 310 u32 vals[4]; 311 312 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); 313 if (ret) { 314 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap ret= %d\n", ret); 315 return ret; 316 } 317 priv->pipe_grf = syscon_get_regmap(syscon); 318 319 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); 320 if (ret) { 321 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 322 return ret; 323 } 324 priv->phy_grf = syscon_get_regmap(syscon); 325 326 ret = clk_get_by_index(dev, 0, &priv->ref_clk); 327 if (ret) { 328 dev_err(dev, "failed to find ref clock\n"); 329 return PTR_ERR(&priv->ref_clk); 330 } 331 332 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); 333 if (ret) { 334 dev_err(dev, "no phy reset control specified\n"); 335 return ret; 336 } 337 338 if (!dev_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", 339 vals, ARRAY_SIZE(vals))) 340 regmap_write(priv->pipe_grf, vals[0], 341 (GENMASK(vals[2], vals[1]) << 16) | vals[3]); 342 343 return 0; 344 } 345 346 static int rockchip_combphy_probe(struct udevice *udev) 347 { 348 struct rockchip_combphy_priv *priv = dev_get_priv(udev); 349 const struct rockchip_combphy_cfg *phy_cfg; 350 351 priv->mmio = (void __iomem *)dev_read_addr(udev); 352 if (IS_ERR(priv->mmio)) 353 return PTR_ERR(priv->mmio); 354 355 phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); 356 if (!phy_cfg) { 357 dev_err(udev, "No OF match data provided\n"); 358 return -EINVAL; 359 } 360 361 priv->dev = udev; 362 priv->mode = PHY_TYPE_SATA; 363 priv->cfg = phy_cfg; 364 365 return rockchip_combphy_parse_dt(udev, priv); 366 } 367 368 #ifdef CONFIG_ROCKCHIP_RK3528 369 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) 370 { 371 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 372 u32 val; 373 374 switch (priv->mode) { 375 case PHY_TYPE_PCIE: 376 /* Set SSC downward spread spectrum */ 377 val = readl(priv->mmio + 0x18); 378 val &= ~GENMASK(5, 4); 379 val |= 0x01 << 4; 380 writel(val, priv->mmio + 0x18); 381 382 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 383 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 384 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 385 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 386 break; 387 case PHY_TYPE_USB3: 388 /* Set SSC downward spread spectrum */ 389 val = readl(priv->mmio + 0x18); 390 val &= ~GENMASK(5, 4); 391 val |= 0x01 << 4; 392 writel(val, priv->mmio + 0x18); 393 394 /* Enable adaptive CTLE for USB3.0 Rx */ 395 val = readl(priv->mmio + 0x200); 396 val &= ~GENMASK(17, 17); 397 val |= 0x01; 398 writel(val, priv->mmio + 0x200); 399 400 /* Set Rx squelch input filler bandwidth */ 401 val = readl(priv->mmio + 0x20c); 402 val &= ~GENMASK(2, 0); 403 val |= 0x06; 404 writel(val, priv->mmio + 0x20c); 405 406 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 407 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 408 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 409 break; 410 default: 411 dev_err(priv->dev, "incompatible PHY type\n"); 412 return -EINVAL; 413 } 414 415 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 416 if (priv->mode == PHY_TYPE_PCIE) { 417 /* PLL KVCO tuning fine */ 418 val = readl(priv->mmio + 0x18); 419 val &= ~(0x7 << 10); 420 val |= 0x2 << 10; 421 writel(val, priv->mmio + 0x18); 422 423 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ 424 val = readl(priv->mmio + 0x108); 425 val &= ~(0x7f7); 426 val |= 0x4f0; 427 writel(val, priv->mmio + 0x108); 428 } 429 430 return 0; 431 } 432 433 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { 434 /* pipe-phy-grf */ 435 .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 }, 436 .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 }, 437 .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 }, 438 .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 }, 439 .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 }, 440 .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 }, 441 .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 }, 442 .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 }, 443 .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 }, 444 .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 }, 445 .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 }, 446 .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 }, 447 .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 }, 448 .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 }, 449 .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 }, 450 .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 }, 451 /* pipe-grf */ 452 .u3otg0_pipe_clk_sel = { 0x40044, 7, 7, 0x01, 0x00 }, 453 .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 }, 454 }; 455 456 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { 457 .grfcfg = &rk3528_combphy_grfcfgs, 458 .combphy_cfg = rk3528_combphy_cfg, 459 }; 460 #endif 461 462 #ifdef CONFIG_ROCKCHIP_RK3562 463 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) 464 { 465 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 466 u32 val; 467 468 switch (priv->mode) { 469 case PHY_TYPE_PCIE: 470 /* Set SSC downward spread spectrum */ 471 val = readl(priv->mmio + (0x1f << 2)); 472 val &= ~GENMASK(5, 4); 473 val |= 0x01 << 4; 474 writel(val, priv->mmio + 0x7c); 475 476 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 477 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 478 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 479 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 480 break; 481 case PHY_TYPE_USB3: 482 /* Set SSC downward spread spectrum */ 483 val = readl(priv->mmio + (0x1f << 2)); 484 val &= ~GENMASK(5, 4); 485 val |= 0x01 << 4; 486 writel(val, priv->mmio + 0x7c); 487 488 /* Enable adaptive CTLE for USB3.0 Rx */ 489 val = readl(priv->mmio + (0x0e << 2)); 490 val &= ~GENMASK(0, 0); 491 val |= 0x01; 492 writel(val, priv->mmio + (0x0e << 2)); 493 494 /* Set PLL KVCO fine tuning signals */ 495 val = readl(priv->mmio + (0x20 << 2)); 496 val &= ~(0x7 << 2); 497 val |= 0x2 << 2; 498 writel(val, priv->mmio + (0x20 << 2)); 499 500 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 501 writel(0x4, priv->mmio + (0xb << 2)); 502 503 /* Set PLL input clock divider 1/2 */ 504 val = readl(priv->mmio + (0x5 << 2)); 505 val &= ~(0x3 << 6); 506 val |= 0x1 << 6; 507 writel(val, priv->mmio + (0x5 << 2)); 508 509 /* Set PLL loop divider */ 510 writel(0x32, priv->mmio + (0x11 << 2)); 511 512 /* Set PLL KVCO to min and set PLL charge pump current to max */ 513 writel(0xf0, priv->mmio + (0xa << 2)); 514 515 /* Set Rx squelch input filler bandwidth */ 516 writel(0x0e, priv->mmio + (0x14 << 2)); 517 518 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 519 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 520 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 521 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 522 break; 523 default: 524 pr_err("%s, phy-type %d\n", __func__, priv->mode); 525 return -EINVAL; 526 } 527 528 clk_set_rate(&priv->ref_clk, 100000000); 529 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 530 531 if (priv->mode == PHY_TYPE_PCIE) { 532 /* PLL KVCO tuning fine */ 533 val = readl(priv->mmio + (0x20 << 2)); 534 val &= ~(0x7 << 2); 535 val |= 0x2 << 2; 536 writel(val, priv->mmio + (0x20 << 2)); 537 538 /* Enable controlling random jitter, aka RMJ */ 539 writel(0x4, priv->mmio + (0xb << 2)); 540 541 val = readl(priv->mmio + (0x5 << 2)); 542 val &= ~(0x3 << 6); 543 val |= 0x1 << 6; 544 writel(val, priv->mmio + (0x5 << 2)); 545 546 writel(0x32, priv->mmio + (0x11 << 2)); 547 writel(0xf0, priv->mmio + (0xa << 2)); 548 } 549 550 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 551 val = readl(priv->mmio + (0x7 << 2)); 552 val |= BIT(4); 553 writel(val, priv->mmio + (0x7 << 2)); 554 } 555 556 return 0; 557 } 558 559 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { 560 /* pipe-phy-grf */ 561 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 562 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 563 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 564 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 565 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 566 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 567 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 568 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 569 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 570 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 571 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 572 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 573 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 574 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 575 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 576 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 577 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 578 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 579 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 580 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 581 /* pipe-grf */ 582 .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 }, 583 }; 584 585 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { 586 .grfcfg = &rk3562_combphy_grfcfgs, 587 .combphy_cfg = rk3562_combphy_cfg, 588 }; 589 #endif 590 591 #ifdef CONFIG_ROCKCHIP_RK3568 592 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 593 { 594 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 595 u32 val; 596 597 switch (priv->mode) { 598 case PHY_TYPE_PCIE: 599 /* Set SSC downward spread spectrum */ 600 val = readl(priv->mmio + (0x1f << 2)); 601 val &= ~GENMASK(5, 4); 602 val |= 0x01 << 4; 603 writel(val, priv->mmio + 0x7c); 604 605 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 606 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 607 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 608 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 609 break; 610 case PHY_TYPE_USB3: 611 /* Set SSC downward spread spectrum */ 612 val = readl(priv->mmio + (0x1f << 2)); 613 val &= ~GENMASK(5, 4); 614 val |= 0x01 << 4; 615 writel(val, priv->mmio + 0x7c); 616 617 /* Enable adaptive CTLE for USB3.0 Rx */ 618 val = readl(priv->mmio + (0x0e << 2)); 619 val &= ~GENMASK(0, 0); 620 val |= 0x01; 621 writel(val, priv->mmio + (0x0e << 2)); 622 623 /* Set PLL KVCO fine tuning signals */ 624 val = readl(priv->mmio + (0x20 << 2)); 625 val &= ~(0x7 << 2); 626 val |= 0x2 << 2; 627 writel(val, priv->mmio + (0x20 << 2)); 628 629 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 630 writel(0x4, priv->mmio + (0xb << 2)); 631 632 /* Set PLL input clock divider 1/2 */ 633 val = readl(priv->mmio + (0x5 << 2)); 634 val &= ~(0x3 << 6); 635 val |= 0x1 << 6; 636 writel(val, priv->mmio + (0x5 << 2)); 637 638 /* Set PLL loop divider */ 639 writel(0x32, priv->mmio + (0x11 << 2)); 640 641 /* Set PLL KVCO to min and set PLL charge pump current to max */ 642 writel(0xf0, priv->mmio + (0xa << 2)); 643 644 /* Set Rx squelch input filler bandwidth */ 645 writel(0x0e, priv->mmio + (0x14 << 2)); 646 647 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 648 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 649 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 650 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 651 break; 652 case PHY_TYPE_SATA: 653 writel(0x41, priv->mmio + 0x38); 654 writel(0x8F, priv->mmio + 0x18); 655 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 656 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 657 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 658 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 659 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 660 break; 661 case PHY_TYPE_SGMII: 662 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 663 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 664 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 665 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 666 break; 667 case PHY_TYPE_QSGMII: 668 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 669 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 670 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 671 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 672 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 673 break; 674 default: 675 pr_err("%s, phy-type %d\n", __func__, priv->mode); 676 return -EINVAL; 677 } 678 679 /* The default ref clock is 25Mhz */ 680 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 681 682 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 683 val = readl(priv->mmio + (0x7 << 2)); 684 val |= BIT(4); 685 writel(val, priv->mmio + (0x7 << 2)); 686 } 687 688 return 0; 689 } 690 691 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 692 /* pipe-phy-grf */ 693 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 694 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 695 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 696 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 697 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 698 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 699 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 700 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 701 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 702 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 703 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 704 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 705 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 706 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 707 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 708 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 709 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 710 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 711 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 712 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 713 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 714 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 715 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 716 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 717 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 718 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 719 /* pipe-grf */ 720 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 721 .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, 722 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 723 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 724 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 725 }; 726 727 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 728 .grfcfg = &rk3568_combphy_grfcfgs, 729 .combphy_cfg = rk3568_combphy_cfg, 730 }; 731 #endif 732 733 #ifdef CONFIG_ROCKCHIP_RK3588 734 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 735 { 736 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 737 u32 val; 738 739 switch (priv->mode) { 740 case PHY_TYPE_PCIE: 741 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 742 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 743 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 744 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 745 break; 746 case PHY_TYPE_USB3: 747 /* Set SSC downward spread spectrum */ 748 val = readl(priv->mmio + (0x1f << 2)); 749 val &= ~GENMASK(5, 4); 750 val |= 0x01 << 4; 751 writel(val, priv->mmio + 0x7c); 752 753 /* Enable adaptive CTLE for USB3.0 Rx */ 754 val = readl(priv->mmio + (0x0e << 2)); 755 val &= ~GENMASK(0, 0); 756 val |= 0x01; 757 writel(val, priv->mmio + (0x0e << 2)); 758 759 /* Set PLL KVCO fine tuning signals */ 760 val = readl(priv->mmio + (0x20 << 2)); 761 val &= ~(0x7 << 2); 762 val |= 0x2 << 2; 763 writel(val, priv->mmio + (0x20 << 2)); 764 765 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 766 writel(0x4, priv->mmio + (0xb << 2)); 767 768 /* Set PLL input clock divider 1/2 */ 769 val = readl(priv->mmio + (0x5 << 2)); 770 val &= ~(0x3 << 6); 771 val |= 0x1 << 6; 772 writel(val, priv->mmio + (0x5 << 2)); 773 774 /* Set PLL loop divider */ 775 writel(0x32, priv->mmio + (0x11 << 2)); 776 777 /* Set PLL KVCO to min and set PLL charge pump current to max */ 778 writel(0xf0, priv->mmio + (0xa << 2)); 779 780 /* Set Rx squelch input filler bandwidth */ 781 writel(0x0d, priv->mmio + (0x14 << 2)); 782 783 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 784 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 785 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 786 break; 787 case PHY_TYPE_SATA: 788 /* Enable adaptive CTLE for SATA Rx */ 789 val = readl(priv->mmio + (0x0e << 2)); 790 val &= ~GENMASK(0, 0); 791 val |= 0x01; 792 writel(val, priv->mmio + (0x0e << 2)); 793 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 794 writel(0x8F, priv->mmio + (0x06 << 2)); 795 796 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 797 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 798 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 799 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 800 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 801 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 802 break; 803 case PHY_TYPE_SGMII: 804 case PHY_TYPE_QSGMII: 805 default: 806 dev_err(priv->dev, "incompatible PHY type\n"); 807 return -EINVAL; 808 } 809 810 /* 100MHz refclock signal is good */ 811 clk_set_rate(&priv->ref_clk, 100000000); 812 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 813 if (priv->mode == PHY_TYPE_PCIE) { 814 /* PLL KVCO tuning fine */ 815 val = readl(priv->mmio + (0x20 << 2)); 816 val &= ~GENMASK(4, 2); 817 val |= 0x4 << 2; 818 writel(val, priv->mmio + (0x20 << 2)); 819 820 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 821 val = 0x4c; 822 writel(val, priv->mmio + (0x1b << 2)); 823 824 /* Set up su_trim: T3 */ 825 val = 0xb0; 826 writel(val, priv->mmio + (0xa << 2)); 827 val = 0x47; 828 writel(val, priv->mmio + (0xb << 2)); 829 val = 0x57; 830 writel(val, priv->mmio + (0xd << 2)); 831 } 832 833 return 0; 834 } 835 836 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 837 /* pipe-phy-grf */ 838 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 839 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 840 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 841 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 842 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 843 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 844 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 845 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 846 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 847 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 848 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 849 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 850 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 851 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 852 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 853 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 854 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 855 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 856 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 857 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 858 /* pipe-grf */ 859 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 860 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 861 }; 862 863 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 864 .grfcfg = &rk3588_combphy_grfcfgs, 865 .combphy_cfg = rk3588_combphy_cfg, 866 }; 867 #endif 868 869 870 #ifdef CONFIG_ROCKCHIP_RK3576 871 static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) 872 { 873 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 874 u32 val; 875 876 switch (priv->mode) { 877 case PHY_TYPE_PCIE: 878 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 879 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 880 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 881 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 882 break; 883 case PHY_TYPE_USB3: 884 /* Set SSC downward spread spectrum */ 885 val = readl(priv->mmio + (0x1f << 2)); 886 val &= ~GENMASK(5, 4); 887 val |= 0x01 << 4; 888 writel(val, priv->mmio + 0x7c); 889 890 /* Enable adaptive CTLE for USB3.0 Rx */ 891 val = readl(priv->mmio + (0x0e << 2)); 892 val &= ~GENMASK(0, 0); 893 val |= 0x01; 894 writel(val, priv->mmio + (0x0e << 2)); 895 896 /* Set PLL KVCO fine tuning signals */ 897 val = readl(priv->mmio + (0x20 << 2)); 898 val &= ~(0x7 << 2); 899 val |= 0x2 << 2; 900 writel(val, priv->mmio + (0x20 << 2)); 901 902 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 903 writel(0x4, priv->mmio + (0xb << 2)); 904 905 /* Set PLL input clock divider 1/2 */ 906 val = readl(priv->mmio + (0x5 << 2)); 907 val &= ~(0x3 << 6); 908 val |= 0x1 << 6; 909 writel(val, priv->mmio + (0x5 << 2)); 910 911 /* Set PLL loop divider */ 912 writel(0x32, priv->mmio + (0x11 << 2)); 913 914 /* Set PLL KVCO to min and set PLL charge pump current to max */ 915 writel(0xf0, priv->mmio + (0xa << 2)); 916 917 /* Set Rx squelch input filler bandwidth */ 918 writel(0x0d, priv->mmio + (0x14 << 2)); 919 920 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 921 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 922 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 923 break; 924 case PHY_TYPE_SATA: 925 /* Enable adaptive CTLE for SATA Rx */ 926 val = readl(priv->mmio + (0x0e << 2)); 927 val &= ~GENMASK(0, 0); 928 val |= 0x01; 929 writel(val, priv->mmio + (0x0e << 2)); 930 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 931 writel(0x8F, priv->mmio + (0x06 << 2)); 932 933 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 934 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 935 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 936 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 937 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 938 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 939 break; 940 case PHY_TYPE_SGMII: 941 case PHY_TYPE_QSGMII: 942 default: 943 dev_err(priv->dev, "incompatible PHY type\n"); 944 return -EINVAL; 945 } 946 947 /* 100MHz refclock signal is good */ 948 clk_set_rate(&priv->ref_clk, 100000000); 949 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 950 if (priv->mode == PHY_TYPE_PCIE) { 951 /* gate_tx_pck_sel length select work for L1SS */ 952 writel(0xc0, priv->mmio + 0x74); 953 954 /* PLL KVCO tuning fine */ 955 val = readl(priv->mmio + (0x20 << 2)); 956 val &= ~(0x7 << 2); 957 val |= 0x2 << 2; 958 writel(val, priv->mmio + (0x20 << 2)); 959 960 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 961 writel(0x4c, priv->mmio + (0x1b << 2)); 962 963 /* Set up su_trim: T3_P1 650mv */ 964 writel(0x90, priv->mmio + (0xa << 2)); 965 writel(0x43, priv->mmio + (0xb << 2)); 966 writel(0x88, priv->mmio + (0xc << 2)); 967 writel(0x56, priv->mmio + (0xd << 2)); 968 } 969 970 return 0; 971 } 972 973 static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { 974 /* pipe-phy-grf */ 975 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 976 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 977 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 978 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 979 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 980 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, 981 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 982 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 983 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 984 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 985 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 986 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 987 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 988 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 989 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 990 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 991 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 992 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 993 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 994 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 995 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 996 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 997 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 998 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 999 /* php-grf */ 1000 .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, 1001 .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, 1002 .u3otg1_port_en = { 0x0038, 15, 0, 0x0181, 0x1100 }, 1003 }; 1004 1005 static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { 1006 .grfcfg = &rk3576_combphy_grfcfgs, 1007 .combphy_cfg = rk3576_combphy_cfg, 1008 }; 1009 #endif 1010 1011 static const struct udevice_id rockchip_combphy_ids[] = { 1012 #ifdef CONFIG_ROCKCHIP_RK3528 1013 { 1014 .compatible = "rockchip,rk3528-naneng-combphy", 1015 .data = (ulong)&rk3528_combphy_cfgs 1016 }, 1017 #endif 1018 #ifdef CONFIG_ROCKCHIP_RK3562 1019 { 1020 .compatible = "rockchip,rk3562-naneng-combphy", 1021 .data = (ulong)&rk3562_combphy_cfgs 1022 }, 1023 #endif 1024 #ifdef CONFIG_ROCKCHIP_RK3568 1025 { 1026 .compatible = "rockchip,rk3568-naneng-combphy", 1027 .data = (ulong)&rk3568_combphy_cfgs 1028 }, 1029 #endif 1030 #ifdef CONFIG_ROCKCHIP_RK3588 1031 { 1032 .compatible = "rockchip,rk3588-naneng-combphy", 1033 .data = (ulong)&rk3588_combphy_cfgs 1034 }, 1035 #endif 1036 #ifdef CONFIG_ROCKCHIP_RK3576 1037 { 1038 .compatible = "rockchip,rk3576-naneng-combphy", 1039 .data = (ulong)&rk3576_combphy_cfgs 1040 }, 1041 #endif 1042 { } 1043 }; 1044 1045 U_BOOT_DRIVER(rockchip_naneng_combphy) = { 1046 .name = "naneng-combphy", 1047 .id = UCLASS_PHY, 1048 .of_match = rockchip_combphy_ids, 1049 .ops = &rochchip_combphy_ops, 1050 .probe = rockchip_combphy_probe, 1051 .priv_auto_alloc_size = sizeof(struct rockchip_combphy_priv), 1052 }; 1053