1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dt-bindings/phy/phy.h> 13 #include <generic-phy.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <regmap.h> 18 #include <reset-uclass.h> 19 20 #define BIT_WRITEABLE_SHIFT 16 21 22 struct rockchip_combphy_priv; 23 24 struct combphy_reg { 25 u32 offset; 26 u16 bitend; 27 u16 bitstart; 28 u16 disable; 29 u16 enable; 30 }; 31 32 struct rockchip_combphy_grfcfg { 33 struct combphy_reg pcie_mode_set; 34 struct combphy_reg usb_mode_set; 35 struct combphy_reg sgmii_mode_set; 36 struct combphy_reg qsgmii_mode_set; 37 struct combphy_reg pipe_rxterm_set; 38 struct combphy_reg pipe_txelec_set; 39 struct combphy_reg pipe_txcomp_set; 40 struct combphy_reg pipe_clk_24m; 41 struct combphy_reg pipe_clk_25m; 42 struct combphy_reg pipe_clk_100m; 43 struct combphy_reg pipe_phymode_sel; 44 struct combphy_reg pipe_rate_sel; 45 struct combphy_reg pipe_rxterm_sel; 46 struct combphy_reg pipe_txelec_sel; 47 struct combphy_reg pipe_txcomp_sel; 48 struct combphy_reg pipe_clk_ext; 49 struct combphy_reg pipe_sel_usb; 50 struct combphy_reg pipe_sel_qsgmii; 51 struct combphy_reg pipe_phy_status; 52 struct combphy_reg con0_for_pcie; 53 struct combphy_reg con1_for_pcie; 54 struct combphy_reg con2_for_pcie; 55 struct combphy_reg con3_for_pcie; 56 struct combphy_reg con0_for_sata; 57 struct combphy_reg con1_for_sata; 58 struct combphy_reg con2_for_sata; 59 struct combphy_reg con3_for_sata; 60 struct combphy_reg pipe_con0_for_sata; 61 struct combphy_reg pipe_con1_for_sata; 62 struct combphy_reg pipe_sgmii_mac_sel; 63 struct combphy_reg pipe_xpcs_phy_ready; 64 struct combphy_reg u3otg0_port_en; 65 struct combphy_reg u3otg1_port_en; 66 struct combphy_reg pipe_phy_grf_reset; 67 }; 68 69 struct rockchip_combphy_cfg { 70 const struct rockchip_combphy_grfcfg *grfcfg; 71 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 72 }; 73 74 struct rockchip_combphy_priv { 75 u32 mode; 76 void __iomem *mmio; 77 struct udevice *dev; 78 struct regmap *pipe_grf; 79 struct regmap *phy_grf; 80 struct phy *phy; 81 struct reset_ctl phy_rst; 82 struct clk ref_clk; 83 const struct rockchip_combphy_cfg *cfg; 84 }; 85 86 static int param_write(struct regmap *base, 87 const struct combphy_reg *reg, bool en) 88 { 89 u32 val, mask, tmp; 90 91 tmp = en ? reg->enable : reg->disable; 92 mask = GENMASK(reg->bitend, reg->bitstart); 93 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 94 95 return regmap_write(base, reg->offset, val); 96 } 97 98 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) 99 { 100 int ret = 0; 101 102 if (priv->cfg->combphy_cfg) { 103 ret = priv->cfg->combphy_cfg(priv); 104 if (ret) { 105 dev_err(priv->dev, "failed to init phy for pcie\n"); 106 return ret; 107 } 108 } 109 110 return ret; 111 } 112 113 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) 114 { 115 int ret = 0; 116 117 if (priv->cfg->combphy_cfg) { 118 ret = priv->cfg->combphy_cfg(priv); 119 if (ret) { 120 dev_err(priv->dev, "failed to init phy for usb3\n"); 121 return ret; 122 } 123 } 124 125 return ret; 126 } 127 128 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) 129 { 130 int ret = 0; 131 132 if (priv->cfg->combphy_cfg) { 133 ret = priv->cfg->combphy_cfg(priv); 134 if (ret) { 135 dev_err(priv->dev, "failed to init phy for sata\n"); 136 return ret; 137 } 138 } 139 140 return ret; 141 } 142 143 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) 144 { 145 int ret = 0; 146 147 if (priv->cfg->combphy_cfg) { 148 ret = priv->cfg->combphy_cfg(priv); 149 if (ret) { 150 dev_err(priv->dev, "failed to init phy for sgmii\n"); 151 return ret; 152 } 153 } 154 155 return ret; 156 } 157 158 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) 159 { 160 switch (priv->mode) { 161 case PHY_TYPE_PCIE: 162 rockchip_combphy_pcie_init(priv); 163 break; 164 case PHY_TYPE_USB3: 165 rockchip_combphy_usb3_init(priv); 166 break; 167 case PHY_TYPE_SATA: 168 rockchip_combphy_sata_init(priv); 169 break; 170 case PHY_TYPE_SGMII: 171 case PHY_TYPE_QSGMII: 172 return rockchip_combphy_sgmii_init(priv); 173 default: 174 dev_err(priv->dev, "incompatible PHY type\n"); 175 return -EINVAL; 176 } 177 178 return 0; 179 } 180 181 static int rockchip_combphy_init(struct phy *phy) 182 { 183 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 184 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 185 int ret; 186 187 ret = clk_enable(&priv->ref_clk); 188 if (ret < 0 && ret != -ENOSYS) 189 return ret; 190 191 ret = rockchip_combphy_set_mode(priv); 192 if (ret) 193 goto err_clk; 194 195 reset_deassert(&priv->phy_rst); 196 197 if (cfg->pipe_phy_grf_reset.enable) 198 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 199 200 return 0; 201 202 err_clk: 203 clk_disable(&priv->ref_clk); 204 205 return ret; 206 } 207 208 static int rockchip_combphy_exit(struct phy *phy) 209 { 210 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 211 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 212 213 if (cfg->pipe_phy_grf_reset.enable) 214 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); 215 216 reset_assert(&priv->phy_rst); 217 clk_disable(&priv->ref_clk); 218 219 return 0; 220 } 221 222 static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) 223 { 224 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 225 226 if (args->args_count != 1) { 227 pr_err("invalid number of arguments\n"); 228 return -EINVAL; 229 } 230 231 priv->mode = args->args[0]; 232 233 return 0; 234 } 235 236 static const struct phy_ops rochchip_combphy_ops = { 237 .init = rockchip_combphy_init, 238 .exit = rockchip_combphy_exit, 239 .of_xlate = rockchip_combphy_xlate, 240 }; 241 242 static int rockchip_combphy_parse_dt(struct udevice *dev, 243 struct rockchip_combphy_priv *priv) 244 { 245 struct udevice *syscon; 246 int ret; 247 u32 vals[4]; 248 249 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); 250 if (ret) { 251 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap ret= %d\n", ret); 252 return ret; 253 } 254 priv->pipe_grf = syscon_get_regmap(syscon); 255 256 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); 257 if (ret) { 258 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 259 return ret; 260 } 261 priv->phy_grf = syscon_get_regmap(syscon); 262 263 ret = clk_get_by_index(dev, 0, &priv->ref_clk); 264 if (ret) { 265 dev_err(dev, "failed to find ref clock\n"); 266 return PTR_ERR(&priv->ref_clk); 267 } 268 269 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); 270 if (ret) { 271 dev_err(dev, "no phy reset control specified\n"); 272 return ret; 273 } 274 275 if (!dev_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", 276 vals, ARRAY_SIZE(vals))) 277 regmap_write(priv->pipe_grf, vals[0], 278 (GENMASK(vals[2], vals[1]) << 16) | vals[3]); 279 280 return 0; 281 } 282 283 static int rockchip_combphy_probe(struct udevice *udev) 284 { 285 struct rockchip_combphy_priv *priv = dev_get_priv(udev); 286 const struct rockchip_combphy_cfg *phy_cfg; 287 288 priv->mmio = (void __iomem *)dev_read_addr(udev); 289 if (IS_ERR(priv->mmio)) 290 return PTR_ERR(priv->mmio); 291 292 phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); 293 if (!phy_cfg) { 294 dev_err(udev, "No OF match data provided\n"); 295 return -EINVAL; 296 } 297 298 priv->dev = udev; 299 priv->mode = PHY_TYPE_SATA; 300 priv->cfg = phy_cfg; 301 302 return rockchip_combphy_parse_dt(udev, priv); 303 } 304 305 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) 306 { 307 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 308 u32 val; 309 310 switch (priv->mode) { 311 case PHY_TYPE_PCIE: 312 /* Set SSC downward spread spectrum */ 313 val = readl(priv->mmio + 0x18); 314 val &= ~GENMASK(5, 4); 315 val |= 0x01 << 4; 316 writel(val, priv->mmio + 0x18); 317 318 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 319 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 320 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 321 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 322 break; 323 case PHY_TYPE_USB3: 324 /* Set SSC downward spread spectrum */ 325 val = readl(priv->mmio + 0x18); 326 val &= ~GENMASK(5, 4); 327 val |= 0x01 << 4; 328 writel(val, priv->mmio + 0x18); 329 330 /* Enable adaptive CTLE for USB3.0 Rx */ 331 val = readl(priv->mmio + 0x200); 332 val &= ~GENMASK(17, 17); 333 val |= 0x01; 334 writel(val, priv->mmio + 0x200); 335 336 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 337 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 338 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 339 break; 340 default: 341 dev_err(priv->dev, "incompatible PHY type\n"); 342 return -EINVAL; 343 } 344 345 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 346 if (priv->mode == PHY_TYPE_PCIE) { 347 /* PLL KVCO tuning fine */ 348 val = readl(priv->mmio + 0x18); 349 val &= ~(0x7 << 10); 350 val |= 0x2 << 10; 351 writel(val, priv->mmio + 0x18); 352 353 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ 354 val = readl(priv->mmio + 0x108); 355 val &= ~(0x7f7); 356 val |= 0x4f0; 357 writel(val, priv->mmio + 0x108); 358 } 359 360 return 0; 361 } 362 363 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { 364 /* pipe-phy-grf */ 365 .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 }, 366 .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 }, 367 .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 }, 368 .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 }, 369 .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 }, 370 .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 }, 371 .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 }, 372 .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 }, 373 .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 }, 374 .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 }, 375 .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 }, 376 .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 }, 377 .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 }, 378 .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 }, 379 .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 }, 380 .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 }, 381 /* pipe-grf */ 382 .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 }, 383 }; 384 385 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { 386 .grfcfg = &rk3528_combphy_grfcfgs, 387 .combphy_cfg = rk3528_combphy_cfg, 388 }; 389 390 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) 391 { 392 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 393 u32 val; 394 395 switch (priv->mode) { 396 case PHY_TYPE_PCIE: 397 /* Set SSC downward spread spectrum */ 398 val = readl(priv->mmio + (0x1f << 2)); 399 val &= ~GENMASK(5, 4); 400 val |= 0x01 << 4; 401 writel(val, priv->mmio + 0x7c); 402 403 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 404 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 405 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 406 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 407 break; 408 case PHY_TYPE_USB3: 409 /* Set SSC downward spread spectrum */ 410 val = readl(priv->mmio + (0x1f << 2)); 411 val &= ~GENMASK(5, 4); 412 val |= 0x01 << 4; 413 writel(val, priv->mmio + 0x7c); 414 415 /* Enable adaptive CTLE for USB3.0 Rx */ 416 val = readl(priv->mmio + (0x0e << 2)); 417 val &= ~GENMASK(0, 0); 418 val |= 0x01; 419 writel(val, priv->mmio + (0x0e << 2)); 420 421 /* Set PLL KVCO fine tuning signals */ 422 val = readl(priv->mmio + (0x20 << 2)); 423 val &= ~(0x7 << 2); 424 val |= 0x2 << 2; 425 writel(val, priv->mmio + (0x20 << 2)); 426 427 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 428 writel(0x4, priv->mmio + (0xb << 2)); 429 430 /* Set PLL input clock divider 1/2 */ 431 val = readl(priv->mmio + (0x5 << 2)); 432 val &= ~(0x3 << 6); 433 val |= 0x1 << 6; 434 writel(val, priv->mmio + (0x5 << 2)); 435 436 /* Set PLL loop divider */ 437 writel(0x32, priv->mmio + (0x11 << 2)); 438 439 /* Set PLL KVCO to min and set PLL charge pump current to max */ 440 writel(0xf0, priv->mmio + (0xa << 2)); 441 442 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 443 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 444 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 445 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 446 break; 447 default: 448 pr_err("%s, phy-type %d\n", __func__, priv->mode); 449 return -EINVAL; 450 } 451 452 clk_set_rate(&priv->ref_clk, 100000000); 453 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 454 455 if (priv->mode == PHY_TYPE_PCIE) { 456 /* PLL KVCO tuning fine */ 457 val = readl(priv->mmio + (0x20 << 2)); 458 val &= ~(0x7 << 2); 459 val |= 0x2 << 2; 460 writel(val, priv->mmio + (0x20 << 2)); 461 462 /* Enable controlling random jitter, aka RMJ */ 463 writel(0x4, priv->mmio + (0xb << 2)); 464 465 val = readl(priv->mmio + (0x5 << 2)); 466 val &= ~(0x3 << 6); 467 val |= 0x1 << 6; 468 writel(val, priv->mmio + (0x5 << 2)); 469 470 writel(0x32, priv->mmio + (0x11 << 2)); 471 writel(0xf0, priv->mmio + (0xa << 2)); 472 } 473 474 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 475 val = readl(priv->mmio + (0x7 << 2)); 476 val |= BIT(4); 477 writel(val, priv->mmio + (0x7 << 2)); 478 } 479 480 return 0; 481 } 482 483 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { 484 /* pipe-phy-grf */ 485 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 486 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 487 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 488 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 489 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 490 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 491 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 492 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 493 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 494 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 495 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 496 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 497 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 498 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 499 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 500 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 501 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 502 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 503 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 504 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 505 /* pipe-grf */ 506 .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 }, 507 }; 508 509 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { 510 .grfcfg = &rk3562_combphy_grfcfgs, 511 .combphy_cfg = rk3562_combphy_cfg, 512 }; 513 514 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 515 { 516 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 517 u32 val; 518 519 switch (priv->mode) { 520 case PHY_TYPE_PCIE: 521 /* Set SSC downward spread spectrum */ 522 val = readl(priv->mmio + (0x1f << 2)); 523 val &= ~GENMASK(5, 4); 524 val |= 0x01 << 4; 525 writel(val, priv->mmio + 0x7c); 526 527 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 528 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 529 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 530 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 531 break; 532 case PHY_TYPE_USB3: 533 /* Set SSC downward spread spectrum */ 534 val = readl(priv->mmio + (0x1f << 2)); 535 val &= ~GENMASK(5, 4); 536 val |= 0x01 << 4; 537 writel(val, priv->mmio + 0x7c); 538 539 /* Enable adaptive CTLE for USB3.0 Rx */ 540 val = readl(priv->mmio + (0x0e << 2)); 541 val &= ~GENMASK(0, 0); 542 val |= 0x01; 543 writel(val, priv->mmio + (0x0e << 2)); 544 545 /* Set PLL KVCO fine tuning signals */ 546 val = readl(priv->mmio + (0x20 << 2)); 547 val &= ~(0x7 << 2); 548 val |= 0x2 << 2; 549 writel(val, priv->mmio + (0x20 << 2)); 550 551 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 552 writel(0x4, priv->mmio + (0xb << 2)); 553 554 /* Set PLL input clock divider 1/2 */ 555 val = readl(priv->mmio + (0x5 << 2)); 556 val &= ~(0x3 << 6); 557 val |= 0x1 << 6; 558 writel(val, priv->mmio + (0x5 << 2)); 559 560 /* Set PLL loop divider */ 561 writel(0x32, priv->mmio + (0x11 << 2)); 562 563 /* Set PLL KVCO to min and set PLL charge pump current to max */ 564 writel(0xf0, priv->mmio + (0xa << 2)); 565 566 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 567 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 568 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 569 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 570 break; 571 case PHY_TYPE_SATA: 572 writel(0x41, priv->mmio + 0x38); 573 writel(0x8F, priv->mmio + 0x18); 574 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 575 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 576 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 577 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 578 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 579 break; 580 case PHY_TYPE_SGMII: 581 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 582 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 583 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 584 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 585 break; 586 case PHY_TYPE_QSGMII: 587 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 588 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 589 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 590 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 591 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 592 break; 593 default: 594 pr_err("%s, phy-type %d\n", __func__, priv->mode); 595 return -EINVAL; 596 } 597 598 /* The default ref clock is 25Mhz */ 599 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 600 601 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 602 val = readl(priv->mmio + (0x7 << 2)); 603 val |= BIT(4); 604 writel(val, priv->mmio + (0x7 << 2)); 605 } 606 607 return 0; 608 } 609 610 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 611 /* pipe-phy-grf */ 612 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 613 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 614 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 615 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 616 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 617 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 618 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 619 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 620 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 621 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 622 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 623 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 624 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 625 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 626 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 627 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 628 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 629 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 630 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 631 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 632 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 633 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 634 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 635 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 636 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 637 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 638 /* pipe-grf */ 639 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 640 .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, 641 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 642 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 643 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 644 }; 645 646 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 647 .grfcfg = &rk3568_combphy_grfcfgs, 648 .combphy_cfg = rk3568_combphy_cfg, 649 }; 650 651 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 652 { 653 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 654 u32 val; 655 656 switch (priv->mode) { 657 case PHY_TYPE_PCIE: 658 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 659 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 660 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 661 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 662 break; 663 case PHY_TYPE_USB3: 664 /* Set SSC downward spread spectrum */ 665 val = readl(priv->mmio + (0x1f << 2)); 666 val &= ~GENMASK(5, 4); 667 val |= 0x01 << 4; 668 writel(val, priv->mmio + 0x7c); 669 670 /* Enable adaptive CTLE for USB3.0 Rx */ 671 val = readl(priv->mmio + (0x0e << 2)); 672 val &= ~GENMASK(0, 0); 673 val |= 0x01; 674 writel(val, priv->mmio + (0x0e << 2)); 675 676 /* Set PLL KVCO fine tuning signals */ 677 val = readl(priv->mmio + (0x20 << 2)); 678 val &= ~(0x7 << 2); 679 val |= 0x2 << 2; 680 writel(val, priv->mmio + (0x20 << 2)); 681 682 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 683 writel(0x4, priv->mmio + (0xb << 2)); 684 685 /* Set PLL input clock divider 1/2 */ 686 val = readl(priv->mmio + (0x5 << 2)); 687 val &= ~(0x3 << 6); 688 val |= 0x1 << 6; 689 writel(val, priv->mmio + (0x5 << 2)); 690 691 /* Set PLL loop divider */ 692 writel(0x32, priv->mmio + (0x11 << 2)); 693 694 /* Set PLL KVCO to min and set PLL charge pump current to max */ 695 writel(0xf0, priv->mmio + (0xa << 2)); 696 697 /* Set Rx squelch input filler bandwidth */ 698 writel(0x0d, priv->mmio + (0x14 << 2)); 699 700 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 701 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 702 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 703 break; 704 case PHY_TYPE_SATA: 705 /* Enable adaptive CTLE for SATA Rx */ 706 val = readl(priv->mmio + (0x0e << 2)); 707 val &= ~GENMASK(0, 0); 708 val |= 0x01; 709 writel(val, priv->mmio + (0x0e << 2)); 710 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 711 writel(0x8F, priv->mmio + (0x06 << 2)); 712 713 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 714 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 715 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 716 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 717 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 718 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 719 break; 720 case PHY_TYPE_SGMII: 721 case PHY_TYPE_QSGMII: 722 default: 723 dev_err(priv->dev, "incompatible PHY type\n"); 724 return -EINVAL; 725 } 726 727 /* 100MHz refclock signal is good */ 728 clk_set_rate(&priv->ref_clk, 100000000); 729 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 730 if (priv->mode == PHY_TYPE_PCIE) { 731 /* PLL KVCO tuning fine */ 732 val = readl(priv->mmio + (0x20 << 2)); 733 val &= ~GENMASK(4, 2); 734 val |= 0x4 << 2; 735 writel(val, priv->mmio + (0x20 << 2)); 736 737 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 738 val = 0x4c; 739 writel(val, priv->mmio + (0x1b << 2)); 740 741 /* Set up su_trim: T3 */ 742 val = 0xb0; 743 writel(val, priv->mmio + (0xa << 2)); 744 val = 0x47; 745 writel(val, priv->mmio + (0xb << 2)); 746 val = 0x57; 747 writel(val, priv->mmio + (0xd << 2)); 748 } 749 750 return 0; 751 } 752 753 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 754 /* pipe-phy-grf */ 755 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 756 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 757 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 758 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 759 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 760 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 761 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 762 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 763 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 764 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 765 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 766 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 767 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 768 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 769 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 770 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 771 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 772 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 773 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 774 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 775 /* pipe-grf */ 776 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 777 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 778 }; 779 780 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 781 .grfcfg = &rk3588_combphy_grfcfgs, 782 .combphy_cfg = rk3588_combphy_cfg, 783 }; 784 785 static const struct udevice_id rockchip_combphy_ids[] = { 786 { 787 .compatible = "rockchip,rk3528-naneng-combphy", 788 .data = (ulong)&rk3528_combphy_cfgs 789 }, 790 { 791 .compatible = "rockchip,rk3562-naneng-combphy", 792 .data = (ulong)&rk3562_combphy_cfgs 793 }, 794 { 795 .compatible = "rockchip,rk3568-naneng-combphy", 796 .data = (ulong)&rk3568_combphy_cfgs 797 }, 798 { 799 .compatible = "rockchip,rk3588-naneng-combphy", 800 .data = (ulong)&rk3588_combphy_cfgs 801 }, 802 { } 803 }; 804 805 U_BOOT_DRIVER(rockchip_naneng_combphy) = { 806 .name = "naneng-combphy", 807 .id = UCLASS_PHY, 808 .of_match = rockchip_combphy_ids, 809 .ops = &rochchip_combphy_ops, 810 .probe = rockchip_combphy_probe, 811 .priv_auto_alloc_size = sizeof(struct rockchip_combphy_priv), 812 }; 813