1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <dm/lists.h> 12 #include <dt-bindings/phy/phy.h> 13 #include <generic-phy.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <regmap.h> 18 #include <reset-uclass.h> 19 #include <linux/iopoll.h> 20 21 #define BIT_WRITEABLE_SHIFT 16 22 23 struct rockchip_combphy_priv; 24 25 struct combphy_reg { 26 u32 offset; 27 u16 bitend; 28 u16 bitstart; 29 u16 disable; 30 u16 enable; 31 }; 32 33 struct rockchip_combphy_grfcfg { 34 struct combphy_reg pcie_mode_set; 35 struct combphy_reg usb_mode_set; 36 struct combphy_reg sgmii_mode_set; 37 struct combphy_reg qsgmii_mode_set; 38 struct combphy_reg pipe_rxterm_set; 39 struct combphy_reg pipe_txelec_set; 40 struct combphy_reg pipe_txcomp_set; 41 struct combphy_reg pipe_clk_24m; 42 struct combphy_reg pipe_clk_25m; 43 struct combphy_reg pipe_clk_100m; 44 struct combphy_reg pipe_phymode_sel; 45 struct combphy_reg pipe_rate_sel; 46 struct combphy_reg pipe_rxterm_sel; 47 struct combphy_reg pipe_txelec_sel; 48 struct combphy_reg pipe_txcomp_sel; 49 struct combphy_reg pipe_clk_ext; 50 struct combphy_reg pipe_sel_usb; 51 struct combphy_reg pipe_sel_qsgmii; 52 struct combphy_reg pipe_phy_status; 53 struct combphy_reg con0_for_pcie; 54 struct combphy_reg con1_for_pcie; 55 struct combphy_reg con2_for_pcie; 56 struct combphy_reg con3_for_pcie; 57 struct combphy_reg con0_for_sata; 58 struct combphy_reg con1_for_sata; 59 struct combphy_reg con2_for_sata; 60 struct combphy_reg con3_for_sata; 61 struct combphy_reg pipe_con0_for_sata; 62 struct combphy_reg pipe_con1_for_sata; 63 struct combphy_reg pipe_sgmii_mac_sel; 64 struct combphy_reg pipe_xpcs_phy_ready; 65 struct combphy_reg u3otg0_port_en; 66 struct combphy_reg u3otg1_port_en; 67 struct combphy_reg u3otg0_pipe_clk_sel; 68 struct combphy_reg pipe_phy_grf_reset; 69 }; 70 71 struct rockchip_combphy_cfg { 72 const struct rockchip_combphy_grfcfg *grfcfg; 73 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 74 }; 75 76 struct rockchip_combphy_priv { 77 u32 mode; 78 void __iomem *mmio; 79 struct udevice *dev; 80 struct regmap *pipe_grf; 81 struct regmap *phy_grf; 82 struct phy *phy; 83 struct reset_ctl phy_rst; 84 struct clk ref_clk; 85 const struct rockchip_combphy_cfg *cfg; 86 }; 87 88 static int param_write(struct regmap *base, 89 const struct combphy_reg *reg, bool en) 90 { 91 u32 val, mask, tmp; 92 93 tmp = en ? reg->enable : reg->disable; 94 mask = GENMASK(reg->bitend, reg->bitstart); 95 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 96 97 return regmap_write(base, reg->offset, val); 98 } 99 100 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) 101 { 102 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 103 u32 mask, val; 104 105 mask = GENMASK(cfg->pipe_phy_status.bitend, 106 cfg->pipe_phy_status.bitstart); 107 108 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); 109 val = (val & mask) >> cfg->pipe_phy_status.bitstart; 110 111 return val; 112 } 113 114 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) 115 { 116 int ret = 0; 117 118 if (priv->cfg->combphy_cfg) { 119 ret = priv->cfg->combphy_cfg(priv); 120 if (ret) { 121 dev_err(priv->dev, "failed to init phy for pcie\n"); 122 return ret; 123 } 124 } 125 126 return ret; 127 } 128 129 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) 130 { 131 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 132 int ret = 0; 133 134 if (dev_read_bool(priv->dev, "rockchip,dis-u3otg0-port")) { 135 ret = param_write(priv->pipe_grf, &cfg->u3otg0_port_en, false); 136 return ret; 137 } else if (dev_read_bool(priv->dev, "rockchip,dis-u3otg1-port")) { 138 param_write(priv->pipe_grf, &cfg->u3otg1_port_en, false); 139 #ifdef CONFIG_ROCKCHIP_RK3576 140 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 141 #endif 142 return ret; 143 } 144 145 if (priv->cfg->combphy_cfg) { 146 ret = priv->cfg->combphy_cfg(priv); 147 if (ret) { 148 dev_err(priv->dev, "failed to init phy for usb3\n"); 149 return ret; 150 } 151 } 152 153 return ret; 154 } 155 156 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) 157 { 158 int ret = 0; 159 160 if (priv->cfg->combphy_cfg) { 161 ret = priv->cfg->combphy_cfg(priv); 162 if (ret) { 163 dev_err(priv->dev, "failed to init phy for sata\n"); 164 return ret; 165 } 166 } 167 168 return ret; 169 } 170 171 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) 172 { 173 int ret = 0; 174 175 if (priv->cfg->combphy_cfg) { 176 ret = priv->cfg->combphy_cfg(priv); 177 if (ret) { 178 dev_err(priv->dev, "failed to init phy for sgmii\n"); 179 return ret; 180 } 181 } 182 183 return ret; 184 } 185 186 int rockchip_combphy_usb3_uboot_init(void) 187 { 188 struct udevice *udev; 189 struct rockchip_combphy_priv *priv; 190 const struct rockchip_combphy_grfcfg *cfg; 191 u32 val; 192 int ret; 193 194 ret = uclass_get_device_by_driver(UCLASS_PHY, 195 DM_GET_DRIVER(rockchip_naneng_combphy), 196 &udev); 197 if (ret) { 198 pr_err("%s: get usb3-phy node failed: %d\n", __func__, ret); 199 return ret; 200 } 201 202 priv = dev_get_priv(udev); 203 priv->mode = PHY_TYPE_USB3; 204 cfg = priv->cfg->grfcfg; 205 206 rockchip_combphy_usb3_init(priv); 207 reset_deassert(&priv->phy_rst); 208 209 if (cfg->pipe_phy_grf_reset.enable) 210 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 211 212 if (priv->mode == PHY_TYPE_USB3) { 213 ret = readx_poll_timeout(rockchip_combphy_is_ready, 214 priv, val, 215 val == cfg->pipe_phy_status.enable, 216 1000); 217 if (ret) { 218 dev_err(priv->dev, "wait phy status ready timeout\n"); 219 param_write(priv->phy_grf, &cfg->usb_mode_set, false); 220 if (cfg->u3otg0_pipe_clk_sel.disable) 221 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, false); 222 return ret; 223 } 224 } 225 226 /* Select clk_usb3otg0_pipe for source clk */ 227 if (cfg->u3otg0_pipe_clk_sel.disable) 228 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, true); 229 230 return ret; 231 } 232 233 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) 234 { 235 switch (priv->mode) { 236 case PHY_TYPE_PCIE: 237 rockchip_combphy_pcie_init(priv); 238 break; 239 case PHY_TYPE_USB3: 240 rockchip_combphy_usb3_init(priv); 241 break; 242 case PHY_TYPE_SATA: 243 rockchip_combphy_sata_init(priv); 244 break; 245 case PHY_TYPE_SGMII: 246 case PHY_TYPE_QSGMII: 247 return rockchip_combphy_sgmii_init(priv); 248 default: 249 dev_err(priv->dev, "incompatible PHY type\n"); 250 return -EINVAL; 251 } 252 253 return 0; 254 } 255 256 static int rockchip_combphy_init(struct phy *phy) 257 { 258 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 259 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 260 int ret; 261 262 ret = clk_enable(&priv->ref_clk); 263 if (ret < 0 && ret != -ENOSYS) 264 return ret; 265 266 ret = rockchip_combphy_set_mode(priv); 267 if (ret) 268 goto err_clk; 269 270 reset_deassert(&priv->phy_rst); 271 272 if (cfg->pipe_phy_grf_reset.enable) 273 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); 274 275 return 0; 276 277 err_clk: 278 clk_disable(&priv->ref_clk); 279 280 return ret; 281 } 282 283 static int rockchip_combphy_exit(struct phy *phy) 284 { 285 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 286 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 287 288 if (cfg->pipe_phy_grf_reset.enable) 289 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); 290 291 reset_assert(&priv->phy_rst); 292 clk_disable(&priv->ref_clk); 293 294 return 0; 295 } 296 297 static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) 298 { 299 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); 300 301 if (args->args_count != 1) { 302 pr_err("invalid number of arguments\n"); 303 return -EINVAL; 304 } 305 306 priv->mode = args->args[0]; 307 308 return 0; 309 } 310 311 static const struct phy_ops rochchip_combphy_ops = { 312 .init = rockchip_combphy_init, 313 .exit = rockchip_combphy_exit, 314 .of_xlate = rockchip_combphy_xlate, 315 }; 316 317 static int rockchip_combphy_parse_dt(struct udevice *dev, 318 struct rockchip_combphy_priv *priv) 319 { 320 struct udevice *syscon; 321 int ret; 322 u32 vals[4]; 323 324 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); 325 if (ret) { 326 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap ret= %d\n", ret); 327 return ret; 328 } 329 priv->pipe_grf = syscon_get_regmap(syscon); 330 331 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); 332 if (ret) { 333 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 334 return ret; 335 } 336 priv->phy_grf = syscon_get_regmap(syscon); 337 338 ret = clk_get_by_index(dev, 0, &priv->ref_clk); 339 if (ret) { 340 dev_err(dev, "failed to find ref clock\n"); 341 return PTR_ERR(&priv->ref_clk); 342 } 343 344 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); 345 if (ret) { 346 dev_err(dev, "no phy reset control specified\n"); 347 return ret; 348 } 349 350 if (!dev_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", 351 vals, ARRAY_SIZE(vals))) 352 regmap_write(priv->pipe_grf, vals[0], 353 (GENMASK(vals[2], vals[1]) << 16) | vals[3]); 354 355 return 0; 356 } 357 358 static int rockchip_combphy_probe(struct udevice *udev) 359 { 360 struct rockchip_combphy_priv *priv = dev_get_priv(udev); 361 const struct rockchip_combphy_cfg *phy_cfg; 362 363 priv->mmio = (void __iomem *)dev_read_addr(udev); 364 if (IS_ERR(priv->mmio)) 365 return PTR_ERR(priv->mmio); 366 367 phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); 368 if (!phy_cfg) { 369 dev_err(udev, "No OF match data provided\n"); 370 return -EINVAL; 371 } 372 373 priv->dev = udev; 374 priv->mode = PHY_TYPE_SATA; 375 priv->cfg = phy_cfg; 376 377 return rockchip_combphy_parse_dt(udev, priv); 378 } 379 380 #ifdef CONFIG_ROCKCHIP_RK3528 381 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) 382 { 383 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 384 u32 val; 385 386 switch (priv->mode) { 387 case PHY_TYPE_PCIE: 388 /* Set SSC downward spread spectrum */ 389 val = readl(priv->mmio + 0x18); 390 val &= ~GENMASK(5, 4); 391 val |= 0x01 << 4; 392 writel(val, priv->mmio + 0x18); 393 394 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 395 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 396 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 397 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 398 break; 399 case PHY_TYPE_USB3: 400 /* Set SSC downward spread spectrum */ 401 val = readl(priv->mmio + 0x18); 402 val &= ~GENMASK(5, 4); 403 val |= 0x01 << 4; 404 writel(val, priv->mmio + 0x18); 405 406 /* Enable adaptive CTLE for USB3.0 Rx */ 407 val = readl(priv->mmio + 0x200); 408 val &= ~GENMASK(17, 17); 409 val |= 0x01; 410 writel(val, priv->mmio + 0x200); 411 412 /* Set Rx squelch input filler bandwidth */ 413 val = readl(priv->mmio + 0x20c); 414 val &= ~GENMASK(2, 0); 415 val |= 0x06; 416 writel(val, priv->mmio + 0x20c); 417 418 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 419 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 420 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 421 break; 422 default: 423 dev_err(priv->dev, "incompatible PHY type\n"); 424 return -EINVAL; 425 } 426 427 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 428 if (priv->mode == PHY_TYPE_PCIE) { 429 /* PLL KVCO tuning fine */ 430 val = readl(priv->mmio + 0x18); 431 val &= ~(0x7 << 10); 432 val |= 0x2 << 10; 433 writel(val, priv->mmio + 0x18); 434 435 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ 436 val = readl(priv->mmio + 0x108); 437 val &= ~(0x7f7); 438 val |= 0x4f0; 439 writel(val, priv->mmio + 0x108); 440 } 441 442 return 0; 443 } 444 445 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { 446 /* pipe-phy-grf */ 447 .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 }, 448 .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 }, 449 .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 }, 450 .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 }, 451 .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 }, 452 .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 }, 453 .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 }, 454 .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 }, 455 .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 }, 456 .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 }, 457 .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 }, 458 .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 }, 459 .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 }, 460 .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 }, 461 .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 }, 462 .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 }, 463 /* pipe-grf */ 464 .u3otg0_pipe_clk_sel = { 0x40044, 7, 7, 0x01, 0x00 }, 465 .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 }, 466 }; 467 468 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { 469 .grfcfg = &rk3528_combphy_grfcfgs, 470 .combphy_cfg = rk3528_combphy_cfg, 471 }; 472 #endif 473 474 #ifdef CONFIG_ROCKCHIP_RK3562 475 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) 476 { 477 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 478 u32 val; 479 480 switch (priv->mode) { 481 case PHY_TYPE_PCIE: 482 /* Set SSC downward spread spectrum */ 483 val = readl(priv->mmio + (0x1f << 2)); 484 val &= ~GENMASK(5, 4); 485 val |= 0x01 << 4; 486 writel(val, priv->mmio + 0x7c); 487 488 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 489 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 490 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 491 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 492 break; 493 case PHY_TYPE_USB3: 494 /* Set SSC downward spread spectrum */ 495 val = readl(priv->mmio + (0x1f << 2)); 496 val &= ~GENMASK(5, 4); 497 val |= 0x01 << 4; 498 writel(val, priv->mmio + 0x7c); 499 500 /* Enable adaptive CTLE for USB3.0 Rx */ 501 val = readl(priv->mmio + (0x0e << 2)); 502 val &= ~GENMASK(0, 0); 503 val |= 0x01; 504 writel(val, priv->mmio + (0x0e << 2)); 505 506 /* Set PLL KVCO fine tuning signals */ 507 val = readl(priv->mmio + (0x20 << 2)); 508 val &= ~(0x7 << 2); 509 val |= 0x2 << 2; 510 writel(val, priv->mmio + (0x20 << 2)); 511 512 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 513 writel(0x4, priv->mmio + (0xb << 2)); 514 515 /* Set PLL input clock divider 1/2 */ 516 val = readl(priv->mmio + (0x5 << 2)); 517 val &= ~(0x3 << 6); 518 val |= 0x1 << 6; 519 writel(val, priv->mmio + (0x5 << 2)); 520 521 /* Set PLL loop divider */ 522 writel(0x32, priv->mmio + (0x11 << 2)); 523 524 /* Set PLL KVCO to min and set PLL charge pump current to max */ 525 writel(0xf0, priv->mmio + (0xa << 2)); 526 527 /* Set Rx squelch input filler bandwidth */ 528 writel(0x0e, priv->mmio + (0x14 << 2)); 529 530 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 531 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 532 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 533 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 534 break; 535 default: 536 pr_err("%s, phy-type %d\n", __func__, priv->mode); 537 return -EINVAL; 538 } 539 540 clk_set_rate(&priv->ref_clk, 100000000); 541 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 542 543 if (priv->mode == PHY_TYPE_PCIE) { 544 /* PLL KVCO tuning fine */ 545 val = readl(priv->mmio + (0x20 << 2)); 546 val &= ~(0x7 << 2); 547 val |= 0x2 << 2; 548 writel(val, priv->mmio + (0x20 << 2)); 549 550 /* Enable controlling random jitter, aka RMJ */ 551 writel(0x4, priv->mmio + (0xb << 2)); 552 553 val = readl(priv->mmio + (0x5 << 2)); 554 val &= ~(0x3 << 6); 555 val |= 0x1 << 6; 556 writel(val, priv->mmio + (0x5 << 2)); 557 558 writel(0x32, priv->mmio + (0x11 << 2)); 559 writel(0xf0, priv->mmio + (0xa << 2)); 560 } 561 562 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 563 val = readl(priv->mmio + (0x7 << 2)); 564 val |= BIT(4); 565 writel(val, priv->mmio + (0x7 << 2)); 566 } 567 568 return 0; 569 } 570 571 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { 572 /* pipe-phy-grf */ 573 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 574 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 575 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 576 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 577 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 578 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 579 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 580 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 581 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 582 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 583 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 584 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 585 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 586 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 587 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 588 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 589 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 590 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 591 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 592 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 593 /* pipe-grf */ 594 .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 }, 595 }; 596 597 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { 598 .grfcfg = &rk3562_combphy_grfcfgs, 599 .combphy_cfg = rk3562_combphy_cfg, 600 }; 601 #endif 602 603 #ifdef CONFIG_ROCKCHIP_RK3568 604 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 605 { 606 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 607 u32 val; 608 609 switch (priv->mode) { 610 case PHY_TYPE_PCIE: 611 /* Set SSC downward spread spectrum */ 612 val = readl(priv->mmio + (0x1f << 2)); 613 val &= ~GENMASK(5, 4); 614 val |= 0x01 << 4; 615 writel(val, priv->mmio + 0x7c); 616 617 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 618 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 619 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 620 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 621 break; 622 case PHY_TYPE_USB3: 623 /* Set SSC downward spread spectrum */ 624 val = readl(priv->mmio + (0x1f << 2)); 625 val &= ~GENMASK(5, 4); 626 val |= 0x01 << 4; 627 writel(val, priv->mmio + 0x7c); 628 629 /* Enable adaptive CTLE for USB3.0 Rx */ 630 val = readl(priv->mmio + (0x0e << 2)); 631 val &= ~GENMASK(0, 0); 632 val |= 0x01; 633 writel(val, priv->mmio + (0x0e << 2)); 634 635 /* Set PLL KVCO fine tuning signals */ 636 val = readl(priv->mmio + (0x20 << 2)); 637 val &= ~(0x7 << 2); 638 val |= 0x2 << 2; 639 writel(val, priv->mmio + (0x20 << 2)); 640 641 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 642 writel(0x4, priv->mmio + (0xb << 2)); 643 644 /* Set PLL input clock divider 1/2 */ 645 val = readl(priv->mmio + (0x5 << 2)); 646 val &= ~(0x3 << 6); 647 val |= 0x1 << 6; 648 writel(val, priv->mmio + (0x5 << 2)); 649 650 /* Set PLL loop divider */ 651 writel(0x32, priv->mmio + (0x11 << 2)); 652 653 /* Set PLL KVCO to min and set PLL charge pump current to max */ 654 writel(0xf0, priv->mmio + (0xa << 2)); 655 656 /* Set Rx squelch input filler bandwidth */ 657 writel(0x0e, priv->mmio + (0x14 << 2)); 658 659 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 660 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 661 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 662 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 663 break; 664 case PHY_TYPE_SATA: 665 writel(0x41, priv->mmio + 0x38); 666 writel(0x8F, priv->mmio + 0x18); 667 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 668 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 669 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 670 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 671 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 672 break; 673 case PHY_TYPE_SGMII: 674 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 675 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 676 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 677 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 678 break; 679 case PHY_TYPE_QSGMII: 680 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 681 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 682 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 683 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 684 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 685 break; 686 default: 687 pr_err("%s, phy-type %d\n", __func__, priv->mode); 688 return -EINVAL; 689 } 690 691 /* The default ref clock is 25Mhz */ 692 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 693 694 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { 695 val = readl(priv->mmio + (0x7 << 2)); 696 val |= BIT(4); 697 writel(val, priv->mmio + (0x7 << 2)); 698 } 699 700 return 0; 701 } 702 703 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 704 /* pipe-phy-grf */ 705 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 706 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 707 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 708 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 709 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 710 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 711 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 712 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 713 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 714 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 715 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 716 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 717 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 718 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 719 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 720 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 721 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 722 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 723 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 724 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 725 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 726 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 727 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 728 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 729 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 730 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 731 /* pipe-grf */ 732 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 733 .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, 734 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 735 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 736 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 737 }; 738 739 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 740 .grfcfg = &rk3568_combphy_grfcfgs, 741 .combphy_cfg = rk3568_combphy_cfg, 742 }; 743 #endif 744 745 #ifdef CONFIG_ROCKCHIP_RK3588 746 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 747 { 748 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 749 u32 val; 750 751 switch (priv->mode) { 752 case PHY_TYPE_PCIE: 753 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 754 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 755 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 756 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 757 break; 758 case PHY_TYPE_USB3: 759 /* Set SSC downward spread spectrum */ 760 val = readl(priv->mmio + (0x1f << 2)); 761 val &= ~GENMASK(5, 4); 762 val |= 0x01 << 4; 763 writel(val, priv->mmio + 0x7c); 764 765 /* Enable adaptive CTLE for USB3.0 Rx */ 766 val = readl(priv->mmio + (0x0e << 2)); 767 val &= ~GENMASK(0, 0); 768 val |= 0x01; 769 writel(val, priv->mmio + (0x0e << 2)); 770 771 /* Set PLL KVCO fine tuning signals */ 772 val = readl(priv->mmio + (0x20 << 2)); 773 val &= ~(0x7 << 2); 774 val |= 0x2 << 2; 775 writel(val, priv->mmio + (0x20 << 2)); 776 777 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 778 writel(0x4, priv->mmio + (0xb << 2)); 779 780 /* Set PLL input clock divider 1/2 */ 781 val = readl(priv->mmio + (0x5 << 2)); 782 val &= ~(0x3 << 6); 783 val |= 0x1 << 6; 784 writel(val, priv->mmio + (0x5 << 2)); 785 786 /* Set PLL loop divider */ 787 writel(0x32, priv->mmio + (0x11 << 2)); 788 789 /* Set PLL KVCO to min and set PLL charge pump current to max */ 790 writel(0xf0, priv->mmio + (0xa << 2)); 791 792 /* Set Rx squelch input filler bandwidth */ 793 writel(0x0d, priv->mmio + (0x14 << 2)); 794 795 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 796 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 797 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 798 break; 799 case PHY_TYPE_SATA: 800 /* Enable adaptive CTLE for SATA Rx */ 801 val = readl(priv->mmio + (0x0e << 2)); 802 val &= ~GENMASK(0, 0); 803 val |= 0x01; 804 writel(val, priv->mmio + (0x0e << 2)); 805 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 806 writel(0x8F, priv->mmio + (0x06 << 2)); 807 808 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 809 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 810 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 811 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 812 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 813 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 814 break; 815 case PHY_TYPE_SGMII: 816 case PHY_TYPE_QSGMII: 817 default: 818 dev_err(priv->dev, "incompatible PHY type\n"); 819 return -EINVAL; 820 } 821 822 /* 100MHz refclock signal is good */ 823 clk_set_rate(&priv->ref_clk, 100000000); 824 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 825 if (priv->mode == PHY_TYPE_PCIE) { 826 /* PLL KVCO tuning fine */ 827 val = readl(priv->mmio + (0x20 << 2)); 828 val &= ~GENMASK(4, 2); 829 val |= 0x4 << 2; 830 writel(val, priv->mmio + (0x20 << 2)); 831 832 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 833 val = 0x4c; 834 writel(val, priv->mmio + (0x1b << 2)); 835 836 /* Set up su_trim: T3 */ 837 val = 0xb0; 838 writel(val, priv->mmio + (0xa << 2)); 839 val = 0x47; 840 writel(val, priv->mmio + (0xb << 2)); 841 val = 0x57; 842 writel(val, priv->mmio + (0xd << 2)); 843 } 844 845 return 0; 846 } 847 848 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 849 /* pipe-phy-grf */ 850 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 851 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 852 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 853 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 854 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 855 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 856 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 857 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 858 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 859 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 860 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 861 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 862 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 863 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 864 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 865 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 866 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 867 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 868 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 869 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 870 /* pipe-grf */ 871 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 872 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 873 }; 874 875 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 876 .grfcfg = &rk3588_combphy_grfcfgs, 877 .combphy_cfg = rk3588_combphy_cfg, 878 }; 879 #endif 880 881 882 #ifdef CONFIG_ROCKCHIP_RK3576 883 static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) 884 { 885 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 886 u32 val; 887 888 switch (priv->mode) { 889 case PHY_TYPE_PCIE: 890 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 891 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 892 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 893 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 894 break; 895 case PHY_TYPE_USB3: 896 /* Set SSC downward spread spectrum */ 897 val = readl(priv->mmio + (0x1f << 2)); 898 val &= ~GENMASK(5, 4); 899 val |= 0x01 << 4; 900 writel(val, priv->mmio + 0x7c); 901 902 /* Enable adaptive CTLE for USB3.0 Rx */ 903 val = readl(priv->mmio + (0x0e << 2)); 904 val &= ~GENMASK(0, 0); 905 val |= 0x01; 906 writel(val, priv->mmio + (0x0e << 2)); 907 908 /* Set PLL KVCO fine tuning signals */ 909 val = readl(priv->mmio + (0x20 << 2)); 910 val &= ~(0x7 << 2); 911 val |= 0x2 << 2; 912 writel(val, priv->mmio + (0x20 << 2)); 913 914 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 915 writel(0x4, priv->mmio + (0xb << 2)); 916 917 /* Set PLL input clock divider 1/2 */ 918 val = readl(priv->mmio + (0x5 << 2)); 919 val &= ~(0x3 << 6); 920 val |= 0x1 << 6; 921 writel(val, priv->mmio + (0x5 << 2)); 922 923 /* Set PLL loop divider */ 924 writel(0x32, priv->mmio + (0x11 << 2)); 925 926 /* Set PLL KVCO to min and set PLL charge pump current to max */ 927 writel(0xf0, priv->mmio + (0xa << 2)); 928 929 /* Set Rx squelch input filler bandwidth */ 930 writel(0x0d, priv->mmio + (0x14 << 2)); 931 932 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 933 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 934 param_write(priv->phy_grf, &cfg->usb_mode_set, true); 935 break; 936 case PHY_TYPE_SATA: 937 /* Enable adaptive CTLE for SATA Rx */ 938 val = readl(priv->mmio + (0x0e << 2)); 939 val &= ~GENMASK(0, 0); 940 val |= 0x01; 941 writel(val, priv->mmio + (0x0e << 2)); 942 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 943 writel(0x8F, priv->mmio + (0x06 << 2)); 944 945 param_write(priv->phy_grf, &cfg->con0_for_sata, true); 946 param_write(priv->phy_grf, &cfg->con1_for_sata, true); 947 param_write(priv->phy_grf, &cfg->con2_for_sata, true); 948 param_write(priv->phy_grf, &cfg->con3_for_sata, true); 949 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 950 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 951 break; 952 case PHY_TYPE_SGMII: 953 case PHY_TYPE_QSGMII: 954 default: 955 dev_err(priv->dev, "incompatible PHY type\n"); 956 return -EINVAL; 957 } 958 959 /* 100MHz refclock signal is good */ 960 clk_set_rate(&priv->ref_clk, 100000000); 961 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 962 if (priv->mode == PHY_TYPE_PCIE) { 963 /* gate_tx_pck_sel length select work for L1SS */ 964 writel(0xc0, priv->mmio + 0x74); 965 966 /* PLL KVCO tuning fine */ 967 val = readl(priv->mmio + (0x20 << 2)); 968 val &= ~(0x7 << 2); 969 val |= 0x2 << 2; 970 writel(val, priv->mmio + (0x20 << 2)); 971 972 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 973 writel(0x4c, priv->mmio + (0x1b << 2)); 974 975 /* Set up su_trim: T3_P1 650mv */ 976 writel(0x90, priv->mmio + (0xa << 2)); 977 writel(0x43, priv->mmio + (0xb << 2)); 978 writel(0x88, priv->mmio + (0xc << 2)); 979 writel(0x56, priv->mmio + (0xd << 2)); 980 } 981 982 return 0; 983 } 984 985 static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { 986 /* pipe-phy-grf */ 987 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 988 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 989 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 990 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 991 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 992 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, 993 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 994 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 995 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 996 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 997 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 998 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 999 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 1000 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 1001 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 1002 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 1003 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 1004 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 1005 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 1006 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 1007 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 1008 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 1009 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 1010 .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, 1011 /* php-grf */ 1012 .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, 1013 .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, 1014 .u3otg1_port_en = { 0x0038, 15, 0, 0x0181, 0x1100 }, 1015 }; 1016 1017 static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { 1018 .grfcfg = &rk3576_combphy_grfcfgs, 1019 .combphy_cfg = rk3576_combphy_cfg, 1020 }; 1021 #endif 1022 1023 static const struct udevice_id rockchip_combphy_ids[] = { 1024 #ifdef CONFIG_ROCKCHIP_RK3528 1025 { 1026 .compatible = "rockchip,rk3528-naneng-combphy", 1027 .data = (ulong)&rk3528_combphy_cfgs 1028 }, 1029 #endif 1030 #ifdef CONFIG_ROCKCHIP_RK3562 1031 { 1032 .compatible = "rockchip,rk3562-naneng-combphy", 1033 .data = (ulong)&rk3562_combphy_cfgs 1034 }, 1035 #endif 1036 #ifdef CONFIG_ROCKCHIP_RK3568 1037 { 1038 .compatible = "rockchip,rk3568-naneng-combphy", 1039 .data = (ulong)&rk3568_combphy_cfgs 1040 }, 1041 #endif 1042 #ifdef CONFIG_ROCKCHIP_RK3588 1043 { 1044 .compatible = "rockchip,rk3588-naneng-combphy", 1045 .data = (ulong)&rk3588_combphy_cfgs 1046 }, 1047 #endif 1048 #ifdef CONFIG_ROCKCHIP_RK3576 1049 { 1050 .compatible = "rockchip,rk3576-naneng-combphy", 1051 .data = (ulong)&rk3576_combphy_cfgs 1052 }, 1053 #endif 1054 { } 1055 }; 1056 1057 U_BOOT_DRIVER(rockchip_naneng_combphy) = { 1058 .name = "naneng-combphy", 1059 .id = UCLASS_PHY, 1060 .of_match = rockchip_combphy_ids, 1061 .ops = &rochchip_combphy_ops, 1062 .probe = rockchip_combphy_probe, 1063 .priv_auto_alloc_size = sizeof(struct rockchip_combphy_priv), 1064 }; 1065