1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip DesignWare based PCIe host controller driver 4 * 5 * Copyright (c) 2021 Rockchip, Inc. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <generic-phy.h> 12 #include <pci.h> 13 #include <power-domain.h> 14 #include <power/regulator.h> 15 #include <reset.h> 16 #include <syscon.h> 17 #include <asm/io.h> 18 #include <asm-generic/gpio.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/bitfield.h> 21 #include <linux/iopoll.h> 22 #include <linux/ioport.h> 23 #include <linux/log2.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define RK_PCIE_DBG 0 28 29 #define __pcie_dev_print_emit(fmt, ...) \ 30 ({ \ 31 printf(fmt, ##__VA_ARGS__); \ 32 }) 33 34 #ifdef dev_err 35 #undef dev_err 36 #define dev_err(dev, fmt, ...) \ 37 ({ \ 38 if (dev) \ 39 __pcie_dev_print_emit("%s: " fmt, dev->name, \ 40 ##__VA_ARGS__); \ 41 }) 42 #endif 43 44 #ifdef dev_info 45 #undef dev_info 46 #define dev_info dev_err 47 #endif 48 49 #ifdef DEBUG 50 #define dev_dbg dev_err 51 #else 52 #define dev_dbg(dev, fmt, ...) \ 53 ({ \ 54 if (0) \ 55 __dev_printk(7, dev, fmt, ##__VA_ARGS__); \ 56 }) 57 #endif 58 59 struct rk_pcie { 60 struct udevice *dev; 61 struct udevice *vpcie3v3; 62 void *dbi_base; 63 void *apb_base; 64 void *cfg_base; 65 fdt_size_t cfg_size; 66 struct phy phy; 67 struct clk_bulk clks; 68 int first_busno; 69 struct reset_ctl_bulk rsts; 70 struct gpio_desc rst_gpio; 71 struct pci_region io; 72 struct pci_region mem; 73 struct pci_region mem64; 74 bool is_bifurcation; 75 u32 gen; 76 u32 lanes; 77 }; 78 79 enum { 80 PCIBIOS_SUCCESSFUL = 0x0000, 81 PCIBIOS_UNSUPPORTED = -ENODEV, 82 PCIBIOS_NODEV = -ENODEV, 83 }; 84 85 #define msleep(a) udelay((a) * 1000) 86 87 /* Parameters for the waiting for iATU enabled routine */ 88 #define PCIE_CLIENT_GENERAL_DEBUG 0x104 89 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 90 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) 91 #define PCIE_CLIENT_LTSSM_STATUS 0x300 92 #define SMLH_LINKUP BIT(16) 93 #define RDLH_LINKUP BIT(17) 94 #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310 95 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320 96 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324 97 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328 98 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c 99 #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350 100 #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 101 #define PCIE_CLIENT_DBF_EN 0xffff0003 102 103 /* PCI DBICS registers */ 104 #define PCIE_LINK_STATUS_REG 0x80 105 #define PCIE_LINK_STATUS_SPEED_OFF 16 106 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) 107 #define PCIE_LINK_STATUS_WIDTH_OFF 20 108 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) 109 110 #define PCIE_LINK_CAPABILITY 0x7c 111 #define PCIE_LINK_CTL_2 0xa0 112 #define TARGET_LINK_SPEED_MASK 0xf 113 #define LINK_SPEED_GEN_1 0x1 114 #define LINK_SPEED_GEN_2 0x2 115 #define LINK_SPEED_GEN_3 0x3 116 117 #define PCIE_PORT_LINK_CONTROL 0x710 118 #define PORT_LINK_FAST_LINK_MODE BIT(7) 119 #define PCIE_MISC_CONTROL_1_OFF 0x8bc 120 #define PCIE_DBI_RO_WR_EN BIT(0) 121 122 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c 123 #define PORT_LOGIC_SPEED_CHANGE BIT(17) 124 #define PORT_LINK_MODE_MASK GENMASK(21, 16) 125 #define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n) 126 #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1) 127 #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3) 128 #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) 129 #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) 130 #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8) 131 #define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n) 132 #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1) 133 #define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2) 134 #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4) 135 #define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8) 136 137 138 /* 139 * iATU Unroll-specific register definitions 140 * From 4.80 core version the address translation will be made by unroll. 141 * The registers are offset from atu_base 142 */ 143 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 144 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 145 #define PCIE_ATU_UNR_LOWER_BASE 0x08 146 #define PCIE_ATU_UNR_UPPER_BASE 0x0c 147 #define PCIE_ATU_UNR_LIMIT 0x10 148 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 149 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 150 151 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0) 152 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 153 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 154 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 155 #define PCIE_ATU_TYPE_IO (0x2 << 0) 156 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 157 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 158 #define PCIE_ATU_ENABLE (0x1 << 31) 159 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 160 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 161 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 162 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 163 164 /* Register address builder */ 165 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ 166 ((0x3 << 20) | ((region) << 9)) 167 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ 168 ((0x3 << 20) | ((region) << 9) | (0x1 << 8)) 169 170 /* Parameters for the waiting for iATU enabled routine */ 171 #define LINK_WAIT_MAX_IATU_RETRIES 5 172 #define LINK_WAIT_IATU 10000 173 174 #define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 175 176 static int rk_pcie_read(void __iomem *addr, int size, u32 *val) 177 { 178 if ((uintptr_t)addr & (size - 1)) { 179 *val = 0; 180 return PCIBIOS_UNSUPPORTED; 181 } 182 183 if (size == 4) { 184 *val = readl(addr); 185 } else if (size == 2) { 186 *val = readw(addr); 187 } else if (size == 1) { 188 *val = readb(addr); 189 } else { 190 *val = 0; 191 return PCIBIOS_NODEV; 192 } 193 194 return PCIBIOS_SUCCESSFUL; 195 } 196 197 static int rk_pcie_write(void __iomem *addr, int size, u32 val) 198 { 199 if ((uintptr_t)addr & (size - 1)) 200 return PCIBIOS_UNSUPPORTED; 201 202 if (size == 4) 203 writel(val, addr); 204 else if (size == 2) 205 writew(val, addr); 206 else if (size == 1) 207 writeb(val, addr); 208 else 209 return PCIBIOS_NODEV; 210 211 return PCIBIOS_SUCCESSFUL; 212 } 213 214 static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base, 215 u32 reg, size_t size) 216 { 217 int ret; 218 u32 val; 219 220 ret = rk_pcie_read(base + reg, size, &val); 221 if (ret) 222 dev_err(rk_pcie->dev, "Read APB address failed\n"); 223 224 return val; 225 } 226 227 static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base, 228 u32 reg, size_t size, u32 val) 229 { 230 int ret; 231 232 ret = rk_pcie_write(base + reg, size, val); 233 if (ret) 234 dev_err(rk_pcie->dev, "Write APB address failed\n"); 235 } 236 237 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg) 238 { 239 return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4); 240 } 241 242 static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, 243 u32 val) 244 { 245 __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val); 246 } 247 248 static int rk_pcie_get_link_speed(struct rk_pcie *rk_pcie) 249 { 250 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 251 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; 252 } 253 254 static int rk_pcie_get_link_width(struct rk_pcie *rk_pcie) 255 { 256 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 257 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; 258 } 259 260 static void rk_pcie_writel_ob_unroll(struct rk_pcie *rk_pcie, u32 index, 261 u32 reg, u32 val) 262 { 263 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 264 void __iomem *base = rk_pcie->dbi_base; 265 266 writel(val, base + offset + reg); 267 } 268 269 static u32 rk_pcie_readl_ob_unroll(struct rk_pcie *rk_pcie, u32 index, u32 reg) 270 { 271 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 272 void __iomem *base = rk_pcie->dbi_base; 273 274 return readl(base + offset + reg); 275 } 276 277 static inline void rk_pcie_dbi_write_enable(struct rk_pcie *rk_pcie, bool en) 278 { 279 u32 val; 280 281 val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 282 283 if (en) 284 val |= PCIE_DBI_RO_WR_EN; 285 else 286 val &= ~PCIE_DBI_RO_WR_EN; 287 writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 288 } 289 290 static void rk_pcie_setup_host(struct rk_pcie *rk_pcie) 291 { 292 u32 val; 293 294 rk_pcie_dbi_write_enable(rk_pcie, true); 295 296 /* setup RC BARs */ 297 writel(PCI_BASE_ADDRESS_MEM_TYPE_64, 298 rk_pcie->dbi_base + PCI_BASE_ADDRESS_0); 299 writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1); 300 301 /* setup interrupt pins */ 302 val = readl(rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 303 val &= 0xffff00ff; 304 val |= 0x00000100; 305 writel(val, rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 306 307 /* setup bus numbers */ 308 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 309 val &= 0xff000000; 310 val |= 0x00ff0100; 311 writel(val, rk_pcie->dbi_base + PCI_PRIMARY_BUS); 312 313 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 314 315 /* setup command register */ 316 val = readl(rk_pcie->dbi_base + PCI_COMMAND); 317 val &= 0xffff0000; 318 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 319 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 320 writel(val, rk_pcie->dbi_base + PCI_COMMAND); 321 322 /* program correct class for RC */ 323 writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE); 324 /* Better disable write permission right after the update */ 325 326 val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 327 val |= PORT_LOGIC_SPEED_CHANGE; 328 writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 329 330 /* Disable BAR0 BAR1 */ 331 writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 0 * 4); 332 writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 1 * 4); 333 334 rk_pcie_dbi_write_enable(rk_pcie, false); 335 } 336 337 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed, u32 cap_lanes) 338 { 339 u32 val; 340 341 rk_pcie_dbi_write_enable(pci, true); 342 343 val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY); 344 val &= ~TARGET_LINK_SPEED_MASK; 345 val |= cap_speed; 346 writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY); 347 348 val = readl(pci->dbi_base + PCIE_LINK_CTL_2); 349 val &= ~TARGET_LINK_SPEED_MASK; 350 val |= cap_speed; 351 writel(val, pci->dbi_base + PCIE_LINK_CTL_2); 352 353 val = readl(pci->dbi_base + PCIE_PORT_LINK_CONTROL); 354 355 /* Set the number of lanes */ 356 val &= ~PORT_LINK_FAST_LINK_MODE; 357 val &= ~PORT_LINK_MODE_MASK; 358 switch (cap_lanes) { 359 case 1: 360 val |= PORT_LINK_MODE_1_LANES; 361 break; 362 case 2: 363 val |= PORT_LINK_MODE_2_LANES; 364 break; 365 case 4: 366 val |= PORT_LINK_MODE_4_LANES; 367 break; 368 case 8: 369 val |= PORT_LINK_MODE_8_LANES; 370 break; 371 default: 372 dev_err(pci->dev, "cap_lanes %u: invalid value\n", cap_lanes); 373 return; 374 } 375 writel(val, pci->dbi_base + PCIE_PORT_LINK_CONTROL); 376 377 /* Set link width speed control register */ 378 val = readl(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 379 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 380 switch (cap_lanes) { 381 case 1: 382 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; 383 break; 384 case 2: 385 val |= PORT_LOGIC_LINK_WIDTH_2_LANES; 386 break; 387 case 4: 388 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; 389 break; 390 case 8: 391 val |= PORT_LOGIC_LINK_WIDTH_8_LANES; 392 break; 393 } 394 writel(val, pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 395 396 rk_pcie_dbi_write_enable(pci, false); 397 } 398 399 static void rk_pcie_prog_outbound_atu_unroll(struct rk_pcie *pci, int index, 400 int type, u64 cpu_addr, 401 u64 pci_addr, u32 size) 402 { 403 u32 retries, val; 404 405 dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n", 406 index, type, cpu_addr, pci_addr, size); 407 408 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, 409 lower_32_bits(cpu_addr)); 410 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, 411 upper_32_bits(cpu_addr)); 412 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, 413 lower_32_bits(cpu_addr + size - 1)); 414 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, 415 lower_32_bits(pci_addr)); 416 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, 417 upper_32_bits(pci_addr)); 418 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, 419 type); 420 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, 421 PCIE_ATU_ENABLE); 422 423 /* 424 * Make sure ATU enable takes effect before any subsequent config 425 * and I/O accesses. 426 */ 427 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 428 val = rk_pcie_readl_ob_unroll(pci, index, 429 PCIE_ATU_UNR_REGION_CTRL2); 430 if (val & PCIE_ATU_ENABLE) 431 return; 432 433 udelay(LINK_WAIT_IATU); 434 } 435 dev_err(pci->dev, "outbound iATU is not being enabled\n"); 436 } 437 438 static int rk_pcie_addr_valid(pci_dev_t d, int first_busno) 439 { 440 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) 441 return 0; 442 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) 443 return 0; 444 445 return 1; 446 } 447 448 static uintptr_t set_cfg_address(struct rk_pcie *pcie, 449 pci_dev_t d, uint where) 450 { 451 int bus = PCI_BUS(d) - pcie->first_busno; 452 uintptr_t va_address; 453 u32 atu_type; 454 455 /* Use dbi_base for own configuration read and write */ 456 if (!bus) { 457 va_address = (uintptr_t)pcie->dbi_base; 458 goto out; 459 } 460 461 if (bus == 1) 462 /* 463 * For local bus whose primary bus number is root bridge, 464 * change TLP Type field to 4. 465 */ 466 atu_type = PCIE_ATU_TYPE_CFG0; 467 else 468 /* Otherwise, change TLP Type field to 5. */ 469 atu_type = PCIE_ATU_TYPE_CFG1; 470 471 /* 472 * Not accessing root port configuration space? 473 * Region #0 is used for Outbound CFG space access. 474 * Direction = Outbound 475 * Region Index = 0 476 */ 477 d = PCI_MASK_BUS(d); 478 d = PCI_ADD_BUS(bus, d); 479 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 480 atu_type, (u64)pcie->cfg_base, 481 d << 8, pcie->cfg_size); 482 483 va_address = (uintptr_t)pcie->cfg_base; 484 485 out: 486 va_address += where & ~0x3; 487 488 return va_address; 489 } 490 491 static int rockchip_pcie_rd_conf(struct udevice *bus, pci_dev_t bdf, 492 uint offset, ulong *valuep, 493 enum pci_size_t size) 494 { 495 struct rk_pcie *pcie = dev_get_priv(bus); 496 uintptr_t va_address; 497 ulong value; 498 499 debug("PCIE CFG read: bdf=%2x:%2x:%2x\n", 500 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 501 502 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 503 debug("- out of range\n"); 504 *valuep = pci_get_ff(size); 505 return 0; 506 } 507 508 va_address = set_cfg_address(pcie, bdf, offset); 509 510 value = readl(va_address); 511 512 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 513 *valuep = pci_conv_32_to_size(value, offset, size); 514 515 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 516 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 517 pcie->io.bus_start, pcie->io.size); 518 519 return 0; 520 } 521 522 static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf, 523 uint offset, ulong value, 524 enum pci_size_t size) 525 { 526 struct rk_pcie *pcie = dev_get_priv(bus); 527 uintptr_t va_address; 528 ulong old; 529 530 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d)\n", 531 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 532 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 533 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 534 debug("- out of range\n"); 535 return 0; 536 } 537 538 va_address = set_cfg_address(pcie, bdf, offset); 539 540 old = readl(va_address); 541 value = pci_conv_size_to_32(old, value, offset, size); 542 writel(value, va_address); 543 544 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 545 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 546 pcie->io.bus_start, pcie->io.size); 547 548 return 0; 549 } 550 551 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie) 552 { 553 #if RK_PCIE_DBG 554 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0, 555 PCIE_CLIENT_DBG_TRANSITION_DATA); 556 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1, 557 PCIE_CLIENT_DBG_TRANSITION_DATA); 558 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0, 559 PCIE_CLIENT_DBG_TRANSITION_DATA); 560 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1, 561 PCIE_CLIENT_DBG_TRANSITION_DATA); 562 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON, 563 PCIE_CLIENT_DBF_EN); 564 #endif 565 } 566 567 static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie) 568 { 569 #if RK_PCIE_DBG 570 u32 loop; 571 572 dev_err(rk_pcie->dev, "ltssm = 0x%x\n", 573 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); 574 for (loop = 0; loop < 64; loop++) 575 dev_err(rk_pcie->dev, "fifo_status = 0x%x\n", 576 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS)); 577 #endif 578 } 579 580 static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie) 581 { 582 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0); 583 } 584 585 static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie) 586 { 587 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008); 588 } 589 590 static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie) 591 { 592 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c); 593 } 594 595 static int is_link_up(struct rk_pcie *priv) 596 { 597 u32 val; 598 599 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS); 600 if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 && 601 (val & GENMASK(5, 0)) == 0x11) 602 return 1; 603 604 return 0; 605 } 606 607 static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed, u32 cap_lanes) 608 { 609 int retries; 610 611 if (is_link_up(priv)) { 612 printf("PCI Link already up before configuration!\n"); 613 return 1; 614 } 615 616 /* DW pre link configurations */ 617 rk_pcie_configure(priv, cap_speed, cap_lanes); 618 619 /* Release the device */ 620 if (dm_gpio_is_valid(&priv->rst_gpio)) { 621 /* 622 * T_PVPERL (Power stable to PERST# inactive) should be a minimum of 100ms. 623 * We add a 200ms by default for sake of hoping everthings 624 * work fine. 625 */ 626 msleep(200); 627 dm_gpio_set_value(&priv->rst_gpio, 1); 628 /* 629 * Add this 20ms delay because we observe link is always up stably after it and 630 * could help us save 20ms for scanning devices. 631 */ 632 msleep(20); 633 } 634 635 rk_pcie_disable_ltssm(priv); 636 rk_pcie_link_status_clear(priv); 637 rk_pcie_enable_debug(priv); 638 639 /* Enable LTSSM */ 640 rk_pcie_enable_ltssm(priv); 641 642 for (retries = 0; retries < 50; retries++) { 643 if (is_link_up(priv)) { 644 dev_info(priv->dev, "PCIe Link up, LTSSM is 0x%x\n", 645 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 646 rk_pcie_debug_dump(priv); 647 /* Link maybe in Gen switch recovery but we need to wait more 1s */ 648 msleep(1000); 649 return 0; 650 } 651 652 dev_info(priv->dev, "PCIe Linking... LTSSM is 0x%x\n", 653 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 654 rk_pcie_debug_dump(priv); 655 msleep(10); 656 } 657 658 dev_err(priv->dev, "PCIe-%d Link Fail\n", priv->dev->seq); 659 rk_pcie_disable_ltssm(priv); 660 return -EINVAL; 661 } 662 663 static int rockchip_pcie_init_port(struct udevice *dev) 664 { 665 int ret; 666 u32 val; 667 struct rk_pcie *priv = dev_get_priv(dev); 668 union phy_configure_opts phy_cfg; 669 670 /* Rest the device */ 671 if (dm_gpio_is_valid(&priv->rst_gpio)) 672 dm_gpio_set_value(&priv->rst_gpio, 0); 673 674 /* Set power and maybe external ref clk input */ 675 if (priv->vpcie3v3) { 676 ret = regulator_set_enable(priv->vpcie3v3, true); 677 if (ret) { 678 dev_err(priv->dev, "failed to enable vpcie3v3 (ret=%d)\n", 679 ret); 680 return ret; 681 } 682 } 683 684 if (priv->is_bifurcation) { 685 phy_cfg.pcie.is_bifurcation = true; 686 ret = generic_phy_configure(&priv->phy, &phy_cfg); 687 if (ret) 688 dev_err(dev, "failed to set bifurcation for phy (ret=%d)\n", ret); 689 } 690 691 ret = generic_phy_init(&priv->phy); 692 if (ret) { 693 dev_err(dev, "failed to init phy (ret=%d)\n", ret); 694 goto err_disable_3v3; 695 } 696 697 ret = generic_phy_power_on(&priv->phy); 698 if (ret) { 699 dev_err(dev, "failed to power on phy (ret=%d)\n", ret); 700 goto err_exit_phy; 701 } 702 703 ret = reset_deassert_bulk(&priv->rsts); 704 if (ret) { 705 dev_err(dev, "failed to deassert resets (ret=%d)\n", ret); 706 goto err_power_off_phy; 707 } 708 709 ret = clk_enable_bulk(&priv->clks); 710 if (ret) { 711 dev_err(dev, "failed to enable clks (ret=%d)\n", ret); 712 goto err_deassert_bulk; 713 } 714 715 /* LTSSM EN ctrl mode */ 716 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL); 717 val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); 718 rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val); 719 720 /* Set RC mode */ 721 rk_pcie_writel_apb(priv, 0x0, 0xf00040); 722 rk_pcie_setup_host(priv); 723 724 ret = rk_pcie_link_up(priv, priv->gen, priv->lanes); 725 if (ret < 0) 726 goto err_link_up; 727 728 return 0; 729 err_link_up: 730 clk_disable_bulk(&priv->clks); 731 err_deassert_bulk: 732 reset_assert_bulk(&priv->rsts); 733 err_power_off_phy: 734 generic_phy_power_off(&priv->phy); 735 err_exit_phy: 736 generic_phy_exit(&priv->phy); 737 err_disable_3v3: 738 if(priv->vpcie3v3) 739 regulator_set_enable(priv->vpcie3v3, false); 740 return ret; 741 } 742 743 static int rockchip_pcie_parse_dt(struct udevice *dev) 744 { 745 struct rk_pcie *priv = dev_get_priv(dev); 746 u32 max_link_speed, num_lanes; 747 int ret; 748 struct resource res; 749 750 ret = dev_read_resource_byname(dev, "pcie-dbi", &res); 751 if (ret) 752 return -ENODEV; 753 priv->dbi_base = (void *)(res.start); 754 dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base); 755 756 ret = dev_read_resource_byname(dev, "pcie-apb", &res); 757 if (ret) 758 return -ENODEV; 759 priv->apb_base = (void *)(res.start); 760 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); 761 762 ret = gpio_request_by_name(dev, "reset-gpios", 0, 763 &priv->rst_gpio, GPIOD_IS_OUT); 764 if (ret) { 765 dev_err(dev, "failed to find reset-gpios property\n"); 766 return ret; 767 } 768 769 ret = reset_get_bulk(dev, &priv->rsts); 770 if (ret) { 771 dev_err(dev, "Can't get reset: %d\n", ret); 772 return ret; 773 } 774 775 ret = clk_get_bulk(dev, &priv->clks); 776 if (ret) { 777 dev_err(dev, "Can't get clock: %d\n", ret); 778 return ret; 779 } 780 781 ret = device_get_supply_regulator(dev, "vpcie3v3-supply", 782 &priv->vpcie3v3); 783 if (ret && ret != -ENOENT) { 784 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret); 785 return ret; 786 } 787 788 ret = generic_phy_get_by_index(dev, 0, &priv->phy); 789 if (ret) { 790 dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret); 791 return ret; 792 } 793 794 if (dev_read_bool(dev, "rockchip,bifurcation")) 795 priv->is_bifurcation = true; 796 797 ret = ofnode_read_u32(dev->node, "max-link-speed", &max_link_speed); 798 if (ret < 0 || max_link_speed > 4) 799 priv->gen = 0; 800 else 801 priv->gen = max_link_speed; 802 803 ret = ofnode_read_u32(dev->node, "num-lanes", &num_lanes); 804 if (ret >= 0 && ilog2(num_lanes) >= 0 && ilog2(num_lanes) <= 3) 805 priv->lanes = num_lanes; 806 807 return 0; 808 } 809 810 static int rockchip_pcie_probe(struct udevice *dev) 811 { 812 struct rk_pcie *priv = dev_get_priv(dev); 813 struct udevice *ctlr = pci_get_controller(dev); 814 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 815 int ret; 816 817 priv->first_busno = dev->seq; 818 priv->dev = dev; 819 820 ret = rockchip_pcie_parse_dt(dev); 821 if (ret) 822 return ret; 823 824 ret = rockchip_pcie_init_port(dev); 825 if (ret) 826 goto free_rst; 827 828 dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", 829 dev->seq, rk_pcie_get_link_speed(priv), 830 rk_pcie_get_link_width(priv), 831 hose->first_busno); 832 833 for (ret = 0; ret < hose->region_count; ret++) { 834 if (hose->regions[ret].flags == PCI_REGION_IO) { 835 priv->io.phys_start = hose->regions[ret].phys_start; /* IO base */ 836 priv->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */ 837 priv->io.size = hose->regions[ret].size; /* IO size */ 838 } else if (hose->regions[ret].flags == PCI_REGION_MEM) { 839 if (upper_32_bits(hose->regions[ret].bus_start)) {/* MEM64 base */ 840 priv->mem64.phys_start = hose->regions[ret].phys_start; 841 priv->mem64.bus_start = hose->regions[ret].bus_start; 842 priv->mem64.size = hose->regions[ret].size; 843 } else { /* MEM32 base */ 844 priv->mem.phys_start = hose->regions[ret].phys_start; 845 priv->mem.bus_start = hose->regions[ret].bus_start; 846 priv->mem.size = hose->regions[ret].size; 847 } 848 } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { 849 priv->cfg_base = (void *)(priv->io.phys_start - priv->io.size); 850 priv->cfg_size = priv->io.size; 851 } else if (hose->regions[ret].flags == PCI_REGION_PREFETCH) { 852 dev_err(dev, "don't support prefetchable memory, please fix your dtb.\n"); 853 } else { 854 dev_err(dev, "invalid flags type\n"); 855 } 856 } 857 858 #ifdef CONFIG_SYS_PCI_64BIT 859 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 860 priv->cfg_base, priv->cfg_base + priv->cfg_size, 861 priv->cfg_size); 862 863 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%llx]\n", 864 priv->io.phys_start, priv->io.phys_start + priv->io.size, 865 priv->io.size); 866 867 dev_dbg(dev, "IO bus: [0x%llx - 0x%llx, size 0x%llx]\n", 868 priv->io.bus_start, priv->io.bus_start + priv->io.size, 869 priv->io.size); 870 871 dev_dbg(dev, "MEM32 space: [0x%llx - 0x%llx, size 0x%llx]\n", 872 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 873 priv->mem.size); 874 875 dev_dbg(dev, "MEM32 bus: [0x%llx - 0x%llx, size 0x%llx]\n", 876 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 877 priv->mem.size); 878 879 dev_dbg(dev, "MEM64 space: [0x%llx - 0x%llx, size 0x%llx]\n", 880 priv->mem64.phys_start, priv->mem64.phys_start + priv->mem64.size, 881 priv->mem64.size); 882 883 dev_dbg(dev, "MEM64 bus: [0x%llx - 0x%llx, size 0x%llx]\n", 884 priv->mem64.bus_start, priv->mem64.bus_start + priv->mem64.size, 885 priv->mem64.size); 886 887 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX2, 888 PCIE_ATU_TYPE_MEM, 889 priv->mem64.phys_start, 890 priv->mem64.bus_start, priv->mem64.size); 891 #else 892 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 893 priv->cfg_base, priv->cfg_base + priv->cfg_size, 894 priv->cfg_size); 895 896 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%x]\n", 897 priv->io.phys_start, priv->io.phys_start + priv->io.size, 898 priv->io.size); 899 900 dev_dbg(dev, "IO bus: [0x%x - 0x%x, size 0x%x]\n", 901 priv->io.bus_start, priv->io.bus_start + priv->io.size, 902 priv->io.size); 903 904 dev_dbg(dev, "MEM32 space: [0x%llx - 0x%llx, size 0x%x]\n", 905 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 906 priv->mem.size); 907 908 dev_dbg(dev, "MEM32 bus: [0x%x - 0x%x, size 0x%x]\n", 909 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 910 priv->mem.size); 911 912 #endif 913 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX0, 914 PCIE_ATU_TYPE_MEM, 915 priv->mem.phys_start, 916 priv->mem.bus_start, priv->mem.size); 917 918 return 0; 919 free_rst: 920 dm_gpio_free(dev, &priv->rst_gpio); 921 return ret; 922 } 923 924 static const struct dm_pci_ops rockchip_pcie_ops = { 925 .read_config = rockchip_pcie_rd_conf, 926 .write_config = rockchip_pcie_wr_conf, 927 }; 928 929 static const struct udevice_id rockchip_pcie_ids[] = { 930 { .compatible = "rockchip,rk3528-pcie" }, 931 { .compatible = "rockchip,rk3562-pcie" }, 932 { .compatible = "rockchip,rk3568-pcie" }, 933 { .compatible = "rockchip,rk3588-pcie" }, 934 { .compatible = "rockchip,rk3576-pcie" }, 935 { } 936 }; 937 938 U_BOOT_DRIVER(rockchip_pcie) = { 939 .name = "pcie_dw_rockchip", 940 .id = UCLASS_PCI, 941 .of_match = rockchip_pcie_ids, 942 .ops = &rockchip_pcie_ops, 943 .probe = rockchip_pcie_probe, 944 .priv_auto_alloc_size = sizeof(struct rk_pcie), 945 }; 946