1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip DesignWare based PCIe host controller driver 4 * 5 * Copyright (c) 2021 Rockchip, Inc. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <generic-phy.h> 12 #include <pci.h> 13 #include <power-domain.h> 14 #include <power/regulator.h> 15 #include <reset.h> 16 #include <syscon.h> 17 #include <asm/io.h> 18 #include <asm-generic/gpio.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 struct rk_pcie { 25 struct udevice *dev; 26 struct udevice *vpcie3v3; 27 void *dbi_base; 28 void *apb_base; 29 void *cfg_base; 30 fdt_size_t cfg_size; 31 struct phy phy; 32 struct clk_bulk clks; 33 int first_busno; 34 struct reset_ctl_bulk rsts; 35 struct gpio_desc rst_gpio; 36 struct pci_region io; 37 struct pci_region mem; 38 }; 39 40 enum { 41 PCIBIOS_SUCCESSFUL = 0x0000, 42 PCIBIOS_UNSUPPORTED = -ENODEV, 43 PCIBIOS_NODEV = -ENODEV, 44 }; 45 46 #define msleep(a) udelay((a) * 1000) 47 48 /* Parameters for the waiting for iATU enabled routine */ 49 #define PCIE_CLIENT_GENERAL_DEBUG 0x104 50 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 51 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) 52 #define PCIE_CLIENT_LTSSM_STATUS 0x300 53 #define SMLH_LINKUP BIT(16) 54 #define RDLH_LINKUP BIT(17) 55 #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310 56 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320 57 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324 58 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328 59 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c 60 #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350 61 #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 62 #define PCIE_CLIENT_DBF_EN 0xffff0003 63 #define RK_PCIE_DBG 0 64 65 /* PCI DBICS registers */ 66 #define PCIE_LINK_STATUS_REG 0x80 67 #define PCIE_LINK_STATUS_SPEED_OFF 16 68 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) 69 #define PCIE_LINK_STATUS_WIDTH_OFF 20 70 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) 71 72 #define PCIE_LINK_CAPABILITY 0x7c 73 #define PCIE_LINK_CTL_2 0xa0 74 #define TARGET_LINK_SPEED_MASK 0xf 75 #define LINK_SPEED_GEN_1 0x1 76 #define LINK_SPEED_GEN_2 0x2 77 #define LINK_SPEED_GEN_3 0x3 78 79 #define PCIE_MISC_CONTROL_1_OFF 0x8bc 80 #define PCIE_DBI_RO_WR_EN BIT(0) 81 82 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c 83 #define PORT_LOGIC_SPEED_CHANGE BIT(17) 84 85 /* 86 * iATU Unroll-specific register definitions 87 * From 4.80 core version the address translation will be made by unroll. 88 * The registers are offset from atu_base 89 */ 90 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 91 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 92 #define PCIE_ATU_UNR_LOWER_BASE 0x08 93 #define PCIE_ATU_UNR_UPPER_BASE 0x0c 94 #define PCIE_ATU_UNR_LIMIT 0x10 95 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 96 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 97 98 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 99 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 100 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 101 #define PCIE_ATU_TYPE_IO (0x2 << 0) 102 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 103 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 104 #define PCIE_ATU_ENABLE (0x1 << 31) 105 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 106 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 107 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 108 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 109 110 /* Register address builder */ 111 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ 112 ((0x3 << 20) | ((region) << 9)) 113 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ 114 ((0x3 << 20) | ((region) << 9) | (0x1 << 8)) 115 116 /* Parameters for the waiting for iATU enabled routine */ 117 #define LINK_WAIT_MAX_IATU_RETRIES 5 118 #define LINK_WAIT_IATU 10000 119 120 static int rk_pcie_read(void __iomem *addr, int size, u32 *val) 121 { 122 if ((uintptr_t)addr & (size - 1)) { 123 *val = 0; 124 return PCIBIOS_UNSUPPORTED; 125 } 126 127 if (size == 4) { 128 *val = readl(addr); 129 } else if (size == 2) { 130 *val = readw(addr); 131 } else if (size == 1) { 132 *val = readb(addr); 133 } else { 134 *val = 0; 135 return PCIBIOS_NODEV; 136 } 137 138 return PCIBIOS_SUCCESSFUL; 139 } 140 141 static int rk_pcie_write(void __iomem *addr, int size, u32 val) 142 { 143 if ((uintptr_t)addr & (size - 1)) 144 return PCIBIOS_UNSUPPORTED; 145 146 if (size == 4) 147 writel(val, addr); 148 else if (size == 2) 149 writew(val, addr); 150 else if (size == 1) 151 writeb(val, addr); 152 else 153 return PCIBIOS_NODEV; 154 155 return PCIBIOS_SUCCESSFUL; 156 } 157 158 static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base, 159 u32 reg, size_t size) 160 { 161 int ret; 162 u32 val; 163 164 ret = rk_pcie_read(base + reg, size, &val); 165 if (ret) 166 dev_err(rk_pcie->pci->dev, "Read APB address failed\n"); 167 168 return val; 169 } 170 171 static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base, 172 u32 reg, size_t size, u32 val) 173 { 174 int ret; 175 176 ret = rk_pcie_write(base + reg, size, val); 177 if (ret) 178 dev_err(rk_pcie->pci->dev, "Write APB address failed\n"); 179 } 180 181 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg) 182 { 183 return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4); 184 } 185 186 static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, 187 u32 val) 188 { 189 __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val); 190 } 191 192 static int rk_pcie_get_link_speed(struct rk_pcie *rk_pcie) 193 { 194 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 195 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; 196 } 197 198 static int rk_pcie_get_link_width(struct rk_pcie *rk_pcie) 199 { 200 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 201 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; 202 } 203 204 static void rk_pcie_writel_ob_unroll(struct rk_pcie *rk_pcie, u32 index, 205 u32 reg, u32 val) 206 { 207 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 208 void __iomem *base = rk_pcie->dbi_base; 209 210 writel(val, base + offset + reg); 211 } 212 213 static u32 rk_pcie_readl_ob_unroll(struct rk_pcie *rk_pcie, u32 index, u32 reg) 214 { 215 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 216 void __iomem *base = rk_pcie->dbi_base; 217 218 return readl(base + offset + reg); 219 } 220 221 static inline void rk_pcie_dbi_write_enable(struct rk_pcie *rk_pcie, bool en) 222 { 223 u32 val; 224 225 val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 226 227 if (en) 228 val |= PCIE_DBI_RO_WR_EN; 229 else 230 val &= ~PCIE_DBI_RO_WR_EN; 231 writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 232 } 233 234 static void rk_pcie_setup_host(struct rk_pcie *rk_pcie) 235 { 236 u32 val; 237 238 rk_pcie_dbi_write_enable(rk_pcie, true); 239 240 /* setup RC BARs */ 241 writel(PCI_BASE_ADDRESS_MEM_TYPE_64, 242 rk_pcie->dbi_base + PCI_BASE_ADDRESS_0); 243 writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1); 244 245 /* setup interrupt pins */ 246 val = readl(rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 247 val &= 0xffff00ff; 248 val |= 0x00000100; 249 writel(val, rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 250 251 /* setup bus numbers */ 252 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 253 val &= 0xff000000; 254 val |= 0x00ff0100; 255 writel(val, rk_pcie->dbi_base + PCI_PRIMARY_BUS); 256 257 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 258 259 /* setup command register */ 260 val = readl(rk_pcie->dbi_base + PCI_COMMAND); 261 val &= 0xffff0000; 262 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 263 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 264 writel(val, rk_pcie->dbi_base + PCI_COMMAND); 265 266 /* program correct class for RC */ 267 writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE); 268 /* Better disable write permission right after the update */ 269 270 val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 271 val |= PORT_LOGIC_SPEED_CHANGE; 272 writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 273 274 rk_pcie_dbi_write_enable(rk_pcie, false); 275 } 276 277 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed) 278 { 279 u32 val; 280 281 rk_pcie_dbi_write_enable(pci, true); 282 283 val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY); 284 val &= ~TARGET_LINK_SPEED_MASK; 285 val |= cap_speed; 286 writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY); 287 288 val = readl(pci->dbi_base + PCIE_LINK_CTL_2); 289 val &= ~TARGET_LINK_SPEED_MASK; 290 val |= cap_speed; 291 writel(val, pci->dbi_base + PCIE_LINK_CTL_2); 292 293 rk_pcie_dbi_write_enable(pci, false); 294 } 295 296 static void rk_pcie_prog_outbound_atu_unroll(struct rk_pcie *pci, int index, 297 int type, u64 cpu_addr, 298 u64 pci_addr, u32 size) 299 { 300 u32 retries, val; 301 302 dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n", 303 index, type, cpu_addr, pci_addr, size); 304 305 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, 306 lower_32_bits(cpu_addr)); 307 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, 308 upper_32_bits(cpu_addr)); 309 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, 310 lower_32_bits(cpu_addr + size - 1)); 311 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, 312 lower_32_bits(pci_addr)); 313 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, 314 upper_32_bits(pci_addr)); 315 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, 316 type); 317 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, 318 PCIE_ATU_ENABLE); 319 320 /* 321 * Make sure ATU enable takes effect before any subsequent config 322 * and I/O accesses. 323 */ 324 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 325 val = rk_pcie_readl_ob_unroll(pci, index, 326 PCIE_ATU_UNR_REGION_CTRL2); 327 if (val & PCIE_ATU_ENABLE) 328 return; 329 330 udelay(LINK_WAIT_IATU); 331 } 332 dev_err(pci->dev, "outbound iATU is not being enabled\n"); 333 } 334 335 static int rk_pcie_addr_valid(pci_dev_t d, int first_busno) 336 { 337 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) 338 return 0; 339 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) 340 return 0; 341 342 return 1; 343 } 344 345 static uintptr_t set_cfg_address(struct rk_pcie *pcie, 346 pci_dev_t d, uint where) 347 { 348 int bus = PCI_BUS(d) - pcie->first_busno; 349 uintptr_t va_address; 350 u32 atu_type; 351 352 /* Use dbi_base for own configuration read and write */ 353 if (!bus) { 354 va_address = (uintptr_t)pcie->dbi_base; 355 goto out; 356 } 357 358 if (bus == 1) 359 /* 360 * For local bus whose primary bus number is root bridge, 361 * change TLP Type field to 4. 362 */ 363 atu_type = PCIE_ATU_TYPE_CFG0; 364 else 365 /* Otherwise, change TLP Type field to 5. */ 366 atu_type = PCIE_ATU_TYPE_CFG1; 367 368 /* 369 * Not accessing root port configuration space? 370 * Region #0 is used for Outbound CFG space access. 371 * Direction = Outbound 372 * Region Index = 0 373 */ 374 d = PCI_MASK_BUS(d); 375 d = PCI_ADD_BUS(bus, d); 376 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 377 atu_type, (u64)pcie->cfg_base, 378 d << 8, pcie->cfg_size); 379 380 va_address = (uintptr_t)pcie->cfg_base; 381 382 out: 383 va_address += where & ~0x3; 384 385 return va_address; 386 } 387 388 static int rockchip_pcie_rd_conf(struct udevice *bus, pci_dev_t bdf, 389 uint offset, ulong *valuep, 390 enum pci_size_t size) 391 { 392 struct rk_pcie *pcie = dev_get_priv(bus); 393 uintptr_t va_address; 394 ulong value; 395 396 debug("PCIE CFG read: bdf=%2x:%2x:%2x\n", 397 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 398 399 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 400 debug("- out of range\n"); 401 *valuep = pci_get_ff(size); 402 return 0; 403 } 404 405 va_address = set_cfg_address(pcie, bdf, offset); 406 407 value = readl(va_address); 408 409 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 410 *valuep = pci_conv_32_to_size(value, offset, size); 411 412 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 413 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 414 pcie->io.bus_start, pcie->io.size); 415 416 return 0; 417 } 418 419 static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf, 420 uint offset, ulong value, 421 enum pci_size_t size) 422 { 423 struct rk_pcie *pcie = dev_get_priv(bus); 424 uintptr_t va_address; 425 ulong old; 426 427 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d)\n", 428 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 429 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 430 431 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 432 debug("- out of range\n"); 433 return 0; 434 } 435 436 va_address = set_cfg_address(pcie, bdf, offset); 437 438 old = readl(va_address); 439 value = pci_conv_size_to_32(old, value, offset, size); 440 writel(value, va_address); 441 442 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 443 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 444 pcie->io.bus_start, pcie->io.size); 445 446 return 0; 447 } 448 449 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie) 450 { 451 #if RK_PCIE_DBG 452 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0, 453 PCIE_CLIENT_DBG_TRANSITION_DATA); 454 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1, 455 PCIE_CLIENT_DBG_TRANSITION_DATA); 456 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0, 457 PCIE_CLIENT_DBG_TRANSITION_DATA); 458 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1, 459 PCIE_CLIENT_DBG_TRANSITION_DATA); 460 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON, 461 PCIE_CLIENT_DBF_EN); 462 #endif 463 } 464 465 static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie) 466 { 467 #if RK_PCIE_DBG 468 u32 loop; 469 470 dev_info(rk_pcie->dev, "ltssm = 0x%x\n", 471 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); 472 for (loop = 0; loop < 64; loop++) 473 dev_info(rk_pcie->dev, "fifo_status = 0x%x\n", 474 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS)); 475 #endif 476 } 477 478 static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie) 479 { 480 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0); 481 } 482 483 static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie) 484 { 485 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008); 486 } 487 488 static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie) 489 { 490 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c); 491 } 492 493 static int is_link_up(struct rk_pcie *priv) 494 { 495 u32 val; 496 497 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS); 498 if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 && 499 (val & GENMASK(5, 0)) == 0x11) 500 return 1; 501 502 return 0; 503 } 504 505 static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) 506 { 507 int retries; 508 509 if (is_link_up(priv)) { 510 printf("PCI Link already up before configuration!\n"); 511 return 1; 512 } 513 514 /* DW pre link configurations */ 515 rk_pcie_configure(priv, cap_speed); 516 517 /* Rest the device */ 518 if (dm_gpio_is_valid(&priv->rst_gpio)) { 519 dm_gpio_set_value(&priv->rst_gpio, 0); 520 msleep(1000); 521 dm_gpio_set_value(&priv->rst_gpio, 1); 522 } 523 524 rk_pcie_disable_ltssm(priv); 525 rk_pcie_link_status_clear(priv); 526 rk_pcie_enable_debug(priv); 527 528 /* Enable LTSSM */ 529 rk_pcie_enable_ltssm(priv); 530 531 for (retries = 0; retries < 10000000; retries++) { 532 if (is_link_up(priv)) { 533 dev_info(priv->dev, "PCIe Link up, LTSSM is 0x%x\n", 534 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 535 rk_pcie_debug_dump(priv); 536 return 0; 537 } 538 539 dev_info(priv->dev, "PCIe Linking... LTSSM is 0x%x\n", 540 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 541 rk_pcie_debug_dump(priv); 542 msleep(1000); 543 } 544 545 dev_err(priv->dev, "PCIe-%d Link Fail\n", priv->dev->seq); 546 /* Link maybe in Gen switch recovery but we need to wait more 1s */ 547 msleep(1000); 548 return -EINVAL; 549 } 550 551 static int rockchip_pcie_init_port(struct udevice *dev) 552 { 553 int ret; 554 u32 val; 555 struct rk_pcie *priv = dev_get_priv(dev); 556 557 /* Set power and maybe external ref clk input */ 558 if (priv->vpcie3v3) { 559 ret = regulator_set_value(priv->vpcie3v3, 3300000); 560 if (ret) { 561 dev_err(priv->dev, "failed to enable vpcie3v3 (ret=%d)\n", 562 ret); 563 return ret; 564 } 565 } 566 567 msleep(1000); 568 569 ret = generic_phy_init(&priv->phy); 570 if (ret) { 571 dev_err(dev, "failed to init phy (ret=%d)\n", ret); 572 return ret; 573 } 574 575 ret = generic_phy_power_on(&priv->phy); 576 if (ret) { 577 dev_err(dev, "failed to power on phy (ret=%d)\n", ret); 578 goto err_exit_phy; 579 } 580 581 ret = reset_deassert_bulk(&priv->rsts); 582 if (ret) { 583 dev_err(dev, "failed to deassert resets (ret=%d)\n", ret); 584 goto err_power_off_phy; 585 } 586 587 ret = clk_enable_bulk(&priv->clks); 588 if (ret) { 589 dev_err(dev, "failed to enable clks (ret=%d)\n", ret); 590 goto err_deassert_bulk; 591 } 592 593 /* LTSSM EN ctrl mode */ 594 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL); 595 val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); 596 rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val); 597 598 /* Set RC mode */ 599 rk_pcie_writel_apb(priv, 0x0, 0xf00040); 600 rk_pcie_setup_host(priv); 601 602 ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3); 603 if (ret < 0) 604 goto err_link_up; 605 606 return 0; 607 err_link_up: 608 clk_disable_bulk(&priv->clks); 609 err_deassert_bulk: 610 reset_assert_bulk(&priv->rsts); 611 err_power_off_phy: 612 generic_phy_power_off(&priv->phy); 613 err_exit_phy: 614 generic_phy_exit(&priv->phy); 615 return ret; 616 } 617 618 static int rockchip_pcie_parse_dt(struct udevice *dev) 619 { 620 struct rk_pcie *priv = dev_get_priv(dev); 621 int ret; 622 623 priv->dbi_base = (void *)dev_read_addr_index(dev, 0); 624 if (!priv->dbi_base) 625 return -ENODEV; 626 627 dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base); 628 629 priv->apb_base = (void *)dev_read_addr_index(dev, 1); 630 if (!priv->apb_base) 631 return -ENODEV; 632 633 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); 634 635 ret = gpio_request_by_name(dev, "reset-gpios", 0, 636 &priv->rst_gpio, GPIOD_IS_OUT); 637 if (ret) { 638 dev_err(dev, "failed to find reset-gpios property\n"); 639 return ret; 640 } 641 642 ret = reset_get_bulk(dev, &priv->rsts); 643 if (ret) { 644 dev_err(dev, "Can't get reset: %d\n", ret); 645 return ret; 646 } 647 648 ret = clk_get_bulk(dev, &priv->clks); 649 if (ret) { 650 dev_err(dev, "Can't get clock: %d\n", ret); 651 return ret; 652 } 653 654 ret = device_get_supply_regulator(dev, "vpcie3v3-supply", 655 &priv->vpcie3v3); 656 if (ret && ret != -ENOENT) { 657 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret); 658 return ret; 659 } 660 661 ret = generic_phy_get_by_index(dev, 0, &priv->phy); 662 if (ret) { 663 dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret); 664 return ret; 665 } 666 667 return 0; 668 } 669 670 static int rockchip_pcie_probe(struct udevice *dev) 671 { 672 struct rk_pcie *priv = dev_get_priv(dev); 673 struct udevice *ctlr = pci_get_controller(dev); 674 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 675 int ret; 676 677 priv->first_busno = dev->seq; 678 priv->dev = dev; 679 680 ret = rockchip_pcie_parse_dt(dev); 681 if (ret) 682 return ret; 683 684 ret = rockchip_pcie_init_port(dev); 685 if (ret) 686 return ret; 687 688 dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", 689 dev->seq, rk_pcie_get_link_speed(priv), 690 rk_pcie_get_link_width(priv), 691 hose->first_busno); 692 693 for (ret = 0; ret < hose->region_count; ret++) { 694 if (hose->regions[ret].flags == PCI_REGION_IO) { 695 priv->io.phys_start = hose->regions[ret].phys_start; /* IO base */ 696 priv->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */ 697 priv->io.size = hose->regions[ret].size; /* IO size */ 698 } else if (hose->regions[ret].flags == PCI_REGION_MEM) { 699 priv->mem.phys_start = hose->regions[ret].phys_start; /* MEM base */ 700 priv->mem.bus_start = hose->regions[ret].bus_start; /* MEM_bus_addr */ 701 priv->mem.size = hose->regions[ret].size; /* MEM size */ 702 } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { 703 priv->cfg_base = (void *)(priv->io.phys_start - priv->io.size); 704 priv->cfg_size = priv->io.size; 705 } else { 706 dev_err(dev, "invalid flags type!\n"); 707 } 708 } 709 710 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 711 priv->cfg_base, priv->cfg_base + priv->cfg_size, 712 priv->cfg_size); 713 714 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%x]\n", 715 priv->io.phys_start, priv->io.phys_start + priv->io.size, 716 priv->io.size); 717 718 dev_dbg(dev, "IO bus: [0x%x - 0x%x, size 0x%x]\n", 719 priv->io.bus_start, priv->io.bus_start + priv->io.size, 720 priv->io.size); 721 722 dev_dbg(dev, "MEM space: [0x%llx - 0x%llx, size 0x%x]\n", 723 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 724 priv->mem.size); 725 726 dev_dbg(dev, "MEM bus: [0x%x - 0x%x, size 0x%x]\n", 727 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 728 priv->mem.size); 729 730 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX0, 731 PCIE_ATU_TYPE_MEM, 732 priv->mem.phys_start, 733 priv->mem.bus_start, priv->mem.size); 734 return 0; 735 } 736 737 static const struct dm_pci_ops rockchip_pcie_ops = { 738 .read_config = rockchip_pcie_rd_conf, 739 .write_config = rockchip_pcie_wr_conf, 740 }; 741 742 static const struct udevice_id rockchip_pcie_ids[] = { 743 { .compatible = "rockchip,rk3568-pcie" }, 744 { } 745 }; 746 747 U_BOOT_DRIVER(rockchip_pcie) = { 748 .name = "pcie_dw_rockchip", 749 .id = UCLASS_PCI, 750 .of_match = rockchip_pcie_ids, 751 .ops = &rockchip_pcie_ops, 752 .probe = rockchip_pcie_probe, 753 .priv_auto_alloc_size = sizeof(struct rk_pcie), 754 }; 755